| blob | dc4254b8cbbc2075bf1bb2debadd4587d3721b1f |
1 /*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
14 #ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H
15 #define _DT_BINDINGS_CLK_GCC_IPQ806X_H
17 #define AFAB_CLK_SRC 0
18 #define QDSS_STM_CLK 1
19 #define SCSS_A_CLK 2
20 #define SCSS_H_CLK 3
21 #define AFAB_CORE_CLK 4
22 #define SCSS_XO_SRC_CLK 5
23 #define AFAB_EBI1_CH0_A_CLK 6
24 #define AFAB_EBI1_CH1_A_CLK 7
25 #define AFAB_AXI_S0_FCLK 8
26 #define AFAB_AXI_S1_FCLK 9
27 #define AFAB_AXI_S2_FCLK 10
28 #define AFAB_AXI_S3_FCLK 11
29 #define AFAB_AXI_S4_FCLK 12
30 #define SFAB_CORE_CLK 13
31 #define SFAB_AXI_S0_FCLK 14
32 #define SFAB_AXI_S1_FCLK 15
33 #define SFAB_AXI_S2_FCLK 16
34 #define SFAB_AXI_S3_FCLK 17
35 #define SFAB_AXI_S4_FCLK 18
36 #define SFAB_AXI_S5_FCLK 19
37 #define SFAB_AHB_S0_FCLK 20
38 #define SFAB_AHB_S1_FCLK 21
39 #define SFAB_AHB_S2_FCLK 22
40 #define SFAB_AHB_S3_FCLK 23
41 #define SFAB_AHB_S4_FCLK 24
42 #define SFAB_AHB_S5_FCLK 25
43 #define SFAB_AHB_S6_FCLK 26
44 #define SFAB_AHB_S7_FCLK 27
45 #define QDSS_AT_CLK_SRC 28
46 #define QDSS_AT_CLK 29
47 #define QDSS_TRACECLKIN_CLK_SRC 30
48 #define QDSS_TRACECLKIN_CLK 31
49 #define QDSS_TSCTR_CLK_SRC 32
50 #define QDSS_TSCTR_CLK 33
51 #define SFAB_ADM0_M0_A_CLK 34
52 #define SFAB_ADM0_M1_A_CLK 35
53 #define SFAB_ADM0_M2_H_CLK 36
54 #define ADM0_CLK 37
55 #define ADM0_PBUS_CLK 38
56 #define IMEM0_A_CLK 39
57 #define QDSS_H_CLK 40
58 #define PCIE_A_CLK 41
59 #define PCIE_AUX_CLK 42
60 #define PCIE_H_CLK 43
61 #define PCIE_PHY_CLK 44
62 #define SFAB_CLK_SRC 45
63 #define SFAB_LPASS_Q6_A_CLK 46
64 #define SFAB_AFAB_M_A_CLK 47
65 #define AFAB_SFAB_M0_A_CLK 48
66 #define AFAB_SFAB_M1_A_CLK 49
67 #define SFAB_SATA_S_H_CLK 50
68 #define DFAB_CLK_SRC 51
69 #define DFAB_CLK 52
70 #define SFAB_DFAB_M_A_CLK 53
71 #define DFAB_SFAB_M_A_CLK 54
72 #define DFAB_SWAY0_H_CLK 55
73 #define DFAB_SWAY1_H_CLK 56
74 #define DFAB_ARB0_H_CLK 57
75 #define DFAB_ARB1_H_CLK 58
76 #define PPSS_H_CLK 59
77 #define PPSS_PROC_CLK 60
78 #define PPSS_TIMER0_CLK 61
79 #define PPSS_TIMER1_CLK 62
80 #define PMEM_A_CLK 63
81 #define DMA_BAM_H_CLK 64
82 #define SIC_H_CLK 65
83 #define SPS_TIC_H_CLK 66
84 #define CFPB_2X_CLK_SRC 67
85 #define CFPB_CLK 68
86 #define CFPB0_H_CLK 69
87 #define CFPB1_H_CLK 70
88 #define CFPB2_H_CLK 71
89 #define SFAB_CFPB_M_H_CLK 72
90 #define CFPB_MASTER_H_CLK 73
91 #define SFAB_CFPB_S_H_CLK 74
92 #define CFPB_SPLITTER_H_CLK 75
93 #define TSIF_H_CLK 76
94 #define TSIF_INACTIVITY_TIMERS_CLK 77
95 #define TSIF_REF_SRC 78
96 #define TSIF_REF_CLK 79
97 #define CE1_H_CLK 80
98 #define CE1_CORE_CLK 81
99 #define CE1_SLEEP_CLK 82
100 #define CE2_H_CLK 83
101 #define CE2_CORE_CLK 84
102 #define SFPB_H_CLK_SRC 85
103 #define SFPB_H_CLK 86
104 #define SFAB_SFPB_M_H_CLK 87
105 #define SFAB_SFPB_S_H_CLK 88
106 #define RPM_PROC_CLK 89
107 #define RPM_BUS_H_CLK 90
108 #define RPM_SLEEP_CLK 91
109 #define RPM_TIMER_CLK 92
110 #define RPM_MSG_RAM_H_CLK 93
111 #define PMIC_ARB0_H_CLK 94
112 #define PMIC_ARB1_H_CLK 95
113 #define PMIC_SSBI2_SRC 96
114 #define PMIC_SSBI2_CLK 97
115 #define SDC1_H_CLK 98
116 #define SDC2_H_CLK 99
117 #define SDC3_H_CLK 100
118 #define SDC4_H_CLK 101
119 #define SDC1_SRC 102
120 #define SDC1_CLK 103
121 #define SDC2_SRC 104
122 #define SDC2_CLK 105
123 #define SDC3_SRC 106
124 #define SDC3_CLK 107
125 #define SDC4_SRC 108
126 #define SDC4_CLK 109
127 #define USB_HS1_H_CLK 110
128 #define USB_HS1_XCVR_SRC 111
129 #define USB_HS1_XCVR_CLK 112
130 #define USB_HSIC_H_CLK 113
131 #define USB_HSIC_XCVR_SRC 114
132 #define USB_HSIC_XCVR_CLK 115
133 #define USB_HSIC_SYSTEM_CLK_SRC 116
134 #define USB_HSIC_SYSTEM_CLK 117
135 #define CFPB0_C0_H_CLK 118
136 #define CFPB0_D0_H_CLK 119
137 #define CFPB0_C1_H_CLK 120
138 #define CFPB0_D1_H_CLK 121
139 #define USB_FS1_H_CLK 122
140 #define USB_FS1_XCVR_SRC 123
141 #define USB_FS1_XCVR_CLK 124
142 #define USB_FS1_SYSTEM_CLK 125
143 #define GSBI_COMMON_SIM_SRC 126
144 #define GSBI1_H_CLK 127
145 #define GSBI2_H_CLK 128
146 #define GSBI3_H_CLK 129
147 #define GSBI4_H_CLK 130
148 #define GSBI5_H_CLK 131
149 #define GSBI6_H_CLK 132
150 #define GSBI7_H_CLK 133
151 #define GSBI1_QUP_SRC 134
152 #define GSBI1_QUP_CLK 135
153 #define GSBI2_QUP_SRC 136
154 #define GSBI2_QUP_CLK 137
155 #define GSBI3_QUP_SRC 138
156 #define GSBI3_QUP_CLK 139
157 #define GSBI4_QUP_SRC 140
158 #define GSBI4_QUP_CLK 141
159 #define GSBI5_QUP_SRC 142
160 #define GSBI5_QUP_CLK 143
161 #define GSBI6_QUP_SRC 144
162 #define GSBI6_QUP_CLK 145
163 #define GSBI7_QUP_SRC 146
164 #define GSBI7_QUP_CLK 147
165 #define GSBI1_UART_SRC 148
166 #define GSBI1_UART_CLK 149
167 #define GSBI2_UART_SRC 150
168 #define GSBI2_UART_CLK 151
169 #define GSBI3_UART_SRC 152
170 #define GSBI3_UART_CLK 153
171 #define GSBI4_UART_SRC 154
172 #define GSBI4_UART_CLK 155
173 #define GSBI5_UART_SRC 156
174 #define GSBI5_UART_CLK 157
175 #define GSBI6_UART_SRC 158
176 #define GSBI6_UART_CLK 159
177 #define GSBI7_UART_SRC 160
178 #define GSBI7_UART_CLK 161
179 #define GSBI1_SIM_CLK 162
180 #define GSBI2_SIM_CLK 163
181 #define GSBI3_SIM_CLK 164
182 #define GSBI4_SIM_CLK 165
183 #define GSBI5_SIM_CLK 166
184 #define GSBI6_SIM_CLK 167
185 #define GSBI7_SIM_CLK 168
186 #define USB_HSIC_HSIC_CLK_SRC 169
187 #define USB_HSIC_HSIC_CLK 170
188 #define USB_HSIC_HSIO_CAL_CLK 171
189 #define SPDM_CFG_H_CLK 172
190 #define SPDM_MSTR_H_CLK 173
191 #define SPDM_FF_CLK_SRC 174
192 #define SPDM_FF_CLK 175
193 #define SEC_CTRL_CLK 176
194 #define SEC_CTRL_ACC_CLK_SRC 177
195 #define SEC_CTRL_ACC_CLK 178
196 #define TLMM_H_CLK 179
197 #define TLMM_CLK 180
198 #define SATA_H_CLK 181
199 #define SATA_CLK_SRC 182
200 #define SATA_RXOOB_CLK 183
201 #define SATA_PMALIVE_CLK 184
202 #define SATA_PHY_REF_CLK 185
203 #define SATA_A_CLK 186
204 #define SATA_PHY_CFG_CLK 187
205 #define TSSC_CLK_SRC 188
206 #define TSSC_CLK 189
207 #define PDM_SRC 190
208 #define PDM_CLK 191
209 #define GP0_SRC 192
210 #define GP0_CLK 193
211 #define GP1_SRC 194
212 #define GP1_CLK 195
213 #define GP2_SRC 196
214 #define GP2_CLK 197
215 #define MPM_CLK 198
216 #define EBI1_CLK_SRC 199
217 #define EBI1_CH0_CLK 200
218 #define EBI1_CH1_CLK 201
219 #define EBI1_2X_CLK 202
220 #define EBI1_CH0_DQ_CLK 203
221 #define EBI1_CH1_DQ_CLK 204
222 #define EBI1_CH0_CA_CLK 205
223 #define EBI1_CH1_CA_CLK 206
224 #define EBI1_XO_CLK 207
225 #define SFAB_SMPSS_S_H_CLK 208
226 #define PRNG_SRC 209
227 #define PRNG_CLK 210
228 #define PXO_SRC 211
229 #define SPDM_CY_PORT0_CLK 212
230 #define SPDM_CY_PORT1_CLK 213
231 #define SPDM_CY_PORT2_CLK 214
232 #define SPDM_CY_PORT3_CLK 215
233 #define SPDM_CY_PORT4_CLK 216
234 #define SPDM_CY_PORT5_CLK 217
235 #define SPDM_CY_PORT6_CLK 218
236 #define SPDM_CY_PORT7_CLK 219
237 #define PLL0 220
238 #define PLL0_VOTE 221
239 #define PLL3 222
240 #define PLL3_VOTE 223
241 #define PLL4_VOTE 225
242 #define PLL8 226
243 #define PLL8_VOTE 227
244 #define PLL9 228
245 #define PLL10 229
246 #define PLL11 230
247 #define PLL12 231
248 #define PLL14 232
249 #define PLL14_VOTE 233
250 #define PLL18 234
251 #define CE5_SRC 235
252 #define CE5_H_CLK 236
253 #define CE5_CORE_CLK 237
254 #define CE3_SLEEP_CLK 238
255 #define SFAB_AHB_S8_FCLK 239
256 #define SPDM_CY_PORT8_CLK 246
257 #define PCIE_ALT_REF_SRC 247
258 #define PCIE_ALT_REF_CLK 248
259 #define PCIE_1_A_CLK 249
260 #define PCIE_1_AUX_CLK 250
261 #define PCIE_1_H_CLK 251
262 #define PCIE_1_PHY_CLK 252
263 #define PCIE_1_ALT_REF_SRC 253
264 #define PCIE_1_ALT_REF_CLK 254
265 #define PCIE_2_A_CLK 255
266 #define PCIE_2_AUX_CLK 256
267 #define PCIE_2_H_CLK 257
268 #define PCIE_2_PHY_CLK 258
269 #define PCIE_2_ALT_REF_SRC 259
270 #define PCIE_2_ALT_REF_CLK 260
271 #define EBI2_CLK 261
272 #define USB30_SLEEP_CLK 262
273 #define USB30_UTMI_SRC 263
274 #define USB30_0_UTMI_CLK 264
275 #define USB30_1_UTMI_CLK 265
276 #define USB30_MASTER_SRC 266
277 #define USB30_0_MASTER_CLK 267
278 #define USB30_1_MASTER_CLK 268
279 #define GMAC_CORE1_CLK_SRC 269
280 #define GMAC_CORE2_CLK_SRC 270
281 #define GMAC_CORE3_CLK_SRC 271
282 #define GMAC_CORE4_CLK_SRC 272
283 #define GMAC_CORE1_CLK 273
284 #define GMAC_CORE2_CLK 274
285 #define GMAC_CORE3_CLK 275
286 #define GMAC_CORE4_CLK 276
287 #define UBI32_CORE1_CLK_SRC 277
288 #define UBI32_CORE2_CLK_SRC 278
289 #define UBI32_CORE1_CLK 279
290 #define UBI32_CORE2_CLK 280
291 #define EBI2_AON_CLK 281
292 #define NSSTCM_CLK_SRC 282
293 #define NSSTCM_CLK 283
295 #endif