include/dt-bindings/clock/rk3036-cru.h

   1 /*
   2  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
   3  * Author: Xing Zheng <zhengxing@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
  17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
  18
  19 /* core clocks */
  20 #define PLL_APLL                1
  21 #define PLL_DPLL                2
  22 #define PLL_GPLL                3
  23 #define ARMCLK                  4
  24
  25 /* sclk gates (special clocks) */
  26 #define SCLK_GPU                64
  27 #define SCLK_SPI                65
  28 #define SCLK_SDMMC              68
  29 #define SCLK_SDIO               69
  30 #define SCLK_EMMC               71
  31 #define SCLK_NANDC              76
  32 #define SCLK_UART0              77
  33 #define SCLK_UART1              78
  34 #define SCLK_UART2              79
  35 #define SCLK_I2S                82
  36 #define SCLK_SPDIF              83
  37 #define SCLK_TIMER0             85
  38 #define SCLK_TIMER1             86
  39 #define SCLK_TIMER2             87
  40 #define SCLK_TIMER3             88
  41 #define SCLK_OTGPHY0            93
  42 #define SCLK_LCDC               100
  43 #define SCLK_HDMI               109
  44 #define SCLK_HEVC               111
  45 #define SCLK_I2S_OUT            113
  46 #define SCLK_SDMMC_DRV          114
  47 #define SCLK_SDIO_DRV           115
  48 #define SCLK_EMMC_DRV           117
  49 #define SCLK_SDMMC_SAMPLE       118
  50 #define SCLK_SDIO_SAMPLE        119
  51 #define SCLK_EMMC_SAMPLE        121
  52 #define SCLK_PVTM_CORE          123
  53 #define SCLK_PVTM_GPU           124
  54 #define SCLK_PVTM_VIDEO         125
  55 #define SCLK_MAC                151
  56 #define SCLK_MACREF             152
  57 #define SCLK_SFC                160
  58
  59 /* aclk gates */
  60 #define ACLK_DMAC2              194
  61 #define ACLK_LCDC               197
  62 #define ACLK_VIO                203
  63 #define ACLK_VCODEC             208
  64 #define ACLK_CPU                209
  65 #define ACLK_PERI               210
  66
  67 /* pclk gates */
  68 #define PCLK_GPIO0              320
  69 #define PCLK_GPIO1              321
  70 #define PCLK_GPIO2              322
  71 #define PCLK_GRF                329
  72 #define PCLK_I2C0               332
  73 #define PCLK_I2C1               333
  74 #define PCLK_I2C2               334
  75 #define PCLK_SPI                338
  76 #define PCLK_UART0              341
  77 #define PCLK_UART1              342
  78 #define PCLK_UART2              343
  79 #define PCLK_PWM                350
  80 #define PCLK_TIMER              353
  81 #define PCLK_HDMI               360
  82 #define PCLK_CPU                362
  83 #define PCLK_PERI               363
  84 #define PCLK_DDRUPCTL           364
  85 #define PCLK_WDT                368
  86 #define PCLK_ACODEC             369
  87
  88 /* hclk gates */
  89 #define HCLK_OTG0               449
  90 #define HCLK_OTG1               450
  91 #define HCLK_NANDC              453
  92 #define HCLK_SDMMC              456
  93 #define HCLK_SDIO               457
  94 #define HCLK_EMMC               459
  95 #define HCLK_I2S                462
  96 #define HCLK_LCDC               465
  97 #define HCLK_ROM                467
  98 #define HCLK_VIO_BUS            472
  99 #define HCLK_VCODEC             476
 100 #define HCLK_CPU                477
 101 #define HCLK_PERI               478
 102
 103 #define CLK_NR_CLKS             (HCLK_PERI + 1)
 104
 105 /* soft-reset indices */
 106 #define SRST_CORE0              0
 107 #define SRST_CORE1              1
 108 #define SRST_CORE0_DBG          4
 109 #define SRST_CORE1_DBG          5
 110 #define SRST_CORE0_POR          8
 111 #define SRST_CORE1_POR          9
 112 #define SRST_L2C                12
 113 #define SRST_TOPDBG             13
 114 #define SRST_STRC_SYS_A         14
 115 #define SRST_PD_CORE_NIU        15
 116
 117 #define SRST_TIMER2             16
 118 #define SRST_CPUSYS_H           17
 119 #define SRST_AHB2APB_H          19
 120 #define SRST_TIMER3             20
 121 #define SRST_INTMEM             21
 122 #define SRST_ROM                22
 123 #define SRST_PERI_NIU           23
 124 #define SRST_I2S                24
 125 #define SRST_DDR_PLL            25
 126 #define SRST_GPU_DLL            26
 127 #define SRST_TIMER0             27
 128 #define SRST_TIMER1             28
 129 #define SRST_CORE_DLL           29
 130 #define SRST_EFUSE_P            30
 131 #define SRST_ACODEC_P           31
 132
 133 #define SRST_GPIO0              32
 134 #define SRST_GPIO1              33
 135 #define SRST_GPIO2              34
 136 #define SRST_UART0              39
 137 #define SRST_UART1              40
 138 #define SRST_UART2              41
 139 #define SRST_I2C0               43
 140 #define SRST_I2C1               44
 141 #define SRST_I2C2               45
 142 #define SRST_SFC                47
 143
 144 #define SRST_PWM0               48
 145 #define SRST_DAP                51
 146 #define SRST_DAP_SYS            52
 147 #define SRST_GRF                55
 148 #define SRST_PERIPHSYS_A        57
 149 #define SRST_PERIPHSYS_H        58
 150 #define SRST_PERIPHSYS_P        59
 151 #define SRST_CPU_PERI           61
 152 #define SRST_EMEM_PERI          62
 153 #define SRST_USB_PERI           63
 154
 155 #define SRST_DMA2               64
 156 #define SRST_MAC                66
 157 #define SRST_NANDC              68
 158 #define SRST_USBOTG0            69
 159 #define SRST_OTGC0              71
 160 #define SRST_USBOTG1            72
 161 #define SRST_OTGC1              74
 162 #define SRST_DDRMSCH            79
 163
 164 #define SRST_MMC0               81
 165 #define SRST_SDIO               82
 166 #define SRST_EMMC               83
 167 #define SRST_SPI0               84
 168 #define SRST_WDT                86
 169 #define SRST_DDRPHY             88
 170 #define SRST_DDRPHY_P           89
 171 #define SRST_DDRCTRL            90
 172 #define SRST_DDRCTRL_P          91
 173
 174 #define SRST_HDMI_P             96
 175 #define SRST_VIO_BUS_H          99
 176 #define SRST_UTMI0              103
 177 #define SRST_UTMI1              104
 178 #define SRST_USBPOR             105
 179
 180 #define SRST_VCODEC_A           112
 181 #define SRST_VCODEC_H           113
 182 #define SRST_VIO1_A             114
 183 #define SRST_HEVC               115
 184 #define SRST_VCODEC_NIU_A       116
 185 #define SRST_LCDC1_A            117
 186 #define SRST_LCDC1_H            118
 187 #define SRST_LCDC1_D            119
 188 #define SRST_GPU                120
 189 #define SRST_GPU_NIU_A          122
 190
 191 #define SRST_DBG_P              131
 192
 193 #endif