include/dt-bindings/clock/tegra114-car.h

   1 /*
   2  * This header provides constants for binding nvidia,tegra114-car.
   3  *
   4  * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
   5  * registers. These IDs often match those in the CAR's RST_DEVICES registers,
   6  * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
   7  * this case, those clocks are assigned IDs above 160 in order to highlight
   8  * this issue. Implementations that interpret these clock IDs as bit values
   9  * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
  10  * explicitly handle these special cases.
  11  *
  12  * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
  13  * above.
  14  */
  15
  16 #ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
  17 #define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
  18
  19 /* 0 */
  20 /* 1 */
  21 /* 2 */
  22 /* 3 */
  23 #define TEGRA114_CLK_RTC 4
  24 #define TEGRA114_CLK_TIMER 5
  25 #define TEGRA114_CLK_UARTA 6
  26 /* 7 (register bit affects uartb and vfir) */
  27 /* 8 */
  28 #define TEGRA114_CLK_SDMMC2 9
  29 /* 10 (register bit affects spdif_in and spdif_out) */
  30 #define TEGRA114_CLK_I2S1 11
  31 #define TEGRA114_CLK_I2C1 12
  32 #define TEGRA114_CLK_NDFLASH 13
  33 #define TEGRA114_CLK_SDMMC1 14
  34 #define TEGRA114_CLK_SDMMC4 15
  35 /* 16 */
  36 #define TEGRA114_CLK_PWM 17
  37 #define TEGRA114_CLK_I2S2 18
  38 #define TEGRA114_CLK_EPP 19
  39 /* 20 (register bit affects vi and vi_sensor) */
  40 #define TEGRA114_CLK_GR2D 21
  41 #define TEGRA114_CLK_USBD 22
  42 #define TEGRA114_CLK_ISP 23
  43 #define TEGRA114_CLK_GR3D 24
  44 /* 25 */
  45 #define TEGRA114_CLK_DISP2 26
  46 #define TEGRA114_CLK_DISP1 27
  47 #define TEGRA114_CLK_HOST1X 28
  48 #define TEGRA114_CLK_VCP 29
  49 #define TEGRA114_CLK_I2S0 30
  50 /* 31 */
  51
  52 #define TEGRA114_CLK_MC 32
  53 /* 33 */
  54 #define TEGRA114_CLK_APBDMA 34
  55 /* 35 */
  56 #define TEGRA114_CLK_KBC 36
  57 /* 37 */
  58 /* 38 */
  59 /* 39 (register bit affects fuse and fuse_burn) */
  60 #define TEGRA114_CLK_KFUSE 40
  61 #define TEGRA114_CLK_SBC1 41
  62 #define TEGRA114_CLK_NOR 42
  63 /* 43 */
  64 #define TEGRA114_CLK_SBC2 44
  65 /* 45 */
  66 #define TEGRA114_CLK_SBC3 46
  67 #define TEGRA114_CLK_I2C5 47
  68 #define TEGRA114_CLK_DSIA 48
  69 /* 49 */
  70 #define TEGRA114_CLK_MIPI 50
  71 #define TEGRA114_CLK_HDMI 51
  72 #define TEGRA114_CLK_CSI 52
  73 /* 53 */
  74 #define TEGRA114_CLK_I2C2 54
  75 #define TEGRA114_CLK_UARTC 55
  76 #define TEGRA114_CLK_MIPI_CAL 56
  77 #define TEGRA114_CLK_EMC 57
  78 #define TEGRA114_CLK_USB2 58
  79 #define TEGRA114_CLK_USB3 59
  80 /* 60 */
  81 #define TEGRA114_CLK_VDE 61
  82 #define TEGRA114_CLK_BSEA 62
  83 #define TEGRA114_CLK_BSEV 63
  84
  85 /* 64 */
  86 #define TEGRA114_CLK_UARTD 65
  87 /* 66 */
  88 #define TEGRA114_CLK_I2C3 67
  89 #define TEGRA114_CLK_SBC4 68
  90 #define TEGRA114_CLK_SDMMC3 69
  91 /* 70 */
  92 #define TEGRA114_CLK_OWR 71
  93 /* 72 */
  94 #define TEGRA114_CLK_CSITE 73
  95 /* 74 */
  96 /* 75 */
  97 #define TEGRA114_CLK_LA 76
  98 #define TEGRA114_CLK_TRACE 77
  99 #define TEGRA114_CLK_SOC_THERM 78
 100 #define TEGRA114_CLK_DTV 79
 101 #define TEGRA114_CLK_NDSPEED 80
 102 #define TEGRA114_CLK_I2CSLOW 81
 103 #define TEGRA114_CLK_DSIB 82
 104 #define TEGRA114_CLK_TSEC 83
 105 /* 84 */
 106 /* 85 */
 107 /* 86 */
 108 /* 87 */
 109 /* 88 */
 110 #define TEGRA114_CLK_XUSB_HOST 89
 111 /* 90 */
 112 #define TEGRA114_CLK_MSENC 91
 113 #define TEGRA114_CLK_CSUS 92
 114 /* 93 */
 115 /* 94 */
 116 /* 95 (bit affects xusb_dev and xusb_dev_src) */
 117
 118 /* 96 */
 119 /* 97 */
 120 /* 98 */
 121 #define TEGRA114_CLK_MSELECT 99
 122 #define TEGRA114_CLK_TSENSOR 100
 123 #define TEGRA114_CLK_I2S3 101
 124 #define TEGRA114_CLK_I2S4 102
 125 #define TEGRA114_CLK_I2C4 103
 126 #define TEGRA114_CLK_SBC5 104
 127 #define TEGRA114_CLK_SBC6 105
 128 #define TEGRA114_CLK_D_AUDIO 106
 129 #define TEGRA114_CLK_APBIF 107
 130 #define TEGRA114_CLK_DAM0 108
 131 #define TEGRA114_CLK_DAM1 109
 132 #define TEGRA114_CLK_DAM2 110
 133 #define TEGRA114_CLK_HDA2CODEC_2X 111
 134 /* 112 */
 135 #define TEGRA114_CLK_AUDIO0_2X 113
 136 #define TEGRA114_CLK_AUDIO1_2X 114
 137 #define TEGRA114_CLK_AUDIO2_2X 115
 138 #define TEGRA114_CLK_AUDIO3_2X 116
 139 #define TEGRA114_CLK_AUDIO4_2X 117
 140 #define TEGRA114_CLK_SPDIF_2X 118
 141 #define TEGRA114_CLK_ACTMON 119
 142 #define TEGRA114_CLK_EXTERN1 120
 143 #define TEGRA114_CLK_EXTERN2 121
 144 #define TEGRA114_CLK_EXTERN3 122
 145 /* 123 */
 146 /* 124 */
 147 #define TEGRA114_CLK_HDA 125
 148 /* 126 */
 149 #define TEGRA114_CLK_SE 127
 150
 151 #define TEGRA114_CLK_HDA2HDMI 128
 152 /* 129 */
 153 /* 130 */
 154 /* 131 */
 155 /* 132 */
 156 /* 133 */
 157 /* 134 */
 158 /* 135 */
 159 /* 136 */
 160 /* 137 */
 161 /* 138 */
 162 /* 139 */
 163 /* 140 */
 164 /* 141 */
 165 /* 142 */
 166 /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
 167 /*      xusb_host_src and xusb_ss_src) */
 168 #define TEGRA114_CLK_CILAB 144
 169 #define TEGRA114_CLK_CILCD 145
 170 #define TEGRA114_CLK_CILE 146
 171 #define TEGRA114_CLK_DSIALP 147
 172 #define TEGRA114_CLK_DSIBLP 148
 173 /* 149 */
 174 #define TEGRA114_CLK_DDS 150
 175 /* 151 */
 176 #define TEGRA114_CLK_DP2 152
 177 #define TEGRA114_CLK_AMX 153
 178 #define TEGRA114_CLK_ADX 154
 179 /* 155 (bit affects dfll_ref and dfll_soc) */
 180 #define TEGRA114_CLK_XUSB_SS 156
 181 /* 157 */
 182 /* 158 */
 183 /* 159 */
 184
 185 /* 160 */
 186 /* 161 */
 187 /* 162 */
 188 /* 163 */
 189 /* 164 */
 190 /* 165 */
 191 /* 166 */
 192 /* 167 */
 193 /* 168 */
 194 /* 169 */
 195 /* 170 */
 196 /* 171 */
 197 /* 172 */
 198 /* 173 */
 199 /* 174 */
 200 /* 175 */
 201 /* 176 */
 202 /* 177 */
 203 /* 178 */
 204 /* 179 */
 205 /* 180 */
 206 /* 181 */
 207 /* 182 */
 208 /* 183 */
 209 /* 184 */
 210 /* 185 */
 211 /* 186 */
 212 /* 187 */
 213 /* 188 */
 214 /* 189 */
 215 /* 190 */
 216 /* 191 */
 217
 218 #define TEGRA114_CLK_UARTB 192
 219 #define TEGRA114_CLK_VFIR 193
 220 #define TEGRA114_CLK_SPDIF_IN 194
 221 #define TEGRA114_CLK_SPDIF_OUT 195
 222 #define TEGRA114_CLK_VI 196
 223 #define TEGRA114_CLK_VI_SENSOR 197
 224 #define TEGRA114_CLK_FUSE 198
 225 #define TEGRA114_CLK_FUSE_BURN 199
 226 #define TEGRA114_CLK_CLK_32K 200
 227 #define TEGRA114_CLK_CLK_M 201
 228 #define TEGRA114_CLK_CLK_M_DIV2 202
 229 #define TEGRA114_CLK_CLK_M_DIV4 203
 230 #define TEGRA114_CLK_PLL_REF 204
 231 #define TEGRA114_CLK_PLL_C 205
 232 #define TEGRA114_CLK_PLL_C_OUT1 206
 233 #define TEGRA114_CLK_PLL_C2 207
 234 #define TEGRA114_CLK_PLL_C3 208
 235 #define TEGRA114_CLK_PLL_M 209
 236 #define TEGRA114_CLK_PLL_M_OUT1 210
 237 #define TEGRA114_CLK_PLL_P 211
 238 #define TEGRA114_CLK_PLL_P_OUT1 212
 239 #define TEGRA114_CLK_PLL_P_OUT2 213
 240 #define TEGRA114_CLK_PLL_P_OUT3 214
 241 #define TEGRA114_CLK_PLL_P_OUT4 215
 242 #define TEGRA114_CLK_PLL_A 216
 243 #define TEGRA114_CLK_PLL_A_OUT0 217
 244 #define TEGRA114_CLK_PLL_D 218
 245 #define TEGRA114_CLK_PLL_D_OUT0 219
 246 #define TEGRA114_CLK_PLL_D2 220
 247 #define TEGRA114_CLK_PLL_D2_OUT0 221
 248 #define TEGRA114_CLK_PLL_U 222
 249 #define TEGRA114_CLK_PLL_U_480M 223
 250
 251 #define TEGRA114_CLK_PLL_U_60M 224
 252 #define TEGRA114_CLK_PLL_U_48M 225
 253 #define TEGRA114_CLK_PLL_U_12M 226
 254 #define TEGRA114_CLK_PLL_X 227
 255 #define TEGRA114_CLK_PLL_X_OUT0 228
 256 #define TEGRA114_CLK_PLL_RE_VCO 229
 257 #define TEGRA114_CLK_PLL_RE_OUT 230
 258 #define TEGRA114_CLK_PLL_E_OUT0 231
 259 #define TEGRA114_CLK_SPDIF_IN_SYNC 232
 260 #define TEGRA114_CLK_I2S0_SYNC 233
 261 #define TEGRA114_CLK_I2S1_SYNC 234
 262 #define TEGRA114_CLK_I2S2_SYNC 235
 263 #define TEGRA114_CLK_I2S3_SYNC 236
 264 #define TEGRA114_CLK_I2S4_SYNC 237
 265 #define TEGRA114_CLK_VIMCLK_SYNC 238
 266 #define TEGRA114_CLK_AUDIO0 239
 267 #define TEGRA114_CLK_AUDIO1 240
 268 #define TEGRA114_CLK_AUDIO2 241
 269 #define TEGRA114_CLK_AUDIO3 242
 270 #define TEGRA114_CLK_AUDIO4 243
 271 #define TEGRA114_CLK_SPDIF 244
 272 #define TEGRA114_CLK_CLK_OUT_1 245
 273 #define TEGRA114_CLK_CLK_OUT_2 246
 274 #define TEGRA114_CLK_CLK_OUT_3 247
 275 #define TEGRA114_CLK_BLINK 248
 276 /* 249 */
 277 /* 250 */
 278 /* 251 */
 279 #define TEGRA114_CLK_XUSB_HOST_SRC 252
 280 #define TEGRA114_CLK_XUSB_FALCON_SRC 253
 281 #define TEGRA114_CLK_XUSB_FS_SRC 254
 282 #define TEGRA114_CLK_XUSB_SS_SRC 255
 283
 284 #define TEGRA114_CLK_XUSB_DEV_SRC 256
 285 #define TEGRA114_CLK_XUSB_DEV 257
 286 #define TEGRA114_CLK_XUSB_HS_SRC 258
 287 #define TEGRA114_CLK_SCLK 259
 288 #define TEGRA114_CLK_HCLK 260
 289 #define TEGRA114_CLK_PCLK 261
 290 #define TEGRA114_CLK_CCLK_G 262
 291 #define TEGRA114_CLK_CCLK_LP 263
 292 #define TEGRA114_CLK_DFLL_REF 264
 293 #define TEGRA114_CLK_DFLL_SOC 265
 294 /* 266 */
 295 /* 267 */
 296 /* 268 */
 297 /* 269 */
 298 /* 270 */
 299 /* 271 */
 300 /* 272 */
 301 /* 273 */
 302 /* 274 */
 303 /* 275 */
 304 /* 276 */
 305 /* 277 */
 306 /* 278 */
 307 /* 279 */
 308 /* 280 */
 309 /* 281 */
 310 /* 282 */
 311 /* 283 */
 312 /* 284 */
 313 /* 285 */
 314 /* 286 */
 315 /* 287 */
 316
 317 /* 288 */
 318 /* 289 */
 319 /* 290 */
 320 /* 291 */
 321 /* 292 */
 322 /* 293 */
 323 /* 294 */
 324 /* 295 */
 325 /* 296 */
 326 /* 297 */
 327 /* 298 */
 328 /* 299 */
 329 #define TEGRA114_CLK_AUDIO0_MUX 300
 330 #define TEGRA114_CLK_AUDIO1_MUX 301
 331 #define TEGRA114_CLK_AUDIO2_MUX 302
 332 #define TEGRA114_CLK_AUDIO3_MUX 303
 333 #define TEGRA114_CLK_AUDIO4_MUX 304
 334 #define TEGRA114_CLK_SPDIF_MUX 305
 335 #define TEGRA114_CLK_CLK_OUT_1_MUX 306
 336 #define TEGRA114_CLK_CLK_OUT_2_MUX 307
 337 #define TEGRA114_CLK_CLK_OUT_3_MUX 308
 338 #define TEGRA114_CLK_DSIA_MUX 309
 339 #define TEGRA114_CLK_DSIB_MUX 310
 340 #define TEGRA114_CLK_XUSB_SS_DIV2 311
 341 #define TEGRA114_CLK_CLK_MAX 312
 342
 343 #endif  /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */