MAINTAINERS: add an entry for kfifo
[linux/fpc-iii.git] / arch / m68k / coldfire / m5272.c
blob6b3ab583c69875e93648d7a3d0f2f528a345a6e4
1 // SPDX-License-Identifier: GPL-2.0
2 /***************************************************************************/
4 /*
5 * m5272.c -- platform support for ColdFire 5272 based boards
7 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
8 * Copyright (C) 2001-2002, SnapGear Inc. (www.snapgear.com)
9 */
11 /***************************************************************************/
13 #include <linux/kernel.h>
14 #include <linux/param.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/phy.h>
18 #include <linux/phy_fixed.h>
19 #include <asm/machdep.h>
20 #include <asm/coldfire.h>
21 #include <asm/mcfsim.h>
22 #include <asm/mcfuart.h>
23 #include <asm/mcfclk.h>
25 /***************************************************************************/
28 * Some platforms need software versions of the GPIO data registers.
30 unsigned short ppdata;
31 unsigned char ledbank = 0xff;
33 /***************************************************************************/
35 DEFINE_CLK(pll, "pll.0", MCF_CLK);
36 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
37 DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
38 DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
39 DEFINE_CLK(mcftmr2, "mcftmr.2", MCF_BUSCLK);
40 DEFINE_CLK(mcftmr3, "mcftmr.3", MCF_BUSCLK);
41 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
42 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
43 DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
44 DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
46 struct clk *mcf_clks[] = {
47 &clk_pll,
48 &clk_sys,
49 &clk_mcftmr0,
50 &clk_mcftmr1,
51 &clk_mcftmr2,
52 &clk_mcftmr3,
53 &clk_mcfuart0,
54 &clk_mcfuart1,
55 &clk_mcfqspi0,
56 &clk_fec0,
57 NULL
60 /***************************************************************************/
62 static void __init m5272_uarts_init(void)
64 u32 v;
66 /* Enable the output lines for the serial ports */
67 v = readl(MCFSIM_PBCNT);
68 v = (v & ~0x000000ff) | 0x00000055;
69 writel(v, MCFSIM_PBCNT);
71 v = readl(MCFSIM_PDCNT);
72 v = (v & ~0x000003fc) | 0x000002a8;
73 writel(v, MCFSIM_PDCNT);
76 /***************************************************************************/
78 static void m5272_cpu_reset(void)
80 local_irq_disable();
81 /* Set watchdog to reset, and enabled */
82 __raw_writew(0, MCFSIM_WIRR);
83 __raw_writew(1, MCFSIM_WRRR);
84 __raw_writew(0, MCFSIM_WCR);
85 for (;;)
86 /* wait for watchdog to timeout */;
89 /***************************************************************************/
91 void __init config_BSP(char *commandp, int size)
93 #if defined (CONFIG_MOD5272)
94 /* Set base of device vectors to be 64 */
95 writeb(0x40, MCFSIM_PIVR);
96 #endif
98 #if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
99 /* Copy command line from FLASH to local buffer... */
100 memcpy(commandp, (char *) 0xf0004000, size);
101 commandp[size-1] = 0;
102 #elif defined(CONFIG_CANCam)
103 /* Copy command line from FLASH to local buffer... */
104 memcpy(commandp, (char *) 0xf0010000, size);
105 commandp[size-1] = 0;
106 #endif
108 mach_reset = m5272_cpu_reset;
109 mach_sched_init = hw_timer_init;
112 /***************************************************************************/
115 * Some 5272 based boards have the FEC ethernet directly connected to
116 * an ethernet switch. In this case we need to use the fixed phy type,
117 * and we need to declare it early in boot.
119 static struct fixed_phy_status nettel_fixed_phy_status __initdata = {
120 .link = 1,
121 .speed = 100,
122 .duplex = 0,
125 /***************************************************************************/
127 static int __init init_BSP(void)
129 m5272_uarts_init();
130 fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
131 return 0;
134 arch_initcall(init_BSP);
136 /***************************************************************************/