arch/m68k/coldfire/sltimers.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /***************************************************************************/
   3
   4 /*
   5  *      sltimers.c -- generic ColdFire slice timer support.
   6  *
   7  *      Copyright (C) 2009-2010, Philippe De Muyter <phdm@macqel.be>
   8  *      based on
   9  *      timers.c -- generic ColdFire hardware timer support.
  10  *      Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com>
  11  */
  12
  13 /***************************************************************************/
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/sched.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20 #include <linux/profile.h>
  21 #include <linux/clocksource.h>
  22 #include <asm/io.h>
  23 #include <asm/traps.h>
  24 #include <asm/machdep.h>
  25 #include <asm/coldfire.h>
  26 #include <asm/mcfslt.h>
  27 #include <asm/mcfsim.h>
  28
  29 /***************************************************************************/
  30
  31 #ifdef CONFIG_HIGHPROFILE
  32
  33 /*
  34  *      By default use Slice Timer 1 as the profiler clock timer.
  35  */
  36 #define PA(a)   (MCFSLT_TIMER1 + (a))
  37
  38 /*
  39  *      Choose a reasonably fast profile timer. Make it an odd value to
  40  *      try and get good coverage of kernel operations.
  41  */
  42 #define PROFILEHZ       1013
  43
  44 irqreturn_t mcfslt_profile_tick(int irq, void *dummy)
  45 {
  46         /* Reset Slice Timer 1 */
  47         __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR));
  48         if (current->pid)
  49                 profile_tick(CPU_PROFILING);
  50         return IRQ_HANDLED;
  51 }
  52
  53 void mcfslt_profile_init(void)
  54 {
  55         int ret;
  56
  57         printk(KERN_INFO "PROFILE: lodging TIMER 1 @ %dHz as profile timer\n",
  58                PROFILEHZ);
  59
  60         ret = request_irq(MCF_IRQ_PROFILER, mcfslt_profile_tick, IRQF_TIMER,
  61                           "profile timer", NULL);
  62         if (ret) {
  63                 pr_err("Failed to request irq %d (profile timer): %pe\n",
  64                        MCF_IRQ_PROFILER, ERR_PTR(ret));
  65         }
  66
  67         /* Set up TIMER 2 as high speed profile clock */
  68         __raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT));
  69         __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
  70                                                                 PA(MCFSLT_SCR));
  71
  72 }
  73
  74 #endif  /* CONFIG_HIGHPROFILE */
  75
  76 /***************************************************************************/
  77
  78 /*
  79  *      By default use Slice Timer 0 as the system clock timer.
  80  */
  81 #define TA(a)   (MCFSLT_TIMER0 + (a))
  82
  83 static u32 mcfslt_cycles_per_jiffy;
  84 static u32 mcfslt_cnt;
  85
  86 static irq_handler_t timer_interrupt;
  87
  88 static irqreturn_t mcfslt_tick(int irq, void *dummy)
  89 {
  90         /* Reset Slice Timer 0 */
  91         __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
  92         mcfslt_cnt += mcfslt_cycles_per_jiffy;
  93         return timer_interrupt(irq, dummy);
  94 }
  95
  96 static u64 mcfslt_read_clk(struct clocksource *cs)
  97 {
  98         unsigned long flags;
  99         u32 cycles, scnt;
 100
 101         local_irq_save(flags);
 102         scnt = __raw_readl(TA(MCFSLT_SCNT));
 103         cycles = mcfslt_cnt;
 104         if (__raw_readl(TA(MCFSLT_SSR)) & MCFSLT_SSR_TE) {
 105                 cycles += mcfslt_cycles_per_jiffy;
 106                 scnt = __raw_readl(TA(MCFSLT_SCNT));
 107         }
 108         local_irq_restore(flags);
 109
 110         /* subtract because slice timers count down */
 111         return cycles + ((mcfslt_cycles_per_jiffy - 1) - scnt);
 112 }
 113
 114 static struct clocksource mcfslt_clk = {
 115         .name   = "slt",
 116         .rating = 250,
 117         .read   = mcfslt_read_clk,
 118         .mask   = CLOCKSOURCE_MASK(32),
 119         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 120 };
 121
 122 void hw_timer_init(irq_handler_t handler)
 123 {
 124         int r;
 125
 126         mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ;
 127         /*
 128          *      The coldfire slice timer (SLT) runs from STCNT to 0 included,
 129          *      then STCNT again and so on.  It counts thus actually
 130          *      STCNT + 1 steps for 1 tick, not STCNT.  So if you want
 131          *      n cycles, initialize STCNT with n - 1.
 132          */
 133         __raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT));
 134         __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
 135                                                                 TA(MCFSLT_SCR));
 136         /* initialize mcfslt_cnt knowing that slice timers count down */
 137         mcfslt_cnt = mcfslt_cycles_per_jiffy;
 138
 139         timer_interrupt = handler;
 140         r = request_irq(MCF_IRQ_TIMER, mcfslt_tick, IRQF_TIMER, "timer", NULL);
 141         if (r) {
 142                 pr_err("Failed to request irq %d (timer): %pe\n", MCF_IRQ_TIMER,
 143                        ERR_PTR(r));
 144         }
 145
 146         clocksource_register_hz(&mcfslt_clk, MCF_BUSCLK);
 147
 148 #ifdef CONFIG_HIGHPROFILE
 149         mcfslt_profile_init();
 150 #endif
 151 }