arch/arc/boot/dts/nsimosci_hs_idu.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
   4  */
   5 /dts-v1/;
   6
   7 /include/ "skeleton_hs_idu.dtsi"
   8
   9 / {
  10         model = "snps,nsimosci_hs-smp";
  11         compatible = "snps,nsimosci_hs";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&core_intc>;
  15
  16         chosen {
  17                 /* this is for console on serial */
  18                 bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24 print-fatal-signals=1";
  19         };
  20
  21         aliases {
  22                 serial0 = &uart0;
  23         };
  24
  25         fpga {
  26                 compatible = "simple-bus";
  27                 #address-cells = <1>;
  28                 #size-cells = <1>;
  29
  30                 /* child and parent address space 1:1 mapped */
  31                 ranges;
  32
  33                 core_clk: core_clk {
  34                         #clock-cells = <0>;
  35                         compatible = "fixed-clock";
  36                         clock-frequency = <5000000>;
  37                 };
  38
  39                 core_intc: core-interrupt-controller {
  40                         compatible = "snps,archs-intc";
  41                         interrupt-controller;
  42                         #interrupt-cells = <1>;
  43                 };
  44
  45                 idu_intc: idu-interrupt-controller {
  46                         compatible = "snps,archs-idu-intc";
  47                         interrupt-controller;
  48                         interrupt-parent = <&core_intc>;
  49                         #interrupt-cells = <1>;
  50                 };
  51
  52                 uart0: serial@f0000000 {
  53                         compatible = "ns8250";
  54                         reg = <0xf0000000 0x2000>;
  55                         interrupt-parent = <&idu_intc>;
  56                         interrupts = <0>;
  57                         clock-frequency = <3686400>;
  58                         baud = <115200>;
  59                         reg-shift = <2>;
  60                         reg-io-width = <4>;
  61                         no-loopback-test = <1>;
  62                 };
  63
  64                 pguclk: pguclk {
  65                         #clock-cells = <0>;
  66                         compatible = "fixed-clock";
  67                         clock-frequency = <25175000>;
  68                 };
  69
  70                 pgu@f9000000 {
  71                         compatible = "snps,arcpgu";
  72                         reg = <0xf9000000 0x400>;
  73                         clocks = <&pguclk>;
  74                         clock-names = "pxlclk";
  75                 };
  76
  77                 ps2: ps2@f9001000 {
  78                         compatible = "snps,arc_ps2";
  79                         reg = <0xf9000400 0x14>;
  80                         interrupts = <3>;
  81                         interrupt-parent = <&idu_intc>;
  82                         interrupt-names = "arc_ps2_irq";
  83                 };
  84
  85                 eth0: ethernet@f0003000 {
  86                         compatible = "ezchip,nps-mgt-enet";
  87                         reg = <0xf0003000 0x44>;
  88                         interrupt-parent = <&idu_intc>;
  89                         interrupts = <1>;
  90                 };
  91
  92                 arcpct0: pct {
  93                         compatible = "snps,archs-pct";
  94                         #interrupt-cells = <1>;
  95                         interrupts = <20>;
  96                 };
  97         };
  98 };