Linux 5.6.13
[linux/fpc-iii.git] / arch / arm / boot / dts / am335x-osd335x-common.dtsi
bloba8b6842489f745f838f50f9765e2c854c121b479
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4  *
5  * Author: Robert Nelson <robertcnelson@gmail.com>
6  */
8 / {
9         cpus {
10                 cpu@0 {
11                         cpu0-supply = <&dcdc2_reg>;
12                 };
13         };
15         memory@80000000 {
16                 device_type = "memory";
17                 reg = <0x80000000 0x20000000>; /* 512 MB */
18         };
21 &cpu0_opp_table {
22         /*
23         * Octavo Systems:
24         * The EFUSE_SMA register is not programmed for any of the AM335x wafers
25         * we get and we are not programming them during our production test.
26         * Therefore, from a DEVICE_ID revision point of view, the silicon looks
27         * like it is Revision 2.1.  However, from an EFUSE_SMA point of view for
28         * the HW OPP table, the silicon looks like it is Revision 1.0 (ie the
29         * EFUSE_SMA register reads as all zeros).
30         */
31         oppnitro-1000000000 {
32                 opp-supported-hw = <0x06 0x0100>;
33         };
36 &am33xx_pinmux {
37         i2c0_pins: pinmux-i2c0-pins {
38                 pinctrl-single,pins = <
39                         AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
40                         AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
41                 >;
42         };
45 &i2c0 {
46         pinctrl-names = "default";
47         pinctrl-0 = <&i2c0_pins>;
49         status = "okay";
50         clock-frequency = <400000>;
52         tps: tps@24 {
53                 reg = <0x24>;
54         };
57 /include/ "tps65217.dtsi"
59 &tps {
60         interrupts = <7>; /* NMI */
61         interrupt-parent = <&intc>;
63         ti,pmic-shutdown-controller;
65         pwrbutton {
66                 interrupts = <2>;
67                 status = "okay";
68         };
70         regulators {
71                 dcdc1_reg: regulator@0 {
72                         regulator-name = "vdds_dpr";
73                         regulator-always-on;
74                 };
76                 dcdc2_reg: regulator@1 {
77                         /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
78                         regulator-name = "vdd_mpu";
79                         regulator-min-microvolt = <925000>;
80                         regulator-max-microvolt = <1351500>;
81                         regulator-boot-on;
82                         regulator-always-on;
83                 };
85                 dcdc3_reg: regulator@2 {
86                         /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
87                         regulator-name = "vdd_core";
88                         regulator-min-microvolt = <925000>;
89                         regulator-max-microvolt = <1150000>;
90                         regulator-boot-on;
91                         regulator-always-on;
92                 };
94                 ldo1_reg: regulator@3 {
95                         regulator-name = "vio,vrtc,vdds";
96                         regulator-always-on;
97                 };
99                 ldo2_reg: regulator@4 {
100                         regulator-name = "vdd_3v3aux";
101                         regulator-always-on;
102                 };
104                 ldo3_reg: regulator@5 {
105                         regulator-name = "vdd_1v8";
106                         regulator-min-microvolt = <1800000>;
107                         regulator-max-microvolt = <1800000>;
108                         regulator-always-on;
109                 };
111                 ldo4_reg: regulator@6 {
112                         regulator-name = "vdd_3v3a";
113                         regulator-always-on;
114                 };
115         };
118 &aes {
119         status = "okay";
122 &sham {
123         status = "okay";