| blob | 4e2986f0c604644f8ed54d064993ecea8ce32df9 |
1 &l4_wkup { /* 0x44c00000 */
2 compatible = "ti,am33xx-l4-wkup", "simple-bus";
3 reg = <0x44c00000 0x800>,
4 <0x44c00800 0x800>,
5 <0x44c01000 0x400>,
6 <0x44c01400 0x400>;
7 reg-names = "ap", "la", "ia0", "ia1";
8 #address-cells = <1>;
9 #size-cells = <1>;
10 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
11 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
12 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
14 segment@0 { /* 0x44c00000 */
15 compatible = "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
19 <0x00000800 0x00000800 0x000800>, /* ap 1 */
20 <0x00001000 0x00001000 0x000400>, /* ap 2 */
21 <0x00001400 0x00001400 0x000400>; /* ap 3 */
22 };
24 segment@100000 { /* 0x44d00000 */
25 compatible = "simple-bus";
26 #address-cells = <1>;
27 #size-cells = <1>;
28 ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */
29 <0x00004000 0x00104000 0x001000>, /* ap 5 */
30 <0x00080000 0x00180000 0x002000>, /* ap 6 */
31 <0x00082000 0x00182000 0x001000>; /* ap 7 */
33 target-module@0 { /* 0x44d00000, ap 4 28.0 */
34 compatible = "ti,sysc-omap4", "ti,sysc";
35 reg = <0x0 0x4>;
36 reg-names = "rev";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 ranges = <0x0 0x0 0x4000>;
40 status = "disabled";
41 };
43 target-module@80000 { /* 0x44d80000, ap 6 10.0 */
44 compatible = "ti,sysc";
45 status = "disabled";
46 #address-cells = <1>;
47 #size-cells = <1>;
48 ranges = <0x0 0x80000 0x2000>;
49 };
50 };
52 segment@200000 { /* 0x44e00000 */
53 compatible = "simple-bus";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 ranges = <0x00000000 0x00200000 0x002000>, /* ap 8 */
57 <0x00002000 0x00202000 0x001000>, /* ap 9 */
58 <0x00003000 0x00203000 0x001000>, /* ap 10 */
59 <0x00004000 0x00204000 0x001000>, /* ap 11 */
60 <0x00005000 0x00205000 0x001000>, /* ap 12 */
61 <0x00006000 0x00206000 0x001000>, /* ap 13 */
62 <0x00007000 0x00207000 0x001000>, /* ap 14 */
63 <0x00008000 0x00208000 0x001000>, /* ap 15 */
64 <0x00009000 0x00209000 0x001000>, /* ap 16 */
65 <0x0000a000 0x0020a000 0x001000>, /* ap 17 */
66 <0x0000b000 0x0020b000 0x001000>, /* ap 18 */
67 <0x0000c000 0x0020c000 0x001000>, /* ap 19 */
68 <0x0000d000 0x0020d000 0x001000>, /* ap 20 */
69 <0x0000f000 0x0020f000 0x001000>, /* ap 21 */
70 <0x00010000 0x00210000 0x010000>, /* ap 22 */
71 <0x00020000 0x00220000 0x010000>, /* ap 23 */
72 <0x00030000 0x00230000 0x001000>, /* ap 24 */
73 <0x00031000 0x00231000 0x001000>, /* ap 25 */
74 <0x00032000 0x00232000 0x001000>, /* ap 26 */
75 <0x00033000 0x00233000 0x001000>, /* ap 27 */
76 <0x00034000 0x00234000 0x001000>, /* ap 28 */
77 <0x00035000 0x00235000 0x001000>, /* ap 29 */
78 <0x00036000 0x00236000 0x001000>, /* ap 30 */
79 <0x00037000 0x00237000 0x001000>, /* ap 31 */
80 <0x00038000 0x00238000 0x001000>, /* ap 32 */
81 <0x00039000 0x00239000 0x001000>, /* ap 33 */
82 <0x0003a000 0x0023a000 0x001000>, /* ap 34 */
83 <0x0003e000 0x0023e000 0x001000>, /* ap 35 */
84 <0x0003f000 0x0023f000 0x001000>, /* ap 36 */
85 <0x0000e000 0x0020e000 0x001000>, /* ap 37 */
86 <0x00040000 0x00240000 0x040000>, /* ap 38 */
87 <0x00080000 0x00280000 0x001000>; /* ap 39 */
89 target-module@0 { /* 0x44e00000, ap 8 58.0 */
90 compatible = "ti,sysc-omap4", "ti,sysc";
91 reg = <0 0x4>;
92 reg-names = "rev";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges = <0x0 0x0 0x2000>;
97 prcm: prcm@0 {
98 compatible = "ti,am3-prcm", "simple-bus";
99 reg = <0 0x2000>;
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges = <0 0 0x2000>;
104 prcm_clocks: clocks {
105 #address-cells = <1>;
106 #size-cells = <0>;
107 };
109 prcm_clockdomains: clockdomains {
110 };
111 };
112 };
114 target-module@3000 { /* 0x44e03000, ap 10 0a.0 */
115 compatible = "ti,sysc";
116 status = "disabled";
117 #address-cells = <1>;
118 #size-cells = <1>;
119 ranges = <0x0 0x3000 0x1000>;
120 };
122 target-module@5000 { /* 0x44e05000, ap 12 30.0 */
123 compatible = "ti,sysc";
124 status = "disabled";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 ranges = <0x0 0x5000 0x1000>;
128 };
130 gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */
131 compatible = "ti,sysc-omap2", "ti,sysc";
132 reg = <0x7000 0x4>,
133 <0x7010 0x4>,
134 <0x7114 0x4>;
135 reg-names = "rev", "sysc", "syss";
136 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
137 SYSC_OMAP2_SOFTRESET |
138 SYSC_OMAP2_AUTOIDLE)>;
139 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
140 <SYSC_IDLE_NO>,
141 <SYSC_IDLE_SMART>,
142 <SYSC_IDLE_SMART_WKUP>;
143 ti,syss-mask = <1>;
144 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
145 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 0>,
146 <&l4_wkup_clkctrl AM3_L4_WKUP_GPIO1_CLKCTRL 18>;
147 clock-names = "fck", "dbclk";
148 #address-cells = <1>;
149 #size-cells = <1>;
150 ranges = <0x0 0x7000 0x1000>;
152 gpio0: gpio@0 {
153 compatible = "ti,omap4-gpio";
154 gpio-controller;
155 #gpio-cells = <2>;
156 interrupt-controller;
157 #interrupt-cells = <2>;
158 reg = <0x0 0x1000>;
159 interrupts = <96>;
160 };
161 };
163 target-module@9000 { /* 0x44e09000, ap 16 04.0 */
164 compatible = "ti,sysc-omap2", "ti,sysc";
165 reg = <0x9050 0x4>,
166 <0x9054 0x4>,
167 <0x9058 0x4>;
168 reg-names = "rev", "sysc", "syss";
169 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
170 SYSC_OMAP2_SOFTRESET |
171 SYSC_OMAP2_AUTOIDLE)>;
172 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
173 <SYSC_IDLE_NO>,
174 <SYSC_IDLE_SMART>,
175 <SYSC_IDLE_SMART_WKUP>;
176 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
177 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_UART1_CLKCTRL 0>;
178 clock-names = "fck";
179 #address-cells = <1>;
180 #size-cells = <1>;
181 ranges = <0x0 0x9000 0x1000>;
183 uart0: serial@0 {
184 compatible = "ti,am3352-uart", "ti,omap3-uart";
185 clock-frequency = <48000000>;
186 reg = <0x0 0x1000>;
187 interrupts = <72>;
188 status = "disabled";
189 dmas = <&edma 26 0>, <&edma 27 0>;
190 dma-names = "tx", "rx";
191 };
192 };
194 target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
195 compatible = "ti,sysc-omap2", "ti,sysc";
196 reg = <0xb000 0x8>,
197 <0xb010 0x8>,
198 <0xb090 0x8>;
199 reg-names = "rev", "sysc", "syss";
200 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
201 SYSC_OMAP2_ENAWAKEUP |
202 SYSC_OMAP2_SOFTRESET |
203 SYSC_OMAP2_AUTOIDLE)>;
204 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
205 <SYSC_IDLE_NO>,
206 <SYSC_IDLE_SMART>,
207 <SYSC_IDLE_SMART_WKUP>;
208 ti,syss-mask = <1>;
209 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
210 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_I2C1_CLKCTRL 0>;
211 clock-names = "fck";
212 #address-cells = <1>;
213 #size-cells = <1>;
214 ranges = <0x0 0xb000 0x1000>;
216 i2c0: i2c@0 {
217 compatible = "ti,omap4-i2c";
218 #address-cells = <1>;
219 #size-cells = <0>;
220 reg = <0x0 0x1000>;
221 interrupts = <70>;
222 status = "disabled";
223 };
224 };
226 target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
227 compatible = "ti,sysc-omap4", "ti,sysc";
228 reg = <0xd000 0x4>,
229 <0xd010 0x4>;
230 reg-names = "rev", "sysc";
231 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
232 <SYSC_IDLE_NO>,
233 <SYSC_IDLE_SMART>,
234 <SYSC_IDLE_SMART_WKUP>;
235 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
236 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_ADC_TSC_CLKCTRL 0>;
237 clock-names = "fck";
238 #address-cells = <1>;
239 #size-cells = <1>;
240 ranges = <0x00000000 0x0000d000 0x00001000>,
241 <0x00001000 0x0000e000 0x00001000>;
243 tscadc: tscadc@0 {
244 compatible = "ti,am3359-tscadc";
245 reg = <0x0 0x1000>;
246 interrupts = <16>;
247 status = "disabled";
248 dmas = <&edma 53 0>, <&edma 57 0>;
249 dma-names = "fifo0", "fifo1";
251 tsc {
252 compatible = "ti,am3359-tsc";
253 };
254 am335x_adc: adc {
255 #io-channel-cells = <1>;
256 compatible = "ti,am3359-adc";
257 };
258 };
259 };
261 target-module@10000 { /* 0x44e10000, ap 22 0c.0 */
262 compatible = "ti,sysc-omap4", "ti,sysc";
263 reg = <0x10000 0x4>;
264 reg-names = "rev";
265 #address-cells = <1>;
266 #size-cells = <1>;
267 ranges = <0x00000000 0x00010000 0x00010000>,
268 <0x00010000 0x00020000 0x00010000>;
270 scm: scm@0 {
271 compatible = "ti,am3-scm", "simple-bus";
272 reg = <0x0 0x2000>;
273 #address-cells = <1>;
274 #size-cells = <1>;
275 #pinctrl-cells = <1>;
276 ranges = <0 0 0x2000>;
278 am33xx_pinmux: pinmux@800 {
279 compatible = "pinctrl-single";
280 reg = <0x800 0x238>;
281 #pinctrl-cells = <1>;
282 pinctrl-single,register-width = <32>;
283 pinctrl-single,function-mask = <0x7f>;
284 };
286 scm_conf: scm_conf@0 {
287 compatible = "syscon", "simple-bus";
288 reg = <0x0 0x800>;
289 #address-cells = <1>;
290 #size-cells = <1>;
291 ranges = <0 0 0x800>;
293 phy_gmii_sel: phy-gmii-sel {
294 compatible = "ti,am3352-phy-gmii-sel";
295 reg = <0x650 0x4>;
296 #phy-cells = <2>;
297 };
299 scm_clocks: clocks {
300 #address-cells = <1>;
301 #size-cells = <0>;
302 };
303 };
305 usb_ctrl_mod: control@620 {
306 compatible = "ti,am335x-usb-ctrl-module";
307 reg = <0x620 0x10>,
308 <0x648 0x4>;
309 reg-names = "phy_ctrl", "wakeup";
310 };
312 wkup_m3_ipc: wkup_m3_ipc@1324 {
313 compatible = "ti,am3352-wkup-m3-ipc";
314 reg = <0x1324 0x24>;
315 interrupts = <78>;
316 ti,rproc = <&wkup_m3>;
317 mboxes = <&mailbox &mbox_wkupm3>;
318 };
320 edma_xbar: dma-router@f90 {
321 compatible = "ti,am335x-edma-crossbar";
322 reg = <0xf90 0x40>;
323 #dma-cells = <3>;
324 dma-requests = <32>;
325 dma-masters = <&edma>;
326 };
328 scm_clockdomains: clockdomains {
329 };
330 };
331 };
333 target-module@31000 { /* 0x44e31000, ap 25 40.0 */
334 compatible = "ti,sysc-omap2-timer", "ti,sysc";
335 ti,hwmods = "timer1";
336 reg = <0x31000 0x4>,
337 <0x31010 0x4>,
338 <0x31014 0x4>;
339 reg-names = "rev", "sysc", "syss";
340 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
341 SYSC_OMAP2_SOFTRESET |
342 SYSC_OMAP2_AUTOIDLE)>;
343 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
344 <SYSC_IDLE_NO>,
345 <SYSC_IDLE_SMART>;
346 ti,syss-mask = <1>;
347 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
348 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>;
349 clock-names = "fck";
350 #address-cells = <1>;
351 #size-cells = <1>;
352 ranges = <0x0 0x31000 0x1000>;
354 timer1: timer@0 {
355 compatible = "ti,am335x-timer-1ms";
356 reg = <0x0 0x400>;
357 interrupts = <67>;
358 ti,timer-alwon;
359 clocks = <&timer1_fck>;
360 clock-names = "fck";
361 };
362 };
364 target-module@33000 { /* 0x44e33000, ap 27 18.0 */
365 compatible = "ti,sysc";
366 status = "disabled";
367 #address-cells = <1>;
368 #size-cells = <1>;
369 ranges = <0x0 0x33000 0x1000>;
370 };
372 target-module@35000 { /* 0x44e35000, ap 29 50.0 */
373 compatible = "ti,sysc-omap2", "ti,sysc";
374 reg = <0x35000 0x4>,
375 <0x35010 0x4>,
376 <0x35014 0x4>;
377 reg-names = "rev", "sysc", "syss";
378 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
379 SYSC_OMAP2_SOFTRESET)>;
380 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
381 <SYSC_IDLE_NO>,
382 <SYSC_IDLE_SMART>,
383 <SYSC_IDLE_SMART_WKUP>;
384 ti,syss-mask = <1>;
385 /* Domains (P, C): wkup_pwrdm, l4_wkup_clkdm */
386 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_WD_TIMER2_CLKCTRL 0>;
387 clock-names = "fck";
388 #address-cells = <1>;
389 #size-cells = <1>;
390 ranges = <0x0 0x35000 0x1000>;
392 wdt2: wdt@0 {
393 compatible = "ti,omap3-wdt";
394 reg = <0x0 0x1000>;
395 interrupts = <91>;
396 };
397 };
399 target-module@37000 { /* 0x44e37000, ap 31 08.0 */
400 compatible = "ti,sysc";
401 status = "disabled";
402 #address-cells = <1>;
403 #size-cells = <1>;
404 ranges = <0x0 0x37000 0x1000>;
405 };
407 target-module@39000 { /* 0x44e39000, ap 33 02.0 */
408 compatible = "ti,sysc";
409 status = "disabled";
410 #address-cells = <1>;
411 #size-cells = <1>;
412 ranges = <0x0 0x39000 0x1000>;
413 };
415 target-module@3e000 { /* 0x44e3e000, ap 35 60.0 */
416 compatible = "ti,sysc-omap4-simple", "ti,sysc";
417 ti,hwmods = "rtc";
418 reg = <0x3e074 0x4>,
419 <0x3e078 0x4>;
420 reg-names = "rev", "sysc";
421 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
422 <SYSC_IDLE_NO>,
423 <SYSC_IDLE_SMART>,
424 <SYSC_IDLE_SMART_WKUP>;
425 /* Domains (P, C): rtc_pwrdm, l4_rtc_clkdm */
426 clocks = <&l4_rtc_clkctrl AM3_L4_RTC_RTC_CLKCTRL 0>;
427 clock-names = "fck";
428 #address-cells = <1>;
429 #size-cells = <1>;
430 ranges = <0x0 0x3e000 0x1000>;
432 rtc: rtc@0 {
433 compatible = "ti,am3352-rtc", "ti,da830-rtc";
434 reg = <0x0 0x1000>;
435 interrupts = <75
436 76>;
437 };
438 };
440 target-module@40000 { /* 0x44e40000, ap 38 68.0 */
441 compatible = "ti,sysc";
442 status = "disabled";
443 #address-cells = <1>;
444 #size-cells = <1>;
445 ranges = <0x0 0x40000 0x40000>;
446 };
447 };
448 };
450 &l4_fw { /* 0x47c00000 */
451 compatible = "ti,am33xx-l4-fw", "simple-bus";
452 reg = <0x47c00000 0x800>,
453 <0x47c00800 0x800>,
454 <0x47c01000 0x400>;
455 reg-names = "ap", "la", "ia0";
456 #address-cells = <1>;
457 #size-cells = <1>;
458 ranges = <0x00000000 0x47c00000 0x1000000>; /* segment 0 */
460 segment@0 { /* 0x47c00000 */
461 compatible = "simple-bus";
462 #address-cells = <1>;
463 #size-cells = <1>;
464 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
465 <0x00000800 0x00000800 0x000800>, /* ap 1 */
466 <0x00001000 0x00001000 0x000400>, /* ap 2 */
467 <0x0000c000 0x0000c000 0x001000>, /* ap 3 */
468 <0x0000d000 0x0000d000 0x001000>, /* ap 4 */
469 <0x0000e000 0x0000e000 0x001000>, /* ap 5 */
470 <0x0000f000 0x0000f000 0x001000>, /* ap 6 */
471 <0x00010000 0x00010000 0x001000>, /* ap 7 */
472 <0x00011000 0x00011000 0x001000>, /* ap 8 */
473 <0x0001a000 0x0001a000 0x001000>, /* ap 9 */
474 <0x0001b000 0x0001b000 0x001000>, /* ap 10 */
475 <0x00024000 0x00024000 0x001000>, /* ap 11 */
476 <0x00025000 0x00025000 0x001000>, /* ap 12 */
477 <0x00026000 0x00026000 0x001000>, /* ap 13 */
478 <0x00027000 0x00027000 0x001000>, /* ap 14 */
479 <0x00030000 0x00030000 0x001000>, /* ap 15 */
480 <0x00031000 0x00031000 0x001000>, /* ap 16 */
481 <0x00038000 0x00038000 0x001000>, /* ap 17 */
482 <0x00039000 0x00039000 0x001000>, /* ap 18 */
483 <0x0003a000 0x0003a000 0x001000>, /* ap 19 */
484 <0x0003b000 0x0003b000 0x001000>, /* ap 20 */
485 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */
486 <0x0003f000 0x0003f000 0x001000>, /* ap 22 */
487 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */
488 <0x00040000 0x00040000 0x001000>, /* ap 24 */
489 <0x00046000 0x00046000 0x001000>, /* ap 25 */
490 <0x00047000 0x00047000 0x001000>, /* ap 26 */
491 <0x00044000 0x00044000 0x001000>, /* ap 27 */
492 <0x00045000 0x00045000 0x001000>, /* ap 28 */
493 <0x00028000 0x00028000 0x001000>, /* ap 29 */
494 <0x00029000 0x00029000 0x001000>, /* ap 30 */
495 <0x00032000 0x00032000 0x001000>, /* ap 31 */
496 <0x00033000 0x00033000 0x001000>, /* ap 32 */
497 <0x0003d000 0x0003d000 0x001000>, /* ap 33 */
498 <0x00041000 0x00041000 0x001000>, /* ap 34 */
499 <0x00042000 0x00042000 0x001000>, /* ap 35 */
500 <0x00043000 0x00043000 0x001000>, /* ap 36 */
501 <0x00014000 0x00014000 0x001000>, /* ap 37 */
502 <0x00015000 0x00015000 0x001000>; /* ap 38 */
504 target-module@c000 { /* 0x47c0c000, ap 3 04.0 */
505 compatible = "ti,sysc";
506 status = "disabled";
507 #address-cells = <1>;
508 #size-cells = <1>;
509 ranges = <0x0 0xc000 0x1000>;
510 };
512 target-module@e000 { /* 0x47c0e000, ap 5 0c.0 */
513 compatible = "ti,sysc";
514 status = "disabled";
515 #address-cells = <1>;
516 #size-cells = <1>;
517 ranges = <0x0 0xe000 0x1000>;
518 };
520 target-module@10000 { /* 0x47c10000, ap 7 20.0 */
521 compatible = "ti,sysc";
522 status = "disabled";
523 #address-cells = <1>;
524 #size-cells = <1>;
525 ranges = <0x0 0x10000 0x1000>;
526 };
528 target-module@14000 { /* 0x47c14000, ap 37 3c.0 */
529 compatible = "ti,sysc";
530 status = "disabled";
531 #address-cells = <1>;
532 #size-cells = <1>;
533 ranges = <0x0 0x14000 0x1000>;
534 };
536 target-module@1a000 { /* 0x47c1a000, ap 9 08.0 */
537 compatible = "ti,sysc";
538 status = "disabled";
539 #address-cells = <1>;
540 #size-cells = <1>;
541 ranges = <0x0 0x1a000 0x1000>;
542 };
544 target-module@24000 { /* 0x47c24000, ap 11 28.0 */
545 compatible = "ti,sysc";
546 status = "disabled";
547 #address-cells = <1>;
548 #size-cells = <1>;
549 ranges = <0x0 0x24000 0x1000>;
550 };
552 target-module@26000 { /* 0x47c26000, ap 13 30.0 */
553 compatible = "ti,sysc";
554 status = "disabled";
555 #address-cells = <1>;
556 #size-cells = <1>;
557 ranges = <0x0 0x26000 0x1000>;
558 };
560 target-module@28000 { /* 0x47c28000, ap 29 40.0 */
561 compatible = "ti,sysc";
562 status = "disabled";
563 #address-cells = <1>;
564 #size-cells = <1>;
565 ranges = <0x0 0x28000 0x1000>;
566 };
568 target-module@30000 { /* 0x47c30000, ap 15 14.0 */
569 compatible = "ti,sysc";
570 status = "disabled";
571 #address-cells = <1>;
572 #size-cells = <1>;
573 ranges = <0x0 0x30000 0x1000>;
574 };
576 target-module@32000 { /* 0x47c32000, ap 31 06.0 */
577 compatible = "ti,sysc";
578 status = "disabled";
579 #address-cells = <1>;
580 #size-cells = <1>;
581 ranges = <0x0 0x32000 0x1000>;
582 };
584 target-module@38000 { /* 0x47c38000, ap 17 18.0 */
585 compatible = "ti,sysc";
586 status = "disabled";
587 #address-cells = <1>;
588 #size-cells = <1>;
589 ranges = <0x0 0x38000 0x1000>;
590 };
592 target-module@3a000 { /* 0x47c3a000, ap 19 1c.0 */
593 compatible = "ti,sysc";
594 status = "disabled";
595 #address-cells = <1>;
596 #size-cells = <1>;
597 ranges = <0x0 0x3a000 0x1000>;
598 };
600 target-module@3c000 { /* 0x47c3c000, ap 23 38.0 */
601 compatible = "ti,sysc";
602 status = "disabled";
603 #address-cells = <1>;
604 #size-cells = <1>;
605 ranges = <0x0 0x3c000 0x1000>;
606 };
608 target-module@3e000 { /* 0x47c3e000, ap 21 10.0 */
609 compatible = "ti,sysc";
610 status = "disabled";
611 #address-cells = <1>;
612 #size-cells = <1>;
613 ranges = <0x0 0x3e000 0x1000>;
614 };
616 target-module@40000 { /* 0x47c40000, ap 24 02.0 */
617 compatible = "ti,sysc";
618 status = "disabled";
619 #address-cells = <1>;
620 #size-cells = <1>;
621 ranges = <0x0 0x40000 0x1000>;
622 };
624 target-module@42000 { /* 0x47c42000, ap 35 34.0 */
625 compatible = "ti,sysc";
626 status = "disabled";
627 #address-cells = <1>;
628 #size-cells = <1>;
629 ranges = <0x0 0x42000 0x1000>;
630 };
632 target-module@44000 { /* 0x47c44000, ap 27 24.0 */
633 compatible = "ti,sysc";
634 status = "disabled";
635 #address-cells = <1>;
636 #size-cells = <1>;
637 ranges = <0x0 0x44000 0x1000>;
638 };
640 target-module@46000 { /* 0x47c46000, ap 25 2c.0 */
641 compatible = "ti,sysc";
642 status = "disabled";
643 #address-cells = <1>;
644 #size-cells = <1>;
645 ranges = <0x0 0x46000 0x1000>;
646 };
647 };
648 };
650 &l4_fast { /* 0x4a000000 */
651 compatible = "ti,am33xx-l4-fast", "simple-bus";
652 reg = <0x4a000000 0x800>,
653 <0x4a000800 0x800>,
654 <0x4a001000 0x400>;
655 reg-names = "ap", "la", "ia0";
656 #address-cells = <1>;
657 #size-cells = <1>;
658 ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */
660 segment@0 { /* 0x4a000000 */
661 compatible = "simple-bus";
662 #address-cells = <1>;
663 #size-cells = <1>;
664 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
665 <0x00000800 0x00000800 0x000800>, /* ap 1 */
666 <0x00001000 0x00001000 0x000400>, /* ap 2 */
667 <0x00100000 0x00100000 0x008000>, /* ap 3 */
668 <0x00108000 0x00108000 0x001000>, /* ap 4 */
669 <0x00180000 0x00180000 0x020000>, /* ap 5 */
670 <0x001a0000 0x001a0000 0x001000>, /* ap 6 */
671 <0x00200000 0x00200000 0x080000>, /* ap 7 */
672 <0x00280000 0x00280000 0x001000>, /* ap 8 */
673 <0x00300000 0x00300000 0x080000>, /* ap 9 */
674 <0x00380000 0x00380000 0x001000>; /* ap 10 */
676 target-module@100000 { /* 0x4a100000, ap 3 08.0 */
677 compatible = "ti,sysc-omap4-simple", "ti,sysc";
678 reg = <0x101200 0x4>,
679 <0x101208 0x4>,
680 <0x101204 0x4>;
681 reg-names = "rev", "sysc", "syss";
682 ti,sysc-mask = <0>;
683 ti,sysc-midle = <SYSC_IDLE_FORCE>,
684 <SYSC_IDLE_NO>;
685 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
686 <SYSC_IDLE_NO>;
687 ti,syss-mask = <1>;
688 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
689 clock-names = "fck";
690 #address-cells = <1>;
691 #size-cells = <1>;
692 ranges = <0x0 0x100000 0x8000>;
694 mac: ethernet@0 {
695 compatible = "ti,am335x-cpsw","ti,cpsw";
696 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
697 clock-names = "fck", "cpts";
698 cpdma_channels = <8>;
699 ale_entries = <1024>;
700 bd_ram_size = <0x2000>;
701 mac_control = <0x20>;
702 slaves = <2>;
703 active_slave = <0>;
704 cpts_clock_mult = <0x80000000>;
705 cpts_clock_shift = <29>;
706 reg = <0x0 0x800
707 0x1200 0x100>;
708 #address-cells = <1>;
709 #size-cells = <1>;
710 /*
711 * c0_rx_thresh_pend
712 * c0_rx_pend
713 * c0_tx_pend
714 * c0_misc_pend
715 */
716 interrupts = <40 41 42 43>;
717 ranges = <0 0 0x8000>;
718 syscon = <&scm_conf>;
719 status = "disabled";
721 davinci_mdio: mdio@1000 {
722 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
723 clocks = <&cpsw_125mhz_clkctrl AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
724 clock-names = "fck";
725 #address-cells = <1>;
726 #size-cells = <0>;
727 bus_freq = <1000000>;
728 reg = <0x1000 0x100>;
729 status = "disabled";
730 };
732 cpsw_emac0: slave@200 {
733 /* Filled in by U-Boot */
734 mac-address = [ 00 00 00 00 00 00 ];
735 phys = <&phy_gmii_sel 1 1>;
736 };
738 cpsw_emac1: slave@300 {
739 /* Filled in by U-Boot */
740 mac-address = [ 00 00 00 00 00 00 ];
741 phys = <&phy_gmii_sel 2 1>;
742 };
743 };
744 };
746 target-module@180000 { /* 0x4a180000, ap 5 10.0 */
747 compatible = "ti,sysc";
748 status = "disabled";
749 #address-cells = <1>;
750 #size-cells = <1>;
751 ranges = <0x0 0x180000 0x20000>;
752 };
754 target-module@200000 { /* 0x4a200000, ap 7 02.0 */
755 compatible = "ti,sysc";
756 status = "disabled";
757 #address-cells = <1>;
758 #size-cells = <1>;
759 ranges = <0x0 0x200000 0x80000>;
760 };
762 target-module@300000 { /* 0x4a300000, ap 9 04.0 */
763 compatible = "ti,sysc";
764 status = "disabled";
765 #address-cells = <1>;
766 #size-cells = <1>;
767 ranges = <0x0 0x300000 0x80000>;
768 };
769 };
770 };
772 &l4_mpuss { /* 0x4b140000 */
773 compatible = "ti,am33xx-l4-mpuss", "simple-bus";
774 reg = <0x4b144400 0x100>,
775 <0x4b144800 0x400>;
776 reg-names = "la", "ap";
777 #address-cells = <1>;
778 #size-cells = <1>;
779 ranges = <0x00000000 0x4b140000 0x008000>; /* segment 0 */
781 segment@0 { /* 0x4b140000 */
782 compatible = "simple-bus";
783 #address-cells = <1>;
784 #size-cells = <1>;
785 ranges = <0x00004800 0x00004800 0x000400>, /* ap 0 */
786 <0x00001000 0x00001000 0x001000>, /* ap 1 */
787 <0x00002000 0x00002000 0x001000>, /* ap 2 */
788 <0x00004000 0x00004000 0x000400>, /* ap 3 */
789 <0x00005000 0x00005000 0x000400>, /* ap 4 */
790 <0x00000000 0x00000000 0x001000>, /* ap 5 */
791 <0x00003000 0x00003000 0x001000>, /* ap 6 */
792 <0x00000800 0x00000800 0x000800>; /* ap 7 */
794 target-module@0 { /* 0x4b140000, ap 5 02.2 */
795 compatible = "ti,sysc";
796 status = "disabled";
797 #address-cells = <1>;
798 #size-cells = <1>;
799 ranges = <0x00000000 0x00000000 0x00001000>,
800 <0x00001000 0x00001000 0x00001000>,
801 <0x00002000 0x00002000 0x00001000>;
802 };
804 target-module@3000 { /* 0x4b143000, ap 6 04.0 */
805 compatible = "ti,sysc";
806 status = "disabled";
807 #address-cells = <1>;
808 #size-cells = <1>;
809 ranges = <0x0 0x3000 0x1000>;
810 };
811 };
812 };
814 &l4_per { /* 0x48000000 */
815 compatible = "ti,am33xx-l4-per", "simple-bus";
816 reg = <0x48000000 0x800>,
817 <0x48000800 0x800>,
818 <0x48001000 0x400>,
819 <0x48001400 0x400>,
820 <0x48001800 0x400>,
821 <0x48001c00 0x400>;
822 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
823 #address-cells = <1>;
824 #size-cells = <1>;
825 ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */
826 <0x00100000 0x48100000 0x100000>, /* segment 1 */
827 <0x00200000 0x48200000 0x100000>, /* segment 2 */
828 <0x00300000 0x48300000 0x100000>, /* segment 3 */
829 <0x46000000 0x46000000 0x400000>, /* l3 data port */
830 <0x46400000 0x46400000 0x400000>; /* l3 data port */
832 segment@0 { /* 0x48000000 */
833 compatible = "simple-bus";
834 #address-cells = <1>;
835 #size-cells = <1>;
836 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
837 <0x00000800 0x00000800 0x000800>, /* ap 1 */
838 <0x00001000 0x00001000 0x000400>, /* ap 2 */
839 <0x00001400 0x00001400 0x000400>, /* ap 3 */
840 <0x00001800 0x00001800 0x000400>, /* ap 4 */
841 <0x00001c00 0x00001c00 0x000400>, /* ap 5 */
842 <0x00008000 0x00008000 0x001000>, /* ap 6 */
843 <0x00009000 0x00009000 0x001000>, /* ap 7 */
844 <0x00016000 0x00016000 0x001000>, /* ap 8 */
845 <0x00017000 0x00017000 0x001000>, /* ap 9 */
846 <0x00022000 0x00022000 0x001000>, /* ap 10 */
847 <0x00023000 0x00023000 0x001000>, /* ap 11 */
848 <0x00024000 0x00024000 0x001000>, /* ap 12 */
849 <0x00025000 0x00025000 0x001000>, /* ap 13 */
850 <0x0002a000 0x0002a000 0x001000>, /* ap 14 */
851 <0x0002b000 0x0002b000 0x001000>, /* ap 15 */
852 <0x00038000 0x00038000 0x002000>, /* ap 16 */
853 <0x0003a000 0x0003a000 0x001000>, /* ap 17 */
854 <0x00014000 0x00014000 0x001000>, /* ap 18 */
855 <0x00015000 0x00015000 0x001000>, /* ap 19 */
856 <0x0003c000 0x0003c000 0x002000>, /* ap 20 */
857 <0x0003e000 0x0003e000 0x001000>, /* ap 21 */
858 <0x00040000 0x00040000 0x001000>, /* ap 22 */
859 <0x00041000 0x00041000 0x001000>, /* ap 23 */
860 <0x00042000 0x00042000 0x001000>, /* ap 24 */
861 <0x00043000 0x00043000 0x001000>, /* ap 25 */
862 <0x00044000 0x00044000 0x001000>, /* ap 26 */
863 <0x00045000 0x00045000 0x001000>, /* ap 27 */
864 <0x00046000 0x00046000 0x001000>, /* ap 28 */
865 <0x00047000 0x00047000 0x001000>, /* ap 29 */
866 <0x00048000 0x00048000 0x001000>, /* ap 30 */
867 <0x00049000 0x00049000 0x001000>, /* ap 31 */
868 <0x0004c000 0x0004c000 0x001000>, /* ap 32 */
869 <0x0004d000 0x0004d000 0x001000>, /* ap 33 */
870 <0x00050000 0x00050000 0x002000>, /* ap 34 */
871 <0x00052000 0x00052000 0x001000>, /* ap 35 */
872 <0x00060000 0x00060000 0x001000>, /* ap 36 */
873 <0x00061000 0x00061000 0x001000>, /* ap 37 */
874 <0x00080000 0x00080000 0x010000>, /* ap 38 */
875 <0x00090000 0x00090000 0x001000>, /* ap 39 */
876 <0x000a0000 0x000a0000 0x010000>, /* ap 40 */
877 <0x000b0000 0x000b0000 0x001000>, /* ap 41 */
878 <0x00030000 0x00030000 0x001000>, /* ap 77 */
879 <0x00031000 0x00031000 0x001000>, /* ap 78 */
880 <0x0004a000 0x0004a000 0x001000>, /* ap 85 */
881 <0x0004b000 0x0004b000 0x001000>, /* ap 86 */
882 <0x000c8000 0x000c8000 0x001000>, /* ap 87 */
883 <0x000c9000 0x000c9000 0x001000>, /* ap 88 */
884 <0x000cc000 0x000cc000 0x001000>, /* ap 89 */
885 <0x000cd000 0x000cd000 0x001000>, /* ap 90 */
886 <0x000ca000 0x000ca000 0x001000>, /* ap 91 */
887 <0x000cb000 0x000cb000 0x001000>, /* ap 92 */
888 <0x46000000 0x46000000 0x400000>, /* l3 data port */
889 <0x46400000 0x46400000 0x400000>; /* l3 data port */
891 target-module@8000 { /* 0x48008000, ap 6 10.0 */
892 compatible = "ti,sysc";
893 status = "disabled";
894 #address-cells = <1>;
895 #size-cells = <1>;
896 ranges = <0x0 0x8000 0x1000>;
897 };
899 target-module@14000 { /* 0x48014000, ap 18 58.0 */
900 compatible = "ti,sysc";
901 status = "disabled";
902 #address-cells = <1>;
903 #size-cells = <1>;
904 ranges = <0x0 0x14000 0x1000>;
905 };
907 target-module@16000 { /* 0x48016000, ap 8 3c.0 */
908 compatible = "ti,sysc";
909 status = "disabled";
910 #address-cells = <1>;
911 #size-cells = <1>;
912 ranges = <0x0 0x16000 0x1000>;
913 };
915 target-module@22000 { /* 0x48022000, ap 10 12.0 */
916 compatible = "ti,sysc-omap2", "ti,sysc";
917 reg = <0x22050 0x4>,
918 <0x22054 0x4>,
919 <0x22058 0x4>;
920 reg-names = "rev", "sysc", "syss";
921 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
922 SYSC_OMAP2_SOFTRESET |
923 SYSC_OMAP2_AUTOIDLE)>;
924 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
925 <SYSC_IDLE_NO>,
926 <SYSC_IDLE_SMART>,
927 <SYSC_IDLE_SMART_WKUP>;
928 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
929 clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>;
930 clock-names = "fck";
931 #address-cells = <1>;
932 #size-cells = <1>;
933 ranges = <0x0 0x22000 0x1000>;
935 uart1: serial@0 {
936 compatible = "ti,am3352-uart", "ti,omap3-uart";
937 clock-frequency = <48000000>;
938 reg = <0x0 0x1000>;
939 interrupts = <73>;
940 status = "disabled";
941 dmas = <&edma 28 0>, <&edma 29 0>;
942 dma-names = "tx", "rx";
943 };
944 };
946 target-module@24000 { /* 0x48024000, ap 12 14.0 */
947 compatible = "ti,sysc-omap2", "ti,sysc";
948 reg = <0x24050 0x4>,
949 <0x24054 0x4>,
950 <0x24058 0x4>;
951 reg-names = "rev", "sysc", "syss";
952 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
953 SYSC_OMAP2_SOFTRESET |
954 SYSC_OMAP2_AUTOIDLE)>;
955 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
956 <SYSC_IDLE_NO>,
957 <SYSC_IDLE_SMART>,
958 <SYSC_IDLE_SMART_WKUP>;
959 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
960 clocks = <&l4ls_clkctrl AM3_L4LS_UART3_CLKCTRL 0>;
961 clock-names = "fck";
962 #address-cells = <1>;
963 #size-cells = <1>;
964 ranges = <0x0 0x24000 0x1000>;
966 uart2: serial@0 {
967 compatible = "ti,am3352-uart", "ti,omap3-uart";
968 clock-frequency = <48000000>;
969 reg = <0x0 0x1000>;
970 interrupts = <74>;
971 status = "disabled";
972 dmas = <&edma 30 0>, <&edma 31 0>;
973 dma-names = "tx", "rx";
974 };
975 };
977 target-module@2a000 { /* 0x4802a000, ap 14 2a.0 */
978 compatible = "ti,sysc-omap2", "ti,sysc";
979 reg = <0x2a000 0x8>,
980 <0x2a010 0x8>,
981 <0x2a090 0x8>;
982 reg-names = "rev", "sysc", "syss";
983 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
984 SYSC_OMAP2_ENAWAKEUP |
985 SYSC_OMAP2_SOFTRESET |
986 SYSC_OMAP2_AUTOIDLE)>;
987 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
988 <SYSC_IDLE_NO>,
989 <SYSC_IDLE_SMART>,
990 <SYSC_IDLE_SMART_WKUP>;
991 ti,syss-mask = <1>;
992 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
993 clocks = <&l4ls_clkctrl AM3_L4LS_I2C2_CLKCTRL 0>;
994 clock-names = "fck";
995 #address-cells = <1>;
996 #size-cells = <1>;
997 ranges = <0x0 0x2a000 0x1000>;
999 i2c1: i2c@0 {
1000 compatible = "ti,omap4-i2c";
1001 #address-cells = <1>;
1002 #size-cells = <0>;
1003 reg = <0x0 0x1000>;
1004 interrupts = <71>;
1005 status = "disabled";
1006 };
1007 };
1009 target-module@30000 { /* 0x48030000, ap 77 08.0 */
1010 compatible = "ti,sysc-omap2", "ti,sysc";
1011 reg = <0x30000 0x4>,
1012 <0x30110 0x4>,
1013 <0x30114 0x4>;
1014 reg-names = "rev", "sysc", "syss";
1015 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1016 SYSC_OMAP2_SOFTRESET |
1017 SYSC_OMAP2_AUTOIDLE)>;
1018 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1019 <SYSC_IDLE_NO>,
1020 <SYSC_IDLE_SMART>;
1021 ti,syss-mask = <1>;
1022 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1023 clocks = <&l4ls_clkctrl AM3_L4LS_SPI0_CLKCTRL 0>;
1024 clock-names = "fck";
1025 #address-cells = <1>;
1026 #size-cells = <1>;
1027 ranges = <0x0 0x30000 0x1000>;
1029 spi0: spi@0 {
1030 compatible = "ti,omap4-mcspi";
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1033 reg = <0x0 0x400>;
1034 interrupts = <65>;
1035 ti,spi-num-cs = <2>;
1036 dmas = <&edma 16 0
1037 &edma 17 0
1038 &edma 18 0
1039 &edma 19 0>;
1040 dma-names = "tx0", "rx0", "tx1", "rx1";
1041 status = "disabled";
1042 };
1043 };
1045 target-module@38000 { /* 0x48038000, ap 16 02.0 */
1046 compatible = "ti,sysc-omap4-simple", "ti,sysc";
1047 reg = <0x38000 0x4>,
1048 <0x38004 0x4>;
1049 reg-names = "rev", "sysc";
1050 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1051 <SYSC_IDLE_NO>,
1052 <SYSC_IDLE_SMART>;
1053 /* Domains (P, C): per_pwrdm, l3s_clkdm */
1054 clocks = <&l3s_clkctrl AM3_L3S_MCASP0_CLKCTRL 0>;
1055 clock-names = "fck";
1056 #address-cells = <1>;
1057 #size-cells = <1>;
1058 ranges = <0x0 0x38000 0x2000>,
1059 <0x46000000 0x46000000 0x400000>;
1061 mcasp0: mcasp@0 {
1062 compatible = "ti,am33xx-mcasp-audio";
1063 reg = <0x0 0x2000>,
1064 <0x46000000 0x400000>;
1065 reg-names = "mpu", "dat";
1066 interrupts = <80>, <81>;
1067 interrupt-names = "tx", "rx";
1068 status = "disabled";
1069 dmas = <&edma 8 2>,
1070 <&edma 9 2>;
1071 dma-names = "tx", "rx";
1072 };
1073 };
1075 target-module@3c000 { /* 0x4803c000, ap 20 32.0 */
1076 compatible = "ti,sysc-omap4-simple", "ti,sysc";
1077 reg = <0x3c000 0x4>,
1078 <0x3c004 0x4>;
1079 reg-names = "rev", "sysc";
1080 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1081 <SYSC_IDLE_NO>,
1082 <SYSC_IDLE_SMART>;
1083 /* Domains (P, C): per_pwrdm, l3s_clkdm */
1084 clocks = <&l3s_clkctrl AM3_L3S_MCASP1_CLKCTRL 0>;
1085 clock-names = "fck";
1086 #address-cells = <1>;
1087 #size-cells = <1>;
1088 ranges = <0x0 0x3c000 0x2000>,
1089 <0x46400000 0x46400000 0x400000>;
1091 mcasp1: mcasp@0 {
1092 compatible = "ti,am33xx-mcasp-audio";
1093 reg = <0x0 0x2000>,
1094 <0x46400000 0x400000>;
1095 reg-names = "mpu", "dat";
1096 interrupts = <82>, <83>;
1097 interrupt-names = "tx", "rx";
1098 status = "disabled";
1099 dmas = <&edma 10 2>,
1100 <&edma 11 2>;
1101 dma-names = "tx", "rx";
1102 };
1103 };
1105 target-module@40000 { /* 0x48040000, ap 22 1e.0 */
1106 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1107 ti,hwmods = "timer2";
1108 reg = <0x40000 0x4>,
1109 <0x40010 0x4>,
1110 <0x40014 0x4>;
1111 reg-names = "rev", "sysc", "syss";
1112 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1113 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1114 <SYSC_IDLE_NO>,
1115 <SYSC_IDLE_SMART>,
1116 <SYSC_IDLE_SMART_WKUP>;
1117 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1118 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>;
1119 clock-names = "fck";
1120 #address-cells = <1>;
1121 #size-cells = <1>;
1122 ranges = <0x0 0x40000 0x1000>;
1124 timer2: timer@0 {
1125 compatible = "ti,am335x-timer";
1126 reg = <0x0 0x400>;
1127 interrupts = <68>;
1128 clocks = <&timer2_fck>;
1129 clock-names = "fck";
1130 };
1131 };
1133 target-module@42000 { /* 0x48042000, ap 24 1c.0 */
1134 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1135 reg = <0x42000 0x4>,
1136 <0x42010 0x4>,
1137 <0x42014 0x4>;
1138 reg-names = "rev", "sysc", "syss";
1139 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1140 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1141 <SYSC_IDLE_NO>,
1142 <SYSC_IDLE_SMART>,
1143 <SYSC_IDLE_SMART_WKUP>;
1144 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1145 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER3_CLKCTRL 0>;
1146 clock-names = "fck";
1147 #address-cells = <1>;
1148 #size-cells = <1>;
1149 ranges = <0x0 0x42000 0x1000>;
1151 timer3: timer@0 {
1152 compatible = "ti,am335x-timer";
1153 reg = <0x0 0x400>;
1154 interrupts = <69>;
1155 };
1156 };
1158 target-module@44000 { /* 0x48044000, ap 26 26.0 */
1159 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1160 reg = <0x44000 0x4>,
1161 <0x44010 0x4>,
1162 <0x44014 0x4>;
1163 reg-names = "rev", "sysc", "syss";
1164 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1165 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1166 <SYSC_IDLE_NO>,
1167 <SYSC_IDLE_SMART>,
1168 <SYSC_IDLE_SMART_WKUP>;
1169 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1170 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER4_CLKCTRL 0>;
1171 clock-names = "fck";
1172 #address-cells = <1>;
1173 #size-cells = <1>;
1174 ranges = <0x0 0x44000 0x1000>;
1176 timer4: timer@0 {
1177 compatible = "ti,am335x-timer";
1178 reg = <0x0 0x400>;
1179 interrupts = <92>;
1180 ti,timer-pwm;
1181 };
1182 };
1184 target-module@46000 { /* 0x48046000, ap 28 28.0 */
1185 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1186 reg = <0x46000 0x4>,
1187 <0x46010 0x4>,
1188 <0x46014 0x4>;
1189 reg-names = "rev", "sysc", "syss";
1190 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1191 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1192 <SYSC_IDLE_NO>,
1193 <SYSC_IDLE_SMART>,
1194 <SYSC_IDLE_SMART_WKUP>;
1195 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1196 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER5_CLKCTRL 0>;
1197 clock-names = "fck";
1198 #address-cells = <1>;
1199 #size-cells = <1>;
1200 ranges = <0x0 0x46000 0x1000>;
1202 timer5: timer@0 {
1203 compatible = "ti,am335x-timer";
1204 reg = <0x0 0x400>;
1205 interrupts = <93>;
1206 ti,timer-pwm;
1207 };
1208 };
1210 target-module@48000 { /* 0x48048000, ap 30 22.0 */
1211 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1212 reg = <0x48000 0x4>,
1213 <0x48010 0x4>,
1214 <0x48014 0x4>;
1215 reg-names = "rev", "sysc", "syss";
1216 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1217 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1218 <SYSC_IDLE_NO>,
1219 <SYSC_IDLE_SMART>,
1220 <SYSC_IDLE_SMART_WKUP>;
1221 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1222 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER6_CLKCTRL 0>;
1223 clock-names = "fck";
1224 #address-cells = <1>;
1225 #size-cells = <1>;
1226 ranges = <0x0 0x48000 0x1000>;
1228 timer6: timer@0 {
1229 compatible = "ti,am335x-timer";
1230 reg = <0x0 0x400>;
1231 interrupts = <94>;
1232 ti,timer-pwm;
1233 };
1234 };
1236 target-module@4a000 { /* 0x4804a000, ap 85 60.0 */
1237 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1238 reg = <0x4a000 0x4>,
1239 <0x4a010 0x4>,
1240 <0x4a014 0x4>;
1241 reg-names = "rev", "sysc", "syss";
1242 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1243 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1244 <SYSC_IDLE_NO>,
1245 <SYSC_IDLE_SMART>,
1246 <SYSC_IDLE_SMART_WKUP>;
1247 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1248 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER7_CLKCTRL 0>;
1249 clock-names = "fck";
1250 #address-cells = <1>;
1251 #size-cells = <1>;
1252 ranges = <0x0 0x4a000 0x1000>;
1254 timer7: timer@0 {
1255 compatible = "ti,am335x-timer";
1256 reg = <0x0 0x400>;
1257 interrupts = <95>;
1258 ti,timer-pwm;
1259 };
1260 };
1262 target-module@4c000 { /* 0x4804c000, ap 32 36.0 */
1263 compatible = "ti,sysc-omap2", "ti,sysc";
1264 reg = <0x4c000 0x4>,
1265 <0x4c010 0x4>,
1266 <0x4c114 0x4>;
1267 reg-names = "rev", "sysc", "syss";
1268 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1269 SYSC_OMAP2_SOFTRESET |
1270 SYSC_OMAP2_AUTOIDLE)>;
1271 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1272 <SYSC_IDLE_NO>,
1273 <SYSC_IDLE_SMART>,
1274 <SYSC_IDLE_SMART_WKUP>;
1275 ti,syss-mask = <1>;
1276 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1277 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 0>,
1278 <&l4ls_clkctrl AM3_L4LS_GPIO2_CLKCTRL 18>;
1279 clock-names = "fck", "dbclk";
1280 #address-cells = <1>;
1281 #size-cells = <1>;
1282 ranges = <0x0 0x4c000 0x1000>;
1284 gpio1: gpio@0 {
1285 compatible = "ti,omap4-gpio";
1286 gpio-controller;
1287 #gpio-cells = <2>;
1288 interrupt-controller;
1289 #interrupt-cells = <2>;
1290 reg = <0x0 0x1000>;
1291 interrupts = <98>;
1292 };
1293 };
1295 target-module@50000 { /* 0x48050000, ap 34 2c.0 */
1296 compatible = "ti,sysc";
1297 status = "disabled";
1298 #address-cells = <1>;
1299 #size-cells = <1>;
1300 ranges = <0x0 0x50000 0x2000>;
1301 };
1303 target-module@60000 { /* 0x48060000, ap 36 0c.0 */
1304 compatible = "ti,sysc-omap2", "ti,sysc";
1305 reg = <0x602fc 0x4>,
1306 <0x60110 0x4>,
1307 <0x60114 0x4>;
1308 reg-names = "rev", "sysc", "syss";
1309 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1310 SYSC_OMAP2_ENAWAKEUP |
1311 SYSC_OMAP2_SOFTRESET |
1312 SYSC_OMAP2_AUTOIDLE)>;
1313 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1314 <SYSC_IDLE_NO>,
1315 <SYSC_IDLE_SMART>;
1316 ti,syss-mask = <1>;
1317 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1318 clocks = <&l4ls_clkctrl AM3_L4LS_MMC1_CLKCTRL 0>;
1319 clock-names = "fck";
1320 #address-cells = <1>;
1321 #size-cells = <1>;
1322 ranges = <0x0 0x60000 0x1000>;
1324 mmc1: mmc@0 {
1325 compatible = "ti,omap4-hsmmc";
1326 ti,dual-volt;
1327 ti,needs-special-reset;
1328 ti,needs-special-hs-handling;
1329 dmas = <&edma_xbar 24 0 0
1330 &edma_xbar 25 0 0>;
1331 dma-names = "tx", "rx";
1332 interrupts = <64>;
1333 reg = <0x0 0x1000>;
1334 status = "disabled";
1335 };
1336 };
1338 target-module@80000 { /* 0x48080000, ap 38 18.0 */
1339 compatible = "ti,sysc-omap2", "ti,sysc";
1340 reg = <0x80000 0x4>,
1341 <0x80010 0x4>,
1342 <0x80014 0x4>;
1343 reg-names = "rev", "sysc", "syss";
1344 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1345 SYSC_OMAP2_SOFTRESET |
1346 SYSC_OMAP2_AUTOIDLE)>;
1347 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1348 <SYSC_IDLE_NO>,
1349 <SYSC_IDLE_SMART>;
1350 ti,syss-mask = <1>;
1351 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1352 clocks = <&l4ls_clkctrl AM3_L4LS_ELM_CLKCTRL 0>;
1353 clock-names = "fck";
1354 #address-cells = <1>;
1355 #size-cells = <1>;
1356 ranges = <0x0 0x80000 0x10000>;
1358 elm: elm@0 {
1359 compatible = "ti,am3352-elm";
1360 reg = <0x0 0x2000>;
1361 interrupts = <4>;
1362 status = "disabled";
1363 };
1364 };
1366 target-module@a0000 { /* 0x480a0000, ap 40 5e.0 */
1367 compatible = "ti,sysc";
1368 status = "disabled";
1369 #address-cells = <1>;
1370 #size-cells = <1>;
1371 ranges = <0x0 0xa0000 0x10000>;
1372 };
1374 target-module@c8000 { /* 0x480c8000, ap 87 06.0 */
1375 compatible = "ti,sysc-omap4", "ti,sysc";
1376 reg = <0xc8000 0x4>,
1377 <0xc8010 0x4>;
1378 reg-names = "rev", "sysc";
1379 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
1380 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1381 <SYSC_IDLE_NO>,
1382 <SYSC_IDLE_SMART>;
1383 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1384 clocks = <&l4ls_clkctrl AM3_L4LS_MAILBOX_CLKCTRL 0>;
1385 clock-names = "fck";
1386 #address-cells = <1>;
1387 #size-cells = <1>;
1388 ranges = <0x0 0xc8000 0x1000>;
1390 mailbox: mailbox@0 {
1391 compatible = "ti,omap4-mailbox";
1392 reg = <0x0 0x200>;
1393 interrupts = <77>;
1394 #mbox-cells = <1>;
1395 ti,mbox-num-users = <4>;
1396 ti,mbox-num-fifos = <8>;
1397 mbox_wkupm3: wkup_m3 {
1398 ti,mbox-send-noirq;
1399 ti,mbox-tx = <0 0 0>;
1400 ti,mbox-rx = <0 0 3>;
1401 };
1402 };
1403 };
1405 target-module@ca000 { /* 0x480ca000, ap 91 40.0 */
1406 compatible = "ti,sysc-omap2", "ti,sysc";
1407 reg = <0xca000 0x4>,
1408 <0xca010 0x4>,
1409 <0xca014 0x4>;
1410 reg-names = "rev", "sysc", "syss";
1411 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1412 SYSC_OMAP2_ENAWAKEUP |
1413 SYSC_OMAP2_SOFTRESET |
1414 SYSC_OMAP2_AUTOIDLE)>;
1415 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1416 <SYSC_IDLE_NO>,
1417 <SYSC_IDLE_SMART>;
1418 ti,syss-mask = <1>;
1419 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1420 clocks = <&l4ls_clkctrl AM3_L4LS_SPINLOCK_CLKCTRL 0>;
1421 clock-names = "fck";
1422 #address-cells = <1>;
1423 #size-cells = <1>;
1424 ranges = <0x0 0xca000 0x1000>;
1426 hwspinlock: spinlock@0 {
1427 compatible = "ti,omap4-hwspinlock";
1428 reg = <0x0 0x1000>;
1429 #hwlock-cells = <1>;
1430 };
1431 };
1433 target-module@cc000 { /* 0x480cc000, ap 89 0e.0 */
1434 compatible = "ti,sysc";
1435 status = "disabled";
1436 #address-cells = <1>;
1437 #size-cells = <1>;
1438 ranges = <0x0 0xcc000 0x1000>;
1439 };
1440 };
1442 segment@100000 { /* 0x48100000 */
1443 compatible = "simple-bus";
1444 #address-cells = <1>;
1445 #size-cells = <1>;
1446 ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 42 */
1447 <0x0008d000 0x0018d000 0x001000>, /* ap 43 */
1448 <0x0008e000 0x0018e000 0x001000>, /* ap 44 */
1449 <0x0008f000 0x0018f000 0x001000>, /* ap 45 */
1450 <0x0009c000 0x0019c000 0x001000>, /* ap 46 */
1451 <0x0009d000 0x0019d000 0x001000>, /* ap 47 */
1452 <0x000a6000 0x001a6000 0x001000>, /* ap 48 */
1453 <0x000a7000 0x001a7000 0x001000>, /* ap 49 */
1454 <0x000a8000 0x001a8000 0x001000>, /* ap 50 */
1455 <0x000a9000 0x001a9000 0x001000>, /* ap 51 */
1456 <0x000aa000 0x001aa000 0x001000>, /* ap 52 */
1457 <0x000ab000 0x001ab000 0x001000>, /* ap 53 */
1458 <0x000ac000 0x001ac000 0x001000>, /* ap 54 */
1459 <0x000ad000 0x001ad000 0x001000>, /* ap 55 */
1460 <0x000ae000 0x001ae000 0x001000>, /* ap 56 */
1461 <0x000af000 0x001af000 0x001000>, /* ap 57 */
1462 <0x000b0000 0x001b0000 0x010000>, /* ap 58 */
1463 <0x000c0000 0x001c0000 0x001000>, /* ap 59 */
1464 <0x000cc000 0x001cc000 0x002000>, /* ap 60 */
1465 <0x000ce000 0x001ce000 0x002000>, /* ap 61 */
1466 <0x000d0000 0x001d0000 0x002000>, /* ap 62 */
1467 <0x000d2000 0x001d2000 0x002000>, /* ap 63 */
1468 <0x000d8000 0x001d8000 0x001000>, /* ap 64 */
1469 <0x000d9000 0x001d9000 0x001000>, /* ap 65 */
1470 <0x000a0000 0x001a0000 0x001000>, /* ap 79 */
1471 <0x000a1000 0x001a1000 0x001000>, /* ap 80 */
1472 <0x000a2000 0x001a2000 0x001000>, /* ap 81 */
1473 <0x000a3000 0x001a3000 0x001000>, /* ap 82 */
1474 <0x000a4000 0x001a4000 0x001000>, /* ap 83 */
1475 <0x000a5000 0x001a5000 0x001000>; /* ap 84 */
1477 target-module@8c000 { /* 0x4818c000, ap 42 04.0 */
1478 compatible = "ti,sysc";
1479 status = "disabled";
1480 #address-cells = <1>;
1481 #size-cells = <1>;
1482 ranges = <0x0 0x8c000 0x1000>;
1483 };
1485 target-module@8e000 { /* 0x4818e000, ap 44 0a.0 */
1486 compatible = "ti,sysc";
1487 status = "disabled";
1488 #address-cells = <1>;
1489 #size-cells = <1>;
1490 ranges = <0x0 0x8e000 0x1000>;
1491 };
1493 target-module@9c000 { /* 0x4819c000, ap 46 5a.0 */
1494 compatible = "ti,sysc-omap2", "ti,sysc";
1495 reg = <0x9c000 0x8>,
1496 <0x9c010 0x8>,
1497 <0x9c090 0x8>;
1498 reg-names = "rev", "sysc", "syss";
1499 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1500 SYSC_OMAP2_ENAWAKEUP |
1501 SYSC_OMAP2_SOFTRESET |
1502 SYSC_OMAP2_AUTOIDLE)>;
1503 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1504 <SYSC_IDLE_NO>,
1505 <SYSC_IDLE_SMART>,
1506 <SYSC_IDLE_SMART_WKUP>;
1507 ti,syss-mask = <1>;
1508 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1509 clocks = <&l4ls_clkctrl AM3_L4LS_I2C3_CLKCTRL 0>;
1510 clock-names = "fck";
1511 #address-cells = <1>;
1512 #size-cells = <1>;
1513 ranges = <0x0 0x9c000 0x1000>;
1515 i2c2: i2c@0 {
1516 compatible = "ti,omap4-i2c";
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1519 reg = <0x0 0x1000>;
1520 interrupts = <30>;
1521 status = "disabled";
1522 };
1523 };
1525 target-module@a0000 { /* 0x481a0000, ap 79 24.0 */
1526 compatible = "ti,sysc-omap2", "ti,sysc";
1527 reg = <0xa0000 0x4>,
1528 <0xa0110 0x4>,
1529 <0xa0114 0x4>;
1530 reg-names = "rev", "sysc", "syss";
1531 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1532 SYSC_OMAP2_SOFTRESET |
1533 SYSC_OMAP2_AUTOIDLE)>;
1534 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1535 <SYSC_IDLE_NO>,
1536 <SYSC_IDLE_SMART>;
1537 ti,syss-mask = <1>;
1538 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1539 clocks = <&l4ls_clkctrl AM3_L4LS_SPI1_CLKCTRL 0>;
1540 clock-names = "fck";
1541 #address-cells = <1>;
1542 #size-cells = <1>;
1543 ranges = <0x0 0xa0000 0x1000>;
1545 spi1: spi@0 {
1546 compatible = "ti,omap4-mcspi";
1547 #address-cells = <1>;
1548 #size-cells = <0>;
1549 reg = <0x0 0x400>;
1550 interrupts = <125>;
1551 ti,spi-num-cs = <2>;
1552 dmas = <&edma 42 0
1553 &edma 43 0
1554 &edma 44 0
1555 &edma 45 0>;
1556 dma-names = "tx0", "rx0", "tx1", "rx1";
1557 status = "disabled";
1558 };
1559 };
1561 target-module@a2000 { /* 0x481a2000, ap 81 2e.0 */
1562 compatible = "ti,sysc";
1563 status = "disabled";
1564 #address-cells = <1>;
1565 #size-cells = <1>;
1566 ranges = <0x0 0xa2000 0x1000>;
1567 };
1569 target-module@a4000 { /* 0x481a4000, ap 83 30.0 */
1570 compatible = "ti,sysc";
1571 status = "disabled";
1572 #address-cells = <1>;
1573 #size-cells = <1>;
1574 ranges = <0x0 0xa4000 0x1000>;
1575 };
1577 target-module@a6000 { /* 0x481a6000, ap 48 16.0 */
1578 compatible = "ti,sysc-omap2", "ti,sysc";
1579 reg = <0xa6050 0x4>,
1580 <0xa6054 0x4>,
1581 <0xa6058 0x4>;
1582 reg-names = "rev", "sysc", "syss";
1583 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1584 SYSC_OMAP2_SOFTRESET |
1585 SYSC_OMAP2_AUTOIDLE)>;
1586 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1587 <SYSC_IDLE_NO>,
1588 <SYSC_IDLE_SMART>,
1589 <SYSC_IDLE_SMART_WKUP>;
1590 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1591 clocks = <&l4ls_clkctrl AM3_L4LS_UART4_CLKCTRL 0>;
1592 clock-names = "fck";
1593 #address-cells = <1>;
1594 #size-cells = <1>;
1595 ranges = <0x0 0xa6000 0x1000>;
1597 uart3: serial@0 {
1598 compatible = "ti,am3352-uart", "ti,omap3-uart";
1599 clock-frequency = <48000000>;
1600 reg = <0x0 0x1000>;
1601 interrupts = <44>;
1602 status = "disabled";
1603 };
1604 };
1606 target-module@a8000 { /* 0x481a8000, ap 50 20.0 */
1607 compatible = "ti,sysc-omap2", "ti,sysc";
1608 reg = <0xa8050 0x4>,
1609 <0xa8054 0x4>,
1610 <0xa8058 0x4>;
1611 reg-names = "rev", "sysc", "syss";
1612 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1613 SYSC_OMAP2_SOFTRESET |
1614 SYSC_OMAP2_AUTOIDLE)>;
1615 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1616 <SYSC_IDLE_NO>,
1617 <SYSC_IDLE_SMART>,
1618 <SYSC_IDLE_SMART_WKUP>;
1619 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1620 clocks = <&l4ls_clkctrl AM3_L4LS_UART5_CLKCTRL 0>;
1621 clock-names = "fck";
1622 #address-cells = <1>;
1623 #size-cells = <1>;
1624 ranges = <0x0 0xa8000 0x1000>;
1626 uart4: serial@0 {
1627 compatible = "ti,am3352-uart", "ti,omap3-uart";
1628 clock-frequency = <48000000>;
1629 reg = <0x0 0x1000>;
1630 interrupts = <45>;
1631 status = "disabled";
1632 };
1633 };
1635 target-module@aa000 { /* 0x481aa000, ap 52 1a.0 */
1636 compatible = "ti,sysc-omap2", "ti,sysc";
1637 reg = <0xaa050 0x4>,
1638 <0xaa054 0x4>,
1639 <0xaa058 0x4>;
1640 reg-names = "rev", "sysc", "syss";
1641 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1642 SYSC_OMAP2_SOFTRESET |
1643 SYSC_OMAP2_AUTOIDLE)>;
1644 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1645 <SYSC_IDLE_NO>,
1646 <SYSC_IDLE_SMART>,
1647 <SYSC_IDLE_SMART_WKUP>;
1648 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1649 clocks = <&l4ls_clkctrl AM3_L4LS_UART6_CLKCTRL 0>;
1650 clock-names = "fck";
1651 #address-cells = <1>;
1652 #size-cells = <1>;
1653 ranges = <0x0 0xaa000 0x1000>;
1655 uart5: serial@0 {
1656 compatible = "ti,am3352-uart", "ti,omap3-uart";
1657 clock-frequency = <48000000>;
1658 reg = <0x0 0x1000>;
1659 interrupts = <46>;
1660 status = "disabled";
1661 };
1662 };
1664 target-module@ac000 { /* 0x481ac000, ap 54 38.0 */
1665 compatible = "ti,sysc-omap2", "ti,sysc";
1666 reg = <0xac000 0x4>,
1667 <0xac010 0x4>,
1668 <0xac114 0x4>;
1669 reg-names = "rev", "sysc", "syss";
1670 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1671 SYSC_OMAP2_SOFTRESET |
1672 SYSC_OMAP2_AUTOIDLE)>;
1673 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1674 <SYSC_IDLE_NO>,
1675 <SYSC_IDLE_SMART>,
1676 <SYSC_IDLE_SMART_WKUP>;
1677 ti,syss-mask = <1>;
1678 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1679 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 0>,
1680 <&l4ls_clkctrl AM3_L4LS_GPIO3_CLKCTRL 18>;
1681 clock-names = "fck", "dbclk";
1682 #address-cells = <1>;
1683 #size-cells = <1>;
1684 ranges = <0x0 0xac000 0x1000>;
1686 gpio2: gpio@0 {
1687 compatible = "ti,omap4-gpio";
1688 gpio-controller;
1689 #gpio-cells = <2>;
1690 interrupt-controller;
1691 #interrupt-cells = <2>;
1692 reg = <0x0 0x1000>;
1693 interrupts = <32>;
1694 };
1695 };
1697 target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */
1698 compatible = "ti,sysc-omap2", "ti,sysc";
1699 reg = <0xae000 0x4>,
1700 <0xae010 0x4>,
1701 <0xae114 0x4>;
1702 reg-names = "rev", "sysc", "syss";
1703 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1704 SYSC_OMAP2_SOFTRESET |
1705 SYSC_OMAP2_AUTOIDLE)>;
1706 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1707 <SYSC_IDLE_NO>,
1708 <SYSC_IDLE_SMART>,
1709 <SYSC_IDLE_SMART_WKUP>;
1710 ti,syss-mask = <1>;
1711 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1712 clocks = <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 0>,
1713 <&l4ls_clkctrl AM3_L4LS_GPIO4_CLKCTRL 18>;
1714 clock-names = "fck", "dbclk";
1715 #address-cells = <1>;
1716 #size-cells = <1>;
1717 ranges = <0x0 0xae000 0x1000>;
1719 gpio3: gpio@0 {
1720 compatible = "ti,omap4-gpio";
1721 gpio-controller;
1722 #gpio-cells = <2>;
1723 interrupt-controller;
1724 #interrupt-cells = <2>;
1725 reg = <0x0 0x1000>;
1726 interrupts = <62>;
1727 };
1728 };
1730 target-module@b0000 { /* 0x481b0000, ap 58 50.0 */
1731 compatible = "ti,sysc";
1732 status = "disabled";
1733 #address-cells = <1>;
1734 #size-cells = <1>;
1735 ranges = <0x0 0xb0000 0x10000>;
1736 };
1738 target-module@cc000 { /* 0x481cc000, ap 60 46.0 */
1739 compatible = "ti,sysc-omap4", "ti,sysc";
1740 reg = <0xcc020 0x4>;
1741 reg-names = "rev";
1742 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1743 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
1744 <&dcan0_fck>;
1745 clock-names = "fck", "osc";
1746 #address-cells = <1>;
1747 #size-cells = <1>;
1748 ranges = <0x0 0xcc000 0x2000>;
1750 dcan0: can@0 {
1751 compatible = "ti,am3352-d_can";
1752 reg = <0x0 0x2000>;
1753 clocks = <&dcan0_fck>;
1754 clock-names = "fck";
1755 syscon-raminit = <&scm_conf 0x644 0>;
1756 interrupts = <52>;
1757 status = "disabled";
1758 };
1759 };
1761 target-module@d0000 { /* 0x481d0000, ap 62 42.0 */
1762 compatible = "ti,sysc-omap4", "ti,sysc";
1763 reg = <0xd0020 0x4>;
1764 reg-names = "rev";
1765 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1766 clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
1767 <&dcan1_fck>;
1768 clock-names = "fck", "osc";
1769 #address-cells = <1>;
1770 #size-cells = <1>;
1771 ranges = <0x0 0xd0000 0x2000>;
1773 dcan1: can@0 {
1774 compatible = "ti,am3352-d_can";
1775 reg = <0x0 0x2000>;
1776 clocks = <&dcan1_fck>;
1777 clock-names = "fck";
1778 syscon-raminit = <&scm_conf 0x644 1>;
1779 interrupts = <55>;
1780 status = "disabled";
1781 };
1782 };
1784 target-module@d8000 { /* 0x481d8000, ap 64 66.0 */
1785 compatible = "ti,sysc-omap2", "ti,sysc";
1786 reg = <0xd82fc 0x4>,
1787 <0xd8110 0x4>,
1788 <0xd8114 0x4>;
1789 reg-names = "rev", "sysc", "syss";
1790 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1791 SYSC_OMAP2_ENAWAKEUP |
1792 SYSC_OMAP2_SOFTRESET |
1793 SYSC_OMAP2_AUTOIDLE)>;
1794 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1795 <SYSC_IDLE_NO>,
1796 <SYSC_IDLE_SMART>;
1797 ti,syss-mask = <1>;
1798 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1799 clocks = <&l4ls_clkctrl AM3_L4LS_MMC2_CLKCTRL 0>;
1800 clock-names = "fck";
1801 #address-cells = <1>;
1802 #size-cells = <1>;
1803 ranges = <0x0 0xd8000 0x1000>;
1805 mmc2: mmc@0 {
1806 compatible = "ti,omap4-hsmmc";
1807 ti,needs-special-reset;
1808 dmas = <&edma 2 0
1809 &edma 3 0>;
1810 dma-names = "tx", "rx";
1811 interrupts = <28>;
1812 reg = <0x0 0x1000>;
1813 status = "disabled";
1814 };
1815 };
1816 };
1818 segment@200000 { /* 0x48200000 */
1819 compatible = "simple-bus";
1820 #address-cells = <1>;
1821 #size-cells = <1>;
1822 };
1824 segment@300000 { /* 0x48300000 */
1825 compatible = "simple-bus";
1826 #address-cells = <1>;
1827 #size-cells = <1>;
1828 ranges = <0x00000000 0x00300000 0x001000>, /* ap 66 */
1829 <0x00001000 0x00301000 0x001000>, /* ap 67 */
1830 <0x00002000 0x00302000 0x001000>, /* ap 68 */
1831 <0x00003000 0x00303000 0x001000>, /* ap 69 */
1832 <0x00004000 0x00304000 0x001000>, /* ap 70 */
1833 <0x00005000 0x00305000 0x001000>, /* ap 71 */
1834 <0x0000e000 0x0030e000 0x001000>, /* ap 72 */
1835 <0x0000f000 0x0030f000 0x001000>, /* ap 73 */
1836 <0x00018000 0x00318000 0x004000>, /* ap 74 */
1837 <0x0001c000 0x0031c000 0x001000>, /* ap 75 */
1838 <0x00010000 0x00310000 0x002000>, /* ap 76 */
1839 <0x00012000 0x00312000 0x001000>, /* ap 93 */
1840 <0x00015000 0x00315000 0x001000>, /* ap 94 */
1841 <0x00016000 0x00316000 0x001000>, /* ap 95 */
1842 <0x00017000 0x00317000 0x001000>, /* ap 96 */
1843 <0x00013000 0x00313000 0x001000>, /* ap 97 */
1844 <0x00014000 0x00314000 0x001000>, /* ap 98 */
1845 <0x00020000 0x00320000 0x001000>, /* ap 99 */
1846 <0x00021000 0x00321000 0x001000>, /* ap 100 */
1847 <0x00022000 0x00322000 0x001000>, /* ap 101 */
1848 <0x00023000 0x00323000 0x001000>, /* ap 102 */
1849 <0x00024000 0x00324000 0x001000>, /* ap 103 */
1850 <0x00025000 0x00325000 0x001000>; /* ap 104 */
1852 target-module@0 { /* 0x48300000, ap 66 48.0 */
1853 compatible = "ti,sysc-omap4", "ti,sysc";
1854 reg = <0x0 0x4>,
1855 <0x4 0x4>;
1856 reg-names = "rev", "sysc";
1857 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1858 <SYSC_IDLE_NO>,
1859 <SYSC_IDLE_SMART>,
1860 <SYSC_IDLE_SMART_WKUP>;
1861 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1862 <SYSC_IDLE_NO>,
1863 <SYSC_IDLE_SMART>,
1864 <SYSC_IDLE_SMART_WKUP>;
1865 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1866 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>;
1867 clock-names = "fck";
1868 #address-cells = <1>;
1869 #size-cells = <1>;
1870 ranges = <0x0 0x0 0x1000>;
1872 epwmss0: epwmss@0 {
1873 compatible = "ti,am33xx-pwmss";
1874 reg = <0x0 0x10>;
1875 #address-cells = <1>;
1876 #size-cells = <1>;
1877 status = "disabled";
1878 ranges = <0 0 0x1000>;
1880 ecap0: ecap@100 {
1881 compatible = "ti,am3352-ecap",
1882 "ti,am33xx-ecap";
1883 #pwm-cells = <3>;
1884 reg = <0x100 0x80>;
1885 clocks = <&l4ls_gclk>;
1886 clock-names = "fck";
1887 interrupts = <31>;
1888 interrupt-names = "ecap0";
1889 status = "disabled";
1890 };
1892 ehrpwm0: pwm@200 {
1893 compatible = "ti,am3352-ehrpwm",
1894 "ti,am33xx-ehrpwm";
1895 #pwm-cells = <3>;
1896 reg = <0x200 0x80>;
1897 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
1898 clock-names = "tbclk", "fck";
1899 status = "disabled";
1900 };
1901 };
1902 };
1904 target-module@2000 { /* 0x48302000, ap 68 52.0 */
1905 compatible = "ti,sysc-omap4", "ti,sysc";
1906 reg = <0x2000 0x4>,
1907 <0x2004 0x4>;
1908 reg-names = "rev", "sysc";
1909 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1910 <SYSC_IDLE_NO>,
1911 <SYSC_IDLE_SMART>,
1912 <SYSC_IDLE_SMART_WKUP>;
1913 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1914 <SYSC_IDLE_NO>,
1915 <SYSC_IDLE_SMART>,
1916 <SYSC_IDLE_SMART_WKUP>;
1917 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1918 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS1_CLKCTRL 0>;
1919 clock-names = "fck";
1920 #address-cells = <1>;
1921 #size-cells = <1>;
1922 ranges = <0x0 0x2000 0x1000>;
1924 epwmss1: epwmss@0 {
1925 compatible = "ti,am33xx-pwmss";
1926 reg = <0x0 0x10>;
1927 #address-cells = <1>;
1928 #size-cells = <1>;
1929 status = "disabled";
1930 ranges = <0 0 0x1000>;
1932 ecap1: ecap@100 {
1933 compatible = "ti,am3352-ecap",
1934 "ti,am33xx-ecap";
1935 #pwm-cells = <3>;
1936 reg = <0x100 0x80>;
1937 clocks = <&l4ls_gclk>;
1938 clock-names = "fck";
1939 interrupts = <47>;
1940 interrupt-names = "ecap1";
1941 status = "disabled";
1942 };
1944 ehrpwm1: pwm@200 {
1945 compatible = "ti,am3352-ehrpwm",
1946 "ti,am33xx-ehrpwm";
1947 #pwm-cells = <3>;
1948 reg = <0x200 0x80>;
1949 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
1950 clock-names = "tbclk", "fck";
1951 status = "disabled";
1952 };
1953 };
1954 };
1956 target-module@4000 { /* 0x48304000, ap 70 44.0 */
1957 compatible = "ti,sysc-omap4", "ti,sysc";
1958 reg = <0x4000 0x4>,
1959 <0x4004 0x4>;
1960 reg-names = "rev", "sysc";
1961 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1962 <SYSC_IDLE_NO>,
1963 <SYSC_IDLE_SMART>,
1964 <SYSC_IDLE_SMART_WKUP>;
1965 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1966 <SYSC_IDLE_NO>,
1967 <SYSC_IDLE_SMART>,
1968 <SYSC_IDLE_SMART_WKUP>;
1969 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
1970 clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS2_CLKCTRL 0>;
1971 clock-names = "fck";
1972 #address-cells = <1>;
1973 #size-cells = <1>;
1974 ranges = <0x0 0x4000 0x1000>;
1976 epwmss2: epwmss@0 {
1977 compatible = "ti,am33xx-pwmss";
1978 reg = <0x0 0x10>;
1979 #address-cells = <1>;
1980 #size-cells = <1>;
1981 status = "disabled";
1982 ranges = <0 0 0x1000>;
1984 ecap2: ecap@100 {
1985 compatible = "ti,am3352-ecap",
1986 "ti,am33xx-ecap";
1987 #pwm-cells = <3>;
1988 reg = <0x100 0x80>;
1989 clocks = <&l4ls_gclk>;
1990 clock-names = "fck";
1991 interrupts = <61>;
1992 interrupt-names = "ecap2";
1993 status = "disabled";
1994 };
1996 ehrpwm2: pwm@200 {
1997 compatible = "ti,am3352-ehrpwm",
1998 "ti,am33xx-ehrpwm";
1999 #pwm-cells = <3>;
2000 reg = <0x200 0x80>;
2001 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
2002 clock-names = "tbclk", "fck";
2003 status = "disabled";
2004 };
2005 };
2006 };
2008 target-module@e000 { /* 0x4830e000, ap 72 4a.0 */
2009 compatible = "ti,sysc-omap4", "ti,sysc";
2010 reg = <0xe000 0x4>,
2011 <0xe054 0x4>;
2012 reg-names = "rev", "sysc";
2013 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2014 <SYSC_IDLE_NO>,
2015 <SYSC_IDLE_SMART>;
2016 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2017 <SYSC_IDLE_NO>,
2018 <SYSC_IDLE_SMART>;
2019 /* Domains (P, C): per_pwrdm, lcdc_clkdm */
2020 clocks = <&lcdc_clkctrl AM3_LCDC_LCDC_CLKCTRL 0>;
2021 clock-names = "fck";
2022 #address-cells = <1>;
2023 #size-cells = <1>;
2024 ranges = <0x0 0xe000 0x1000>;
2026 lcdc: lcdc@0 {
2027 compatible = "ti,am33xx-tilcdc";
2028 reg = <0x0 0x1000>;
2029 interrupts = <36>;
2030 status = "disabled";
2031 };
2032 };
2034 target-module@10000 { /* 0x48310000, ap 76 4e.1 */
2035 compatible = "ti,sysc-omap2", "ti,sysc";
2036 reg = <0x11fe0 0x4>,
2037 <0x11fe4 0x4>;
2038 reg-names = "rev", "sysc";
2039 ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
2040 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2041 <SYSC_IDLE_NO>;
2042 /* Domains (P, C): per_pwrdm, l4ls_clkdm */
2043 clocks = <&l4ls_clkctrl AM3_L4LS_RNG_CLKCTRL 0>;
2044 clock-names = "fck";
2045 #address-cells = <1>;
2046 #size-cells = <1>;
2047 ranges = <0x0 0x10000 0x2000>;
2049 rng: rng@0 {
2050 compatible = "ti,omap4-rng";
2051 reg = <0x0 0x2000>;
2052 interrupts = <111>;
2053 };
2054 };
2056 target-module@13000 { /* 0x48313000, ap 97 62.0 */
2057 compatible = "ti,sysc";
2058 status = "disabled";
2059 #address-cells = <1>;
2060 #size-cells = <1>;
2061 ranges = <0x0 0x13000 0x1000>;
2062 };
2064 target-module@15000 { /* 0x48315000, ap 94 56.0 */
2065 compatible = "ti,sysc";
2066 status = "disabled";
2067 #address-cells = <1>;
2068 #size-cells = <1>;
2069 ranges = <0x00000000 0x00015000 0x00001000>,
2070 <0x00001000 0x00016000 0x00001000>;
2071 };
2073 target-module@18000 { /* 0x48318000, ap 74 4c.0 */
2074 compatible = "ti,sysc";
2075 status = "disabled";
2076 #address-cells = <1>;
2077 #size-cells = <1>;
2078 ranges = <0x0 0x18000 0x4000>;
2079 };
2081 target-module@20000 { /* 0x48320000, ap 99 34.0 */
2082 compatible = "ti,sysc";
2083 status = "disabled";
2084 #address-cells = <1>;
2085 #size-cells = <1>;
2086 ranges = <0x0 0x20000 0x1000>;
2087 };
2089 target-module@22000 { /* 0x48322000, ap 101 3e.0 */
2090 compatible = "ti,sysc";
2091 status = "disabled";
2092 #address-cells = <1>;
2093 #size-cells = <1>;
2094 ranges = <0x0 0x22000 0x1000>;
2095 };
2097 target-module@24000 { /* 0x48324000, ap 103 68.0 */
2098 compatible = "ti,sysc";
2099 status = "disabled";
2100 #address-cells = <1>;
2101 #size-cells = <1>;
2102 ranges = <0x0 0x24000 0x1000>;
2103 };
2104 };
2105 };