| blob | d1e684d0acfd5d442bc8af30ba92689fdae8fda2 |
1 // SPDX-License-Identifier: GPL-2.0
2 #include "bcm283x.dtsi"
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
7 / {
8 compatible = "brcm,bcm2711";
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
15 soc {
16 /*
17 * Defined ranges:
18 * Common BCM283x peripherals
19 * BCM2711-specific peripherals
20 * ARM-local peripherals
21 */
22 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
23 <0x7c000000 0x0 0xfc000000 0x02000000>,
24 <0x40000000 0x0 0xff800000 0x00800000>;
25 /* Emulate a contiguous 30-bit address range for DMA */
26 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
28 /*
29 * This node is the provider for the enable-method for
30 * bringing up secondary cores.
31 */
32 local_intc: local_intc@40000000 {
33 compatible = "brcm,bcm2836-l1-intc";
34 reg = <0x40000000 0x100>;
35 };
37 gicv2: interrupt-controller@40041000 {
38 interrupt-controller;
39 #interrupt-cells = <3>;
40 compatible = "arm,gic-400";
41 reg = <0x40041000 0x1000>,
42 <0x40042000 0x2000>,
43 <0x40044000 0x2000>,
44 <0x40046000 0x2000>;
45 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
46 IRQ_TYPE_LEVEL_HIGH)>;
47 };
49 avs_monitor: avs-monitor@7d5d2000 {
50 compatible = "brcm,bcm2711-avs-monitor",
51 "syscon", "simple-mfd";
52 reg = <0x7d5d2000 0xf00>;
54 thermal: thermal {
55 compatible = "brcm,bcm2711-thermal";
56 #thermal-sensor-cells = <0>;
57 };
58 };
60 dma: dma@7e007000 {
61 compatible = "brcm,bcm2835-dma";
62 reg = <0x7e007000 0xb00>;
63 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
70 /* DMA lite 7 - 10 */
71 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
75 interrupt-names = "dma0",
76 "dma1",
77 "dma2",
78 "dma3",
79 "dma4",
80 "dma5",
81 "dma6",
82 "dma7",
83 "dma8",
84 "dma9",
85 "dma10";
86 #dma-cells = <1>;
87 brcm,dma-channel-mask = <0x07f5>;
88 };
90 pm: watchdog@7e100000 {
91 compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
92 #power-domain-cells = <1>;
93 #reset-cells = <1>;
94 reg = <0x7e100000 0x114>,
95 <0x7e00a000 0x24>,
96 <0x7ec11000 0x20>;
97 clocks = <&clocks BCM2835_CLOCK_V3D>,
98 <&clocks BCM2835_CLOCK_PERI_IMAGE>,
99 <&clocks BCM2835_CLOCK_H264>,
100 <&clocks BCM2835_CLOCK_ISP>;
101 clock-names = "v3d", "peri_image", "h264", "isp";
102 system-power-controller;
103 };
105 rng@7e104000 {
106 compatible = "brcm,bcm2711-rng200";
107 reg = <0x7e104000 0x28>;
108 };
110 uart2: serial@7e201400 {
111 compatible = "arm,pl011", "arm,primecell";
112 reg = <0x7e201400 0x200>;
113 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&clocks BCM2835_CLOCK_UART>,
115 <&clocks BCM2835_CLOCK_VPU>;
116 clock-names = "uartclk", "apb_pclk";
117 arm,primecell-periphid = <0x00241011>;
118 status = "disabled";
119 };
121 uart3: serial@7e201600 {
122 compatible = "arm,pl011", "arm,primecell";
123 reg = <0x7e201600 0x200>;
124 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&clocks BCM2835_CLOCK_UART>,
126 <&clocks BCM2835_CLOCK_VPU>;
127 clock-names = "uartclk", "apb_pclk";
128 arm,primecell-periphid = <0x00241011>;
129 status = "disabled";
130 };
132 uart4: serial@7e201800 {
133 compatible = "arm,pl011", "arm,primecell";
134 reg = <0x7e201800 0x200>;
135 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&clocks BCM2835_CLOCK_UART>,
137 <&clocks BCM2835_CLOCK_VPU>;
138 clock-names = "uartclk", "apb_pclk";
139 arm,primecell-periphid = <0x00241011>;
140 status = "disabled";
141 };
143 uart5: serial@7e201a00 {
144 compatible = "arm,pl011", "arm,primecell";
145 reg = <0x7e201a00 0x200>;
146 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&clocks BCM2835_CLOCK_UART>,
148 <&clocks BCM2835_CLOCK_VPU>;
149 clock-names = "uartclk", "apb_pclk";
150 arm,primecell-periphid = <0x00241011>;
151 status = "disabled";
152 };
154 spi3: spi@7e204600 {
155 compatible = "brcm,bcm2835-spi";
156 reg = <0x7e204600 0x0200>;
157 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&clocks BCM2835_CLOCK_VPU>;
159 #address-cells = <1>;
160 #size-cells = <0>;
161 status = "disabled";
162 };
164 spi4: spi@7e204800 {
165 compatible = "brcm,bcm2835-spi";
166 reg = <0x7e204800 0x0200>;
167 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&clocks BCM2835_CLOCK_VPU>;
169 #address-cells = <1>;
170 #size-cells = <0>;
171 status = "disabled";
172 };
174 spi5: spi@7e204a00 {
175 compatible = "brcm,bcm2835-spi";
176 reg = <0x7e204a00 0x0200>;
177 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&clocks BCM2835_CLOCK_VPU>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181 status = "disabled";
182 };
184 spi6: spi@7e204c00 {
185 compatible = "brcm,bcm2835-spi";
186 reg = <0x7e204c00 0x0200>;
187 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&clocks BCM2835_CLOCK_VPU>;
189 #address-cells = <1>;
190 #size-cells = <0>;
191 status = "disabled";
192 };
194 i2c3: i2c@7e205600 {
195 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
196 reg = <0x7e205600 0x200>;
197 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&clocks BCM2835_CLOCK_VPU>;
199 #address-cells = <1>;
200 #size-cells = <0>;
201 status = "disabled";
202 };
204 i2c4: i2c@7e205800 {
205 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
206 reg = <0x7e205800 0x200>;
207 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&clocks BCM2835_CLOCK_VPU>;
209 #address-cells = <1>;
210 #size-cells = <0>;
211 status = "disabled";
212 };
214 i2c5: i2c@7e205a00 {
215 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
216 reg = <0x7e205a00 0x200>;
217 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&clocks BCM2835_CLOCK_VPU>;
219 #address-cells = <1>;
220 #size-cells = <0>;
221 status = "disabled";
222 };
224 i2c6: i2c@7e205c00 {
225 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
226 reg = <0x7e205c00 0x200>;
227 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&clocks BCM2835_CLOCK_VPU>;
229 #address-cells = <1>;
230 #size-cells = <0>;
231 status = "disabled";
232 };
234 pwm1: pwm@7e20c800 {
235 compatible = "brcm,bcm2835-pwm";
236 reg = <0x7e20c800 0x28>;
237 clocks = <&clocks BCM2835_CLOCK_PWM>;
238 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
239 assigned-clock-rates = <10000000>;
240 #pwm-cells = <2>;
241 status = "disabled";
242 };
244 emmc2: emmc2@7e340000 {
245 compatible = "brcm,bcm2711-emmc2";
246 reg = <0x7e340000 0x100>;
247 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&clocks BCM2711_CLOCK_EMMC2>;
249 status = "disabled";
250 };
252 hvs@7e400000 {
253 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
254 };
255 };
257 arm-pmu {
258 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
259 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
263 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
264 };
266 timer {
267 compatible = "arm,armv8-timer";
268 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
269 IRQ_TYPE_LEVEL_LOW)>,
270 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
271 IRQ_TYPE_LEVEL_LOW)>,
272 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
273 IRQ_TYPE_LEVEL_LOW)>,
274 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
275 IRQ_TYPE_LEVEL_LOW)>;
276 /* This only applies to the ARMv7 stub */
277 arm,cpu-registers-not-fw-configured;
278 };
280 cpus: cpus {
281 #address-cells = <1>;
282 #size-cells = <0>;
283 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
285 cpu0: cpu@0 {
286 device_type = "cpu";
287 compatible = "arm,cortex-a72";
288 reg = <0>;
289 enable-method = "spin-table";
290 cpu-release-addr = <0x0 0x000000d8>;
291 };
293 cpu1: cpu@1 {
294 device_type = "cpu";
295 compatible = "arm,cortex-a72";
296 reg = <1>;
297 enable-method = "spin-table";
298 cpu-release-addr = <0x0 0x000000e0>;
299 };
301 cpu2: cpu@2 {
302 device_type = "cpu";
303 compatible = "arm,cortex-a72";
304 reg = <2>;
305 enable-method = "spin-table";
306 cpu-release-addr = <0x0 0x000000e8>;
307 };
309 cpu3: cpu@3 {
310 device_type = "cpu";
311 compatible = "arm,cortex-a72";
312 reg = <3>;
313 enable-method = "spin-table";
314 cpu-release-addr = <0x0 0x000000f0>;
315 };
316 };
318 scb {
319 compatible = "simple-bus";
320 #address-cells = <2>;
321 #size-cells = <1>;
323 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
324 <0x6 0x00000000 0x6 0x00000000 0x40000000>;
326 pcie0: pcie@7d500000 {
327 compatible = "brcm,bcm2711-pcie";
328 reg = <0x0 0x7d500000 0x9310>;
329 device_type = "pci";
330 #address-cells = <3>;
331 #interrupt-cells = <1>;
332 #size-cells = <2>;
333 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
335 interrupt-names = "pcie", "msi";
336 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
337 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
338 IRQ_TYPE_LEVEL_HIGH>;
339 msi-controller;
340 msi-parent = <&pcie0>;
342 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
343 0x0 0x04000000>;
344 /*
345 * The wrapper around the PCIe block has a bug
346 * preventing it from accessing beyond the first 3GB of
347 * memory.
348 */
349 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
350 0x0 0xc0000000>;
351 brcm,enable-ssc;
352 };
354 genet: ethernet@7d580000 {
355 compatible = "brcm,bcm2711-genet-v5";
356 reg = <0x0 0x7d580000 0x10000>;
357 #address-cells = <0x1>;
358 #size-cells = <0x1>;
359 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
361 status = "disabled";
363 genet_mdio: mdio@e14 {
364 compatible = "brcm,genet-mdio-v5";
365 reg = <0xe14 0x8>;
366 reg-names = "mdio";
367 #address-cells = <0x0>;
368 #size-cells = <0x1>;
369 };
370 };
371 };
372 };
374 &clk_osc {
375 clock-frequency = <54000000>;
376 };
378 &clocks {
379 compatible = "brcm,bcm2711-cprman";
380 };
382 &cpu_thermal {
383 coefficients = <(-487) 410040>;
384 thermal-sensors = <&thermal>;
385 };
387 &dsi0 {
388 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
389 };
391 &dsi1 {
392 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
393 };
395 &gpio {
396 compatible = "brcm,bcm2711-gpio";
397 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
402 gpclk0_gpio49: gpclk0_gpio49 {
403 pin-gpclk {
404 pins = "gpio49";
405 function = "alt1";
406 bias-disable;
407 };
408 };
409 gpclk1_gpio50: gpclk1_gpio50 {
410 pin-gpclk {
411 pins = "gpio50";
412 function = "alt1";
413 bias-disable;
414 };
415 };
416 gpclk2_gpio51: gpclk2_gpio51 {
417 pin-gpclk {
418 pins = "gpio51";
419 function = "alt1";
420 bias-disable;
421 };
422 };
424 i2c0_gpio46: i2c0_gpio46 {
425 pin-sda {
426 function = "alt0";
427 pins = "gpio46";
428 bias-pull-up;
429 };
430 pin-scl {
431 function = "alt0";
432 pins = "gpio47";
433 bias-disable;
434 };
435 };
436 i2c1_gpio46: i2c1_gpio46 {
437 pin-sda {
438 function = "alt1";
439 pins = "gpio46";
440 bias-pull-up;
441 };
442 pin-scl {
443 function = "alt1";
444 pins = "gpio47";
445 bias-disable;
446 };
447 };
448 i2c3_gpio2: i2c3_gpio2 {
449 pin-sda {
450 function = "alt5";
451 pins = "gpio2";
452 bias-pull-up;
453 };
454 pin-scl {
455 function = "alt5";
456 pins = "gpio3";
457 bias-disable;
458 };
459 };
460 i2c3_gpio4: i2c3_gpio4 {
461 pin-sda {
462 function = "alt5";
463 pins = "gpio4";
464 bias-pull-up;
465 };
466 pin-scl {
467 function = "alt5";
468 pins = "gpio5";
469 bias-disable;
470 };
471 };
472 i2c4_gpio6: i2c4_gpio6 {
473 pin-sda {
474 function = "alt5";
475 pins = "gpio6";
476 bias-pull-up;
477 };
478 pin-scl {
479 function = "alt5";
480 pins = "gpio7";
481 bias-disable;
482 };
483 };
484 i2c4_gpio8: i2c4_gpio8 {
485 pin-sda {
486 function = "alt5";
487 pins = "gpio8";
488 bias-pull-up;
489 };
490 pin-scl {
491 function = "alt5";
492 pins = "gpio9";
493 bias-disable;
494 };
495 };
496 i2c5_gpio10: i2c5_gpio10 {
497 pin-sda {
498 function = "alt5";
499 pins = "gpio10";
500 bias-pull-up;
501 };
502 pin-scl {
503 function = "alt5";
504 pins = "gpio11";
505 bias-disable;
506 };
507 };
508 i2c5_gpio12: i2c5_gpio12 {
509 pin-sda {
510 function = "alt5";
511 pins = "gpio12";
512 bias-pull-up;
513 };
514 pin-scl {
515 function = "alt5";
516 pins = "gpio13";
517 bias-disable;
518 };
519 };
520 i2c6_gpio0: i2c6_gpio0 {
521 pin-sda {
522 function = "alt5";
523 pins = "gpio0";
524 bias-pull-up;
525 };
526 pin-scl {
527 function = "alt5";
528 pins = "gpio1";
529 bias-disable;
530 };
531 };
532 i2c6_gpio22: i2c6_gpio22 {
533 pin-sda {
534 function = "alt5";
535 pins = "gpio22";
536 bias-pull-up;
537 };
538 pin-scl {
539 function = "alt5";
540 pins = "gpio23";
541 bias-disable;
542 };
543 };
544 i2c_slave_gpio8: i2c_slave_gpio8 {
545 pins-i2c-slave {
546 pins = "gpio8",
547 "gpio9",
548 "gpio10",
549 "gpio11";
550 function = "alt3";
551 };
552 };
554 jtag_gpio48: jtag_gpio48 {
555 pins-jtag {
556 pins = "gpio48",
557 "gpio49",
558 "gpio50",
559 "gpio51",
560 "gpio52",
561 "gpio53";
562 function = "alt4";
563 };
564 };
566 mii_gpio28: mii_gpio28 {
567 pins-mii {
568 pins = "gpio28",
569 "gpio29",
570 "gpio30",
571 "gpio31";
572 function = "alt4";
573 };
574 };
575 mii_gpio36: mii_gpio36 {
576 pins-mii {
577 pins = "gpio36",
578 "gpio37",
579 "gpio38",
580 "gpio39";
581 function = "alt5";
582 };
583 };
585 pcm_gpio50: pcm_gpio50 {
586 pins-pcm {
587 pins = "gpio50",
588 "gpio51",
589 "gpio52",
590 "gpio53";
591 function = "alt2";
592 };
593 };
595 pwm0_0_gpio12: pwm0_0_gpio12 {
596 pin-pwm {
597 pins = "gpio12";
598 function = "alt0";
599 bias-disable;
600 };
601 };
602 pwm0_0_gpio18: pwm0_0_gpio18 {
603 pin-pwm {
604 pins = "gpio18";
605 function = "alt5";
606 bias-disable;
607 };
608 };
609 pwm1_0_gpio40: pwm1_0_gpio40 {
610 pin-pwm {
611 pins = "gpio40";
612 function = "alt0";
613 bias-disable;
614 };
615 };
616 pwm0_1_gpio13: pwm0_1_gpio13 {
617 pin-pwm {
618 pins = "gpio13";
619 function = "alt0";
620 bias-disable;
621 };
622 };
623 pwm0_1_gpio19: pwm0_1_gpio19 {
624 pin-pwm {
625 pins = "gpio19";
626 function = "alt5";
627 bias-disable;
628 };
629 };
630 pwm1_1_gpio41: pwm1_1_gpio41 {
631 pin-pwm {
632 pins = "gpio41";
633 function = "alt0";
634 bias-disable;
635 };
636 };
637 pwm0_1_gpio45: pwm0_1_gpio45 {
638 pin-pwm {
639 pins = "gpio45";
640 function = "alt0";
641 bias-disable;
642 };
643 };
644 pwm0_0_gpio52: pwm0_0_gpio52 {
645 pin-pwm {
646 pins = "gpio52";
647 function = "alt1";
648 bias-disable;
649 };
650 };
651 pwm0_1_gpio53: pwm0_1_gpio53 {
652 pin-pwm {
653 pins = "gpio53";
654 function = "alt1";
655 bias-disable;
656 };
657 };
659 rgmii_gpio35: rgmii_gpio35 {
660 pin-start-stop {
661 pins = "gpio35";
662 function = "alt4";
663 };
664 pin-rx-ok {
665 pins = "gpio36";
666 function = "alt4";
667 };
668 };
669 rgmii_irq_gpio34: rgmii_irq_gpio34 {
670 pin-irq {
671 pins = "gpio34";
672 function = "alt5";
673 };
674 };
675 rgmii_irq_gpio39: rgmii_irq_gpio39 {
676 pin-irq {
677 pins = "gpio39";
678 function = "alt4";
679 };
680 };
681 rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
682 pins-mdio {
683 pins = "gpio28",
684 "gpio29";
685 function = "alt5";
686 };
687 };
688 rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
689 pins-mdio {
690 pins = "gpio37",
691 "gpio38";
692 function = "alt4";
693 };
694 };
696 spi0_gpio46: spi0_gpio46 {
697 pins-spi {
698 pins = "gpio46",
699 "gpio47",
700 "gpio48",
701 "gpio49";
702 function = "alt2";
703 };
704 };
705 spi2_gpio46: spi2_gpio46 {
706 pins-spi {
707 pins = "gpio46",
708 "gpio47",
709 "gpio48",
710 "gpio49",
711 "gpio50";
712 function = "alt5";
713 };
714 };
715 spi3_gpio0: spi3_gpio0 {
716 pins-spi {
717 pins = "gpio0",
718 "gpio1",
719 "gpio2",
720 "gpio3";
721 function = "alt3";
722 };
723 };
724 spi4_gpio4: spi4_gpio4 {
725 pins-spi {
726 pins = "gpio4",
727 "gpio5",
728 "gpio6",
729 "gpio7";
730 function = "alt3";
731 };
732 };
733 spi5_gpio12: spi5_gpio12 {
734 pins-spi {
735 pins = "gpio12",
736 "gpio13",
737 "gpio14",
738 "gpio15";
739 function = "alt3";
740 };
741 };
742 spi6_gpio18: spi6_gpio18 {
743 pins-spi {
744 pins = "gpio18",
745 "gpio19",
746 "gpio20",
747 "gpio21";
748 function = "alt3";
749 };
750 };
752 uart2_gpio0: uart2_gpio0 {
753 pin-tx {
754 pins = "gpio0";
755 function = "alt4";
756 bias-disable;
757 };
758 pin-rx {
759 pins = "gpio1";
760 function = "alt4";
761 bias-pull-up;
762 };
763 };
764 uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
765 pin-cts {
766 pins = "gpio2";
767 function = "alt4";
768 bias-pull-up;
769 };
770 pin-rts {
771 pins = "gpio3";
772 function = "alt4";
773 bias-disable;
774 };
775 };
776 uart3_gpio4: uart3_gpio4 {
777 pin-tx {
778 pins = "gpio4";
779 function = "alt4";
780 bias-disable;
781 };
782 pin-rx {
783 pins = "gpio5";
784 function = "alt4";
785 bias-pull-up;
786 };
787 };
788 uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
789 pin-cts {
790 pins = "gpio6";
791 function = "alt4";
792 bias-pull-up;
793 };
794 pin-rts {
795 pins = "gpio7";
796 function = "alt4";
797 bias-disable;
798 };
799 };
800 uart4_gpio8: uart4_gpio8 {
801 pin-tx {
802 pins = "gpio8";
803 function = "alt4";
804 bias-disable;
805 };
806 pin-rx {
807 pins = "gpio9";
808 function = "alt4";
809 bias-pull-up;
810 };
811 };
812 uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
813 pin-cts {
814 pins = "gpio10";
815 function = "alt4";
816 bias-pull-up;
817 };
818 pin-rts {
819 pins = "gpio11";
820 function = "alt4";
821 bias-disable;
822 };
823 };
824 uart5_gpio12: uart5_gpio12 {
825 pin-tx {
826 pins = "gpio12";
827 function = "alt4";
828 bias-disable;
829 };
830 pin-rx {
831 pins = "gpio13";
832 function = "alt4";
833 bias-pull-up;
834 };
835 };
836 uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
837 pin-cts {
838 pins = "gpio14";
839 function = "alt4";
840 bias-pull-up;
841 };
842 pin-rts {
843 pins = "gpio15";
844 function = "alt4";
845 bias-disable;
846 };
847 };
848 };
850 &rmem {
851 #address-cells = <2>;
852 };
854 &cma {
855 /*
856 * arm64 reserves the CMA by default somewhere in ZONE_DMA32,
857 * that's not good enough for the BCM2711 as some devices can
858 * only address the lower 1G of memory (ZONE_DMA).
859 */
860 alloc-ranges = <0x0 0x00000000 0x40000000>;
861 };
863 &i2c0 {
864 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
865 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
866 };
868 &i2c1 {
869 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
870 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
871 };
873 &mailbox {
874 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
875 };
877 &sdhci {
878 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
879 };
881 &sdhost {
882 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
883 };
885 &spi {
886 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
887 };
889 &spi1 {
890 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
891 };
893 &spi2 {
894 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
895 };
897 &system_timer {
898 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
899 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
900 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
901 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
902 };
904 &txp {
905 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
906 };
908 &uart0 {
909 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
910 };
912 &uart1 {
913 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
914 };
916 &usb {
917 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
918 };
920 &vec {
921 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
922 };