arch/arm/boot/dts/imx6dl.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright 2013 Freescale Semiconductor, Inc.
   4
   5 #include <dt-bindings/interrupt-controller/irq.h>
   6 #include "imx6dl-pinfunc.h"
   7 #include "imx6qdl.dtsi"
   8
   9 / {
  10         aliases {
  11                 i2c3 = &i2c4;
  12         };
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a9";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                         next-level-cache = <&L2>;
  23                         operating-points = <
  24                                 /* kHz    uV */
  25                                 996000  1250000
  26                                 792000  1175000
  27                                 396000  1150000
  28                         >;
  29                         fsl,soc-operating-points = <
  30                                 /* ARM kHz  SOC-PU uV */
  31                                 996000  1175000
  32                                 792000  1175000
  33                                 396000  1175000
  34                         >;
  35                         clock-latency = <61036>; /* two CLK32 periods */
  36                         #cooling-cells = <2>;
  37                         clocks = <&clks IMX6QDL_CLK_ARM>,
  38                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  39                                  <&clks IMX6QDL_CLK_STEP>,
  40                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  41                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  42                         clock-names = "arm", "pll2_pfd2_396m", "step",
  43                                       "pll1_sw", "pll1_sys";
  44                         arm-supply = <&reg_arm>;
  45                         pu-supply = <&reg_pu>;
  46                         soc-supply = <&reg_soc>;
  47                 };
  48
  49                 cpu@1 {
  50                         compatible = "arm,cortex-a9";
  51                         device_type = "cpu";
  52                         reg = <1>;
  53                         next-level-cache = <&L2>;
  54                         operating-points = <
  55                                 /* kHz    uV */
  56                                 996000  1250000
  57                                 792000  1175000
  58                                 396000  1150000
  59                         >;
  60                         fsl,soc-operating-points = <
  61                                 /* ARM kHz  SOC-PU uV */
  62                                 996000  1175000
  63                                 792000  1175000
  64                                 396000  1175000
  65                         >;
  66                         clock-latency = <61036>; /* two CLK32 periods */
  67                         #cooling-cells = <2>;
  68                         clocks = <&clks IMX6QDL_CLK_ARM>,
  69                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  70                                  <&clks IMX6QDL_CLK_STEP>,
  71                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  72                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  73                         clock-names = "arm", "pll2_pfd2_396m", "step",
  74                                       "pll1_sw", "pll1_sys";
  75                         arm-supply = <&reg_arm>;
  76                         pu-supply = <&reg_pu>;
  77                         soc-supply = <&reg_soc>;
  78                 };
  79         };
  80
  81         soc {
  82                 ocram: sram@900000 {
  83                         compatible = "mmio-sram";
  84                         reg = <0x00900000 0x20000>;
  85                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
  86                 };
  87
  88                 aips1: aips-bus@2000000 {
  89                         iomuxc: iomuxc@20e0000 {
  90                                 compatible = "fsl,imx6dl-iomuxc";
  91                         };
  92
  93                         pxp: pxp@20f0000 {
  94                                 reg = <0x020f0000 0x4000>;
  95                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
  96                         };
  97
  98                         epdc: epdc@20f4000 {
  99                                 reg = <0x020f4000 0x4000>;
 100                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 101                         };
 102                 };
 103
 104                 aips2: aips-bus@2100000 {
 105                         i2c4: i2c@21f8000 {
 106                                 #address-cells = <1>;
 107                                 #size-cells = <0>;
 108                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
 109                                 reg = <0x021f8000 0x4000>;
 110                                 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 111                                 clocks = <&clks IMX6DL_CLK_I2C4>;
 112                                 status = "disabled";
 113                         };
 114                 };
 115         };
 116
 117         capture-subsystem {
 118                 compatible = "fsl,imx-capture-subsystem";
 119                 ports = <&ipu1_csi0>, <&ipu1_csi1>;
 120         };
 121
 122         display-subsystem {
 123                 compatible = "fsl,imx-display-subsystem";
 124                 ports = <&ipu1_di0>, <&ipu1_di1>;
 125         };
 126 };
 127
 128 &gpio1 {
 129         gpio-ranges = <&iomuxc  0 131 2>, <&iomuxc  2 137 8>, <&iomuxc 10 189 2>,
 130                       <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
 131                       <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
 132                       <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
 133                       <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
 134                       <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
 135                       <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
 136 };
 137
 138 &gpio2 {
 139         gpio-ranges = <&iomuxc  0 161 8>, <&iomuxc  8 208 8>, <&iomuxc 16  74 1>,
 140                       <&iomuxc 17  73 1>, <&iomuxc 18  72 1>, <&iomuxc 19  71 1>,
 141                       <&iomuxc 20  70 1>, <&iomuxc 21  69 1>, <&iomuxc 22  68 1>,
 142                       <&iomuxc 23  79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
 143                       <&iomuxc 28 113 4>;
 144 };
 145
 146 &gpio3 {
 147         gpio-ranges = <&iomuxc  0 97  2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
 148                       <&iomuxc 16 81 16>;
 149 };
 150
 151 &gpio4 {
 152         gpio-ranges = <&iomuxc  5 136 1>, <&iomuxc  6 145 1>, <&iomuxc  7 150 1>,
 153                       <&iomuxc  8 146 1>, <&iomuxc  9 151 1>, <&iomuxc 10 147 1>,
 154                       <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
 155                       <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16  39 7>,
 156                       <&iomuxc 23  56 1>, <&iomuxc 24  61 7>, <&iomuxc 31  46 1>;
 157 };
 158
 159 &gpio5 {
 160         gpio-ranges = <&iomuxc  0 120 1>, <&iomuxc  2 77 1>, <&iomuxc  4 76 1>,
 161                       <&iomuxc  5  47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
 162                       <&iomuxc 19  36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
 163                       <&iomuxc 22  29 6>, <&iomuxc 28 19 4>;
 164 };
 165
 166 &gpio6 {
 167         gpio-ranges = <&iomuxc  0  23 6>, <&iomuxc  6  75 1>, <&iomuxc  7 156 1>,
 168                       <&iomuxc  8 155 1>, <&iomuxc  9 170 1>, <&iomuxc 10 169 1>,
 169                       <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
 170                       <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
 171                       <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
 172                       <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31  78 1>;
 173 };
 174
 175 &gpio7 {
 176         gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc  1 201 1>, <&iomuxc  2 196 1>,
 177                       <&iomuxc 3 195 1>, <&iomuxc  4 197 4>, <&iomuxc  8 205 1>,
 178                       <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
 179 };
 180
 181 &gpr {
 182         ipu1_csi0_mux {
 183                 compatible = "video-mux";
 184                 mux-controls = <&mux 0>;
 185                 #address-cells = <1>;
 186                 #size-cells = <0>;
 187
 188                 port@0 {
 189                         reg = <0>;
 190
 191                         ipu1_csi0_mux_from_mipi_vc0: endpoint {
 192                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
 193                         };
 194                 };
 195
 196                 port@1 {
 197                         reg = <1>;
 198
 199                         ipu1_csi0_mux_from_mipi_vc1: endpoint {
 200                                 remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
 201                         };
 202                 };
 203
 204                 port@2 {
 205                         reg = <2>;
 206
 207                         ipu1_csi0_mux_from_mipi_vc2: endpoint {
 208                                 remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
 209                         };
 210                 };
 211
 212                 port@3 {
 213                         reg = <3>;
 214
 215                         ipu1_csi0_mux_from_mipi_vc3: endpoint {
 216                                 remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
 217                         };
 218                 };
 219
 220                 port@4 {
 221                         reg = <4>;
 222
 223                         ipu1_csi0_mux_from_parallel_sensor: endpoint {
 224                         };
 225                 };
 226
 227                 port@5 {
 228                         reg = <5>;
 229
 230                         ipu1_csi0_mux_to_ipu1_csi0: endpoint {
 231                                 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
 232                         };
 233                 };
 234         };
 235
 236         ipu1_csi1_mux {
 237                 compatible = "video-mux";
 238                 mux-controls = <&mux 1>;
 239                 #address-cells = <1>;
 240                 #size-cells = <0>;
 241
 242                 port@0 {
 243                         reg = <0>;
 244
 245                         ipu1_csi1_mux_from_mipi_vc0: endpoint {
 246                                 remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
 247                         };
 248                 };
 249
 250                 port@1 {
 251                         reg = <1>;
 252
 253                         ipu1_csi1_mux_from_mipi_vc1: endpoint {
 254                                 remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
 255                         };
 256                 };
 257
 258                 port@2 {
 259                         reg = <2>;
 260
 261                         ipu1_csi1_mux_from_mipi_vc2: endpoint {
 262                                 remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
 263                         };
 264                 };
 265
 266                 port@3 {
 267                         reg = <3>;
 268
 269                         ipu1_csi1_mux_from_mipi_vc3: endpoint {
 270                                 remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
 271                         };
 272                 };
 273
 274                 port@4 {
 275                         reg = <4>;
 276
 277                         ipu1_csi1_mux_from_parallel_sensor: endpoint {
 278                         };
 279                 };
 280
 281                 port@5 {
 282                         reg = <5>;
 283
 284                         ipu1_csi1_mux_to_ipu1_csi1: endpoint {
 285                                 remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
 286                         };
 287                 };
 288         };
 289 };
 290
 291 &gpt {
 292         compatible = "fsl,imx6dl-gpt";
 293 };
 294
 295 &hdmi {
 296         compatible = "fsl,imx6dl-hdmi";
 297 };
 298
 299 &ipu1_csi1 {
 300         ipu1_csi1_from_ipu1_csi1_mux: endpoint {
 301                 remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
 302         };
 303 };
 304
 305 &ldb {
 306         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 307                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 308                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 309         clock-names = "di0_pll", "di1_pll",
 310                       "di0_sel", "di1_sel",
 311                       "di0", "di1";
 312 };
 313
 314 &mipi_csi {
 315         port@1 {
 316                 reg = <1>;
 317                 #address-cells = <1>;
 318                 #size-cells = <0>;
 319
 320                 mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
 321                         reg = <0>;
 322                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
 323                 };
 324
 325                 mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
 326                         reg = <1>;
 327                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
 328                 };
 329         };
 330
 331         port@2 {
 332                 reg = <2>;
 333                 #address-cells = <1>;
 334                 #size-cells = <0>;
 335
 336                 mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
 337                         reg = <0>;
 338                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
 339                 };
 340
 341                 mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
 342                         reg = <1>;
 343                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
 344                 };
 345         };
 346
 347         port@3 {
 348                 reg = <3>;
 349                 #address-cells = <1>;
 350                 #size-cells = <0>;
 351
 352                 mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
 353                         reg = <0>;
 354                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
 355                 };
 356
 357                 mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
 358                         reg = <1>;
 359                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
 360                 };
 361         };
 362
 363         port@4 {
 364                 reg = <4>;
 365                 #address-cells = <1>;
 366                 #size-cells = <0>;
 367
 368                 mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
 369                         reg = <0>;
 370                         remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
 371                 };
 372
 373                 mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
 374                         reg = <1>;
 375                         remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
 376                 };
 377         };
 378 };
 379
 380 &mux {
 381         mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
 382                         <0x34 0x00000038>, /* IPU_CSI1_MUX */
 383                         <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
 384                         <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
 385                         <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
 386                         <0x28 0x00000003>, /* DCIC1_MUX_CTL */
 387                         <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
 388 };
 389
 390 &vpu {
 391         compatible = "fsl,imx6dl-vpu", "cnm,coda960";
 392 };