arch/arm/boot/dts/imx6qdl-apf6.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Copyright 2015 Armadeus Systems <support@armadeus.com>
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/interrupt-controller/irq.h>
   7
   8 / {
   9         reg_1p8v: regulator-1p8v {
  10                 compatible = "regulator-fixed";
  11                 regulator-name = "1P8V";
  12                 regulator-min-microvolt = <1800000>;
  13                 regulator-max-microvolt = <1800000>;
  14                 regulator-always-on;
  15                 vin-supply = <&reg_3p3v>;
  16         };
  17
  18         usdhc1_pwrseq: usdhc1-pwrseq {
  19                 compatible = "mmc-pwrseq-simple";
  20                 reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
  21                 post-power-on-delay-ms = <15>;
  22                 power-off-delay-us = <70>;
  23         };
  24 };
  25
  26 &fec {
  27         pinctrl-names = "default";
  28         pinctrl-0 = <&pinctrl_enet>;
  29         phy-mode = "rgmii-id";
  30         phy-reset-duration = <10>;
  31         phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
  32         phy-handle = <&ethphy1>;
  33         status = "okay";
  34
  35         mdio {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 ethphy1: ethernet-phy@1 {
  40                         compatible = "ethernet-phy-ieee802.3-c22";
  41                         reg = <1>;
  42                         interrupt-parent = <&gpio1>;
  43                         interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
  44                         status = "okay";
  45                 };
  46         };
  47 };
  48
  49 /* Bluetooth */
  50 &uart2 {
  51         pinctrl-names = "default";
  52         pinctrl-0 = <&pinctrl_uart2>;
  53         uart-has-rtscts;
  54         status = "okay";
  55 };
  56
  57 /* Wi-Fi */
  58 &usdhc1 {
  59         pinctrl-names = "default";
  60         pinctrl-0 = <&pinctrl_usdhc1>;
  61         bus-width = <4>;
  62         mmc-pwrseq = <&usdhc1_pwrseq>;
  63         vmmc-supply = <&reg_3p3v>;
  64         vqmmc-supply = <&reg_1p8v>;
  65         cap-power-off-card;
  66         keep-power-in-suspend;
  67         non-removable;
  68         status = "okay";
  69
  70         #address-cells = <1>;
  71         #size-cells = <0>;
  72         wlcore: wlcore@2 {
  73                 compatible = "ti,wl1271";
  74                 reg = <2>;
  75                 interrupt-parent = <&gpio2>;
  76                 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
  77                 ref-clock-frequency = <38400000>;
  78                 tcxo-clock-frequency = <38400000>;
  79         };
  80 };
  81
  82 /* eMMC */
  83 &usdhc3 {
  84         pinctrl-names = "default";
  85         pinctrl-0 = <&pinctrl_usdhc3>;
  86         bus-width = <8>;
  87         no-1-8-v;
  88         non-removable;
  89         status = "okay";
  90 };
  91
  92 &iomuxc {
  93         pinctrl_enet: enetgrp {
  94                 fsl,pins = <
  95                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b8b0
  96                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
  97                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
  98                         MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24       0x130b0
  99                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x130b0
 100                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 101                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 102                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 103                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 104                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 105                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 106                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x13030
 107                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 108                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x13030
 109                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1f030
 110                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1f030
 111                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x13030
 112                 >;
 113         };
 114
 115         pinctrl_uart2: uart2grp {
 116                 fsl,pins = <
 117                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b0
 118                         MX6QDL_PAD_SD4_DAT5__UART2_RTS_B        0x1b0b0
 119                         MX6QDL_PAD_SD4_DAT6__UART2_CTS_B        0x1b0b0
 120                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b0
 121                         MX6QDL_PAD_SD4_DAT3__GPIO2_IO11         0x130b0 /* BT_EN */
 122                 >;
 123         };
 124
 125         pinctrl_usdhc1: usdhc1grp {
 126                 fsl,pins = <
 127                         MX6QDL_PAD_SD1_CMD__SD1_CMD     0x17059
 128                         MX6QDL_PAD_SD1_CLK__SD1_CLK     0x10059
 129                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0  0x17059
 130                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1  0x17059
 131                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2  0x17059
 132                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3  0x17059
 133                         MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x130b0 /* WL_EN */
 134                         MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x130b0 /* WL_IRQ */
 135                 >;
 136         };
 137
 138         pinctrl_usdhc3: usdhc3grp {
 139                 fsl,pins = <
 140                         MX6QDL_PAD_SD3_CMD__SD3_CMD     0x17059
 141                         MX6QDL_PAD_SD3_CLK__SD3_CLK     0x10059
 142                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x17059
 143                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x17059
 144                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x17059
 145                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x17059
 146                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4  0x17059
 147                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5  0x17059
 148                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6  0x17059
 149                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7  0x17059
 150                 >;
 151         };
 152 };