arch/arm/boot/dts/imx6qdl-gw5904.dtsi

   1 /*
   2  * Copyright 2017 Gateworks Corporation
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/gpio/gpio.h>
  49
  50 / {
  51         /* these are used by bootloader for disabling nodes */
  52         aliases {
  53                 led0 = &led0;
  54                 led1 = &led1;
  55                 led2 = &led2;
  56                 usb0 = &usbh1;
  57                 usb1 = &usbotg;
  58         };
  59
  60         chosen {
  61                 stdout-path = &uart2;
  62         };
  63
  64         backlight {
  65                 compatible = "pwm-backlight";
  66                 pwms = <&pwm4 0 5000000>;
  67                 brightness-levels = <0 4 8 16 32 64 128 255>;
  68                 default-brightness-level = <7>;
  69         };
  70
  71         leds {
  72                 compatible = "gpio-leds";
  73                 pinctrl-names = "default";
  74                 pinctrl-0 = <&pinctrl_gpio_leds>;
  75
  76                 led0: user1 {
  77                         label = "user1";
  78                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  79                         default-state = "on";
  80                         linux,default-trigger = "heartbeat";
  81                 };
  82
  83                 led1: user2 {
  84                         label = "user2";
  85                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  86                         default-state = "off";
  87                 };
  88
  89                 led2: user3 {
  90                         label = "user3";
  91                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  92                         default-state = "off";
  93                 };
  94         };
  95
  96         memory@10000000 {
  97                 device_type = "memory";
  98                 reg = <0x10000000 0x40000000>;
  99         };
 100
 101         pps {
 102                 compatible = "pps-gpio";
 103                 pinctrl-names = "default";
 104                 pinctrl-0 = <&pinctrl_pps>;
 105                 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 106         };
 107
 108         reg_1p0v: regulator-1p0v {
 109                 compatible = "regulator-fixed";
 110                 regulator-name = "1P0V";
 111                 regulator-min-microvolt = <1000000>;
 112                 regulator-max-microvolt = <1000000>;
 113                 regulator-always-on;
 114         };
 115
 116         reg_3p3v: regulator-3p3v {
 117                 compatible = "regulator-fixed";
 118                 regulator-name = "3P3V";
 119                 regulator-min-microvolt = <3300000>;
 120                 regulator-max-microvolt = <3300000>;
 121                 regulator-always-on;
 122         };
 123
 124         reg_usb_h1_vbus: regulator-usb-h1-vbus {
 125                 compatible = "regulator-fixed";
 126                 regulator-name = "usb_h1_vbus";
 127                 regulator-min-microvolt = <5000000>;
 128                 regulator-max-microvolt = <5000000>;
 129                 regulator-always-on;
 130         };
 131
 132         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 133                 compatible = "regulator-fixed";
 134                 regulator-name = "usb_otg_vbus";
 135                 regulator-min-microvolt = <5000000>;
 136                 regulator-max-microvolt = <5000000>;
 137                 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 138                 enable-active-high;
 139         };
 140 };
 141
 142 &clks {
 143         assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 144                           <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
 145         assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
 146                                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 147 };
 148
 149 &fec {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&pinctrl_enet>;
 152         phy-mode = "rgmii-id";
 153         status = "okay";
 154
 155         fixed-link {
 156                 speed = <1000>;
 157                 full-duplex;
 158         };
 159
 160         mdio {
 161                 #address-cells = <1>;
 162                 #size-cells = <0>;
 163
 164                 switch@0 {
 165                         compatible = "marvell,mv88e6085";
 166                         reg = <0>;
 167
 168                         ports {
 169                                 #address-cells = <1>;
 170                                 #size-cells = <0>;
 171
 172                                 port@0 {
 173                                         reg = <0>;
 174                                         label = "lan4";
 175                                 };
 176
 177                                 port@1 {
 178                                         reg = <1>;
 179                                         label = "lan3";
 180                                 };
 181
 182                                 port@2 {
 183                                         reg = <2>;
 184                                         label = "lan2";
 185                                 };
 186
 187                                 port@3 {
 188                                         reg = <3>;
 189                                         label = "lan1";
 190                                 };
 191
 192                                 port@5 {
 193                                         reg = <5>;
 194                                         label = "cpu";
 195                                         ethernet = <&fec>;
 196                                 };
 197                         };
 198                 };
 199         };
 200 };
 201
 202 &i2c1 {
 203         clock-frequency = <100000>;
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&pinctrl_i2c1>;
 206         status = "okay";
 207
 208         pca9555: gpio@23 {
 209                 compatible = "nxp,pca9555";
 210                 reg = <0x23>;
 211                 gpio-controller;
 212                 #gpio-cells = <2>;
 213         };
 214
 215         eeprom1: eeprom@50 {
 216                 compatible = "atmel,24c02";
 217                 reg = <0x50>;
 218                 pagesize = <16>;
 219         };
 220
 221         eeprom2: eeprom@51 {
 222                 compatible = "atmel,24c02";
 223                 reg = <0x51>;
 224                 pagesize = <16>;
 225         };
 226
 227         eeprom3: eeprom@52 {
 228                 compatible = "atmel,24c02";
 229                 reg = <0x52>;
 230                 pagesize = <16>;
 231         };
 232
 233         eeprom4: eeprom@53 {
 234                 compatible = "atmel,24c02";
 235                 reg = <0x53>;
 236                 pagesize = <16>;
 237         };
 238
 239         dts1672: rtc@68 {
 240                 compatible = "dallas,ds1672";
 241                 reg = <0x68>;
 242         };
 243 };
 244
 245 &i2c2 {
 246         clock-frequency = <100000>;
 247         pinctrl-names = "default";
 248         pinctrl-0 = <&pinctrl_i2c2>;
 249         status = "okay";
 250
 251         ltc3676: pmic@3c {
 252                 compatible = "lltc,ltc3676";
 253                 reg = <0x3c>;
 254                 interrupt-parent = <&gpio1>;
 255                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 256
 257                 regulators {
 258                         /* VDD_SOC (1+R1/R2 = 1.635) */
 259                         reg_vdd_soc: sw1 {
 260                                 regulator-name = "vddsoc";
 261                                 regulator-min-microvolt = <674400>;
 262                                 regulator-max-microvolt = <1308000>;
 263                                 lltc,fb-voltage-divider = <127000 200000>;
 264                                 regulator-ramp-delay = <7000>;
 265                                 regulator-boot-on;
 266                                 regulator-always-on;
 267                         };
 268
 269                         /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */
 270                         reg_1p8v: sw2 {
 271                                 regulator-name = "vdd1p8";
 272                                 regulator-min-microvolt = <1033310>;
 273                                 regulator-max-microvolt = <2004000>;
 274                                 lltc,fb-voltage-divider = <301000 200000>;
 275                                 regulator-ramp-delay = <7000>;
 276                                 regulator-boot-on;
 277                                 regulator-always-on;
 278                         };
 279
 280                         /* VDD_ARM (1+R1/R2 = 1.635) */
 281                         reg_vdd_arm: sw3 {
 282                                 regulator-name = "vddarm";
 283                                 regulator-min-microvolt = <674400>;
 284                                 regulator-max-microvolt = <1308000>;
 285                                 lltc,fb-voltage-divider = <127000 200000>;
 286                                 regulator-ramp-delay = <7000>;
 287                                 regulator-boot-on;
 288                                 regulator-always-on;
 289                         };
 290
 291                         /* VDD_DDR (1+R1/R2 = 2.105) */
 292                         reg_vdd_ddr: sw4 {
 293                                 regulator-name = "vddddr";
 294                                 regulator-min-microvolt = <868310>;
 295                                 regulator-max-microvolt = <1684000>;
 296                                 lltc,fb-voltage-divider = <221000 200000>;
 297                                 regulator-ramp-delay = <7000>;
 298                                 regulator-boot-on;
 299                                 regulator-always-on;
 300                         };
 301
 302                         /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
 303                         reg_2p5v: ldo2 {
 304                                 regulator-name = "vdd2p5";
 305                                 regulator-min-microvolt = <2490375>;
 306                                 regulator-max-microvolt = <2490375>;
 307                                 lltc,fb-voltage-divider = <487000 200000>;
 308                                 regulator-boot-on;
 309                                 regulator-always-on;
 310                         };
 311
 312                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 313                         reg_3p0v: ldo4 {
 314                                 regulator-name = "vdd3p0";
 315                                 regulator-min-microvolt = <3023250>;
 316                                 regulator-max-microvolt = <3023250>;
 317                                 lltc,fb-voltage-divider = <634000 200000>;
 318                                 regulator-boot-on;
 319                                 regulator-always-on;
 320                         };
 321                 };
 322         };
 323 };
 324
 325 &i2c3 {
 326         clock-frequency = <100000>;
 327         pinctrl-names = "default";
 328         pinctrl-0 = <&pinctrl_i2c3>;
 329         status = "okay";
 330
 331         egalax_ts: touchscreen@4 {
 332                 compatible = "eeti,egalax_ts";
 333                 reg = <0x04>;
 334                 interrupt-parent = <&gpio1>;
 335                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 336                 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
 337         };
 338 };
 339
 340 &ldb {
 341         status = "okay";
 342
 343         lvds-channel@0 {
 344                 fsl,data-mapping = "spwg";
 345                 fsl,data-width = <18>;
 346                 status = "okay";
 347
 348                 display-timings {
 349                         native-mode = <&timing0>;
 350                         timing0: hsd100pxn1 {
 351                                 clock-frequency = <65000000>;
 352                                 hactive = <1024>;
 353                                 vactive = <768>;
 354                                 hback-porch = <220>;
 355                                 hfront-porch = <40>;
 356                                 vback-porch = <21>;
 357                                 vfront-porch = <7>;
 358                                 hsync-len = <60>;
 359                                 vsync-len = <10>;
 360                         };
 361                 };
 362         };
 363 };
 364
 365 &pcie {
 366         pinctrl-names = "default";
 367         pinctrl-0 = <&pinctrl_pcie>;
 368         reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 369         status = "okay";
 370 };
 371
 372 &pwm2 {
 373         pinctrl-names = "default";
 374         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 375         status = "disabled";
 376 };
 377
 378 &pwm3 {
 379         pinctrl-names = "default";
 380         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 381         status = "disabled";
 382 };
 383
 384 &pwm4 {
 385         pinctrl-names = "default";
 386         pinctrl-0 = <&pinctrl_pwm4>;
 387         status = "okay";
 388 };
 389
 390 &uart1 {
 391         pinctrl-names = "default";
 392         pinctrl-0 = <&pinctrl_uart1>;
 393         status = "okay";
 394 };
 395
 396 &uart2 {
 397         pinctrl-names = "default";
 398         pinctrl-0 = <&pinctrl_uart2>;
 399         status = "okay";
 400 };
 401
 402 &uart3 {
 403         pinctrl-names = "default";
 404         pinctrl-0 = <&pinctrl_uart3>;
 405         uart-has-rtscts;
 406         status = "okay";
 407 };
 408
 409 &uart4 {
 410         pinctrl-names = "default";
 411         pinctrl-0 = <&pinctrl_uart4>;
 412         uart-has-rtscts;
 413         status = "okay";
 414 };
 415
 416 &uart5 {
 417         pinctrl-names = "default";
 418         pinctrl-0 = <&pinctrl_uart5>;
 419         status = "okay";
 420 };
 421
 422 &usbotg {
 423         vbus-supply = <&reg_usb_otg_vbus>;
 424         pinctrl-names = "default";
 425         pinctrl-0 = <&pinctrl_usbotg>;
 426         disable-over-current;
 427         status = "okay";
 428 };
 429
 430 &usbh1 {
 431         vbus-supply = <&reg_usb_h1_vbus>;
 432         status = "okay";
 433 };
 434
 435 &usdhc3 {
 436         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 437         pinctrl-0 = <&pinctrl_usdhc3>;
 438         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 439         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 440         non-removable;
 441         vmmc-supply = <&reg_3p3v>;
 442         keep-power-in-suspend;
 443         status = "okay";
 444 };
 445
 446 &wdog1 {
 447         pinctrl-names = "default";
 448         pinctrl-0 = <&pinctrl_wdog>;
 449         fsl,ext-reset-output;
 450 };
 451
 452 &iomuxc {
 453         pinctrl_enet: enetgrp {
 454                 fsl,pins = <
 455                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 456                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 457                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 458                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 459                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 460                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 461                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 462                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 463                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 464                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 465                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 466                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 467                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 468                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 469                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 470                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 471                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x4001b0b0 /* PHY_RST# */
 472                 >;
 473         };
 474
 475         pinctrl_gpio_leds: gpioledsgrp {
 476                 fsl,pins = <
 477                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 478                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 479                         MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 480                 >;
 481         };
 482
 483         pinctrl_i2c1: i2c1grp {
 484                 fsl,pins = <
 485                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 486                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 487                 >;
 488         };
 489
 490         pinctrl_i2c2: i2c2grp {
 491                 fsl,pins = <
 492                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 493                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 494                 >;
 495         };
 496
 497         pinctrl_i2c3: i2c3grp {
 498                 fsl,pins = <
 499                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 500                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 501                 >;
 502         };
 503
 504         pinctrl_pcie: pciegrp {
 505                 fsl,pins = <
 506                         MX6QDL_PAD_GPIO_0__GPIO1_IO00   0x1b0b0 /* PCIE RST */
 507                 >;
 508         };
 509
 510         pinctrl_pmic: pmicgrp {
 511                 fsl,pins = <
 512                         MX6QDL_PAD_GPIO_8__GPIO1_IO08   0x1b0b0 /* PMIC_IRQ# */
 513                 >;
 514         };
 515
 516         pinctrl_pps: ppsgrp {
 517                 fsl,pins = <
 518                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 519                 >;
 520         };
 521
 522         pinctrl_pwm2: pwm2grp {
 523                 fsl,pins = <
 524                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 525                 >;
 526         };
 527
 528         pinctrl_pwm3: pwm3grp {
 529                 fsl,pins = <
 530                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 531                 >;
 532         };
 533
 534         pinctrl_pwm4: pwm4grp {
 535                 fsl,pins = <
 536                         MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 537                 >;
 538         };
 539
 540         pinctrl_uart1: uart1grp {
 541                 fsl,pins = <
 542                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
 543                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
 544                 >;
 545         };
 546
 547         pinctrl_uart2: uart2grp {
 548                 fsl,pins = <
 549                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 550                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 551                 >;
 552         };
 553
 554         pinctrl_uart3: uart3grp {
 555                 fsl,pins = <
 556                         MX6QDL_PAD_EIM_D23__UART3_CTS_B         0x1b0b1
 557                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 558                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 559                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
 560                 >;
 561         };
 562
 563         pinctrl_uart4: uart4grp {
 564                 fsl,pins = <
 565                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
 566                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
 567                         MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B      0x1b0b1
 568                         MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B      0x1b0b1
 569                 >;
 570         };
 571
 572         pinctrl_uart5: uart5grp {
 573                 fsl,pins = <
 574                         MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 575                         MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 576                 >;
 577         };
 578
 579         pinctrl_usbotg: usbotggrp {
 580                 fsl,pins = <
 581                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 582                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0 /* PWR_EN */
 583                         MX6QDL_PAD_KEY_COL4__GPIO4_IO14         0x1b0b0 /* OC */
 584                 >;
 585         };
 586
 587         pinctrl_usdhc3: usdhc3grp {
 588                 fsl,pins = <
 589                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 590                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 591                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x10059
 592                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 593                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 594                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 595                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 596                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x17059
 597                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x17059
 598                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x17059
 599                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
 600                 >;
 601         };
 602
 603         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 604                 fsl,pins = <
 605                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170b9
 606                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100b9
 607                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x100b9
 608                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170b9
 609                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170b9
 610                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170b9
 611                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170b9
 612                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170b9
 613                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170b9
 614                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170b9
 615                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170b9
 616                 >;
 617         };
 618
 619         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 620                 fsl,pins = <
 621                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x170f9
 622                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x100f9
 623                         MX6QDL_PAD_SD3_RST__SD3_RESET           0x100f9
 624                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x170f9
 625                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x170f9
 626                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x170f9
 627                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x170f9
 628                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x170f9
 629                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x170f9
 630                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x170f9
 631                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x170f9
 632                 >;
 633         };
 634
 635         pinctrl_wdog: wdoggrp {
 636                 fsl,pins = <
 637                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 638                 >;
 639         };
 640 };