| blob | ab91c98f21241127736dada1205d2b57ea7eef59 |
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP
5 * Dong Aisheng <aisheng.dong@nxp.com>
6 */
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
14 / {
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
20 aliases {
21 gpio0 = &gpio_ptc;
22 gpio1 = &gpio_ptd;
23 gpio2 = &gpio_pte;
24 gpio3 = &gpio_ptf;
25 i2c0 = &lpi2c6;
26 i2c1 = &lpi2c7;
27 mmc0 = &usdhc0;
28 mmc1 = &usdhc1;
29 serial0 = &lpuart4;
30 serial1 = &lpuart5;
31 serial2 = &lpuart6;
32 serial3 = &lpuart7;
33 usbphy0 = &usbphy1;
34 };
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
40 cpu0: cpu@f00 {
41 compatible = "arm,cortex-a7";
42 device_type = "cpu";
43 reg = <0xf00>;
44 };
45 };
47 intc: interrupt-controller@40021000 {
48 compatible = "arm,cortex-a7-gic";
49 #interrupt-cells = <3>;
50 interrupt-controller;
51 reg = <0x40021000 0x1000>,
52 <0x40022000 0x1000>;
53 };
55 rosc: clock-rosc {
56 compatible = "fixed-clock";
57 clock-frequency = <32768>;
58 clock-output-names = "rosc";
59 #clock-cells = <0>;
60 };
62 sosc: clock-sosc {
63 compatible = "fixed-clock";
64 clock-frequency = <24000000>;
65 clock-output-names = "sosc";
66 #clock-cells = <0>;
67 };
69 sirc: clock-sirc {
70 compatible = "fixed-clock";
71 clock-frequency = <16000000>;
72 clock-output-names = "sirc";
73 #clock-cells = <0>;
74 };
76 firc: clock-firc {
77 compatible = "fixed-clock";
78 clock-frequency = <48000000>;
79 clock-output-names = "firc";
80 #clock-cells = <0>;
81 };
83 upll: clock-upll {
84 compatible = "fixed-clock";
85 clock-frequency = <480000000>;
86 clock-output-names = "upll";
87 #clock-cells = <0>;
88 };
90 ahbbridge0: bus@40000000 {
91 compatible = "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <1>;
94 reg = <0x40000000 0x800000>;
95 ranges;
97 edma1: dma-controller@40080000 {
98 #dma-cells = <2>;
99 compatible = "fsl,imx7ulp-edma";
100 reg = <0x40080000 0x2000>,
101 <0x40210000 0x1000>;
102 dma-channels = <32>;
103 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
113 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
120 clock-names = "dma", "dmamux0";
121 clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
122 <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
123 };
125 crypto: crypto@40240000 {
126 compatible = "fsl,sec-v4.0";
127 #address-cells = <1>;
128 #size-cells = <1>;
129 reg = <0x40240000 0x10000>;
130 ranges = <0 0x40240000 0x10000>;
131 clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
132 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
133 clock-names = "aclk", "ipg";
135 sec_jr0: jr0@1000 {
136 compatible = "fsl,sec-v4.0-job-ring";
137 reg = <0x1000 0x1000>;
138 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
139 };
141 sec_jr1: jr1@2000 {
142 compatible = "fsl,sec-v4.0-job-ring";
143 reg = <0x2000 0x1000>;
144 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
145 };
146 };
148 lpuart4: serial@402d0000 {
149 compatible = "fsl,imx7ulp-lpuart";
150 reg = <0x402d0000 0x1000>;
151 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
153 clock-names = "ipg";
154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 assigned-clock-rates = <24000000>;
157 status = "disabled";
158 };
160 lpuart5: serial@402e0000 {
161 compatible = "fsl,imx7ulp-lpuart";
162 reg = <0x402e0000 0x1000>;
163 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
165 clock-names = "ipg";
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 assigned-clock-rates = <48000000>;
169 status = "disabled";
170 };
172 tpm4: pwm@40250000 {
173 compatible = "fsl,imx7ulp-pwm";
174 reg = <0x40250000 0x1000>;
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
177 clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
178 #pwm-cells = <3>;
179 status = "disabled";
180 };
182 tpm5: tpm@40260000 {
183 compatible = "fsl,imx7ulp-tpm";
184 reg = <0x40260000 0x1000>;
185 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
187 <&pcc2 IMX7ULP_CLK_LPTPM5>;
188 clock-names = "ipg", "per";
189 };
191 usbotg1: usb@40330000 {
192 compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
193 reg = <0x40330000 0x200>;
194 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&pcc2 IMX7ULP_CLK_USB0>;
196 phys = <&usbphy1>;
197 fsl,usbmisc = <&usbmisc1 0>;
198 ahb-burst-config = <0x0>;
199 tx-burst-size-dword = <0x8>;
200 rx-burst-size-dword = <0x8>;
201 status = "disabled";
202 };
204 usbmisc1: usbmisc@40330200 {
205 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
206 #index-cells = <1>;
207 reg = <0x40330200 0x200>;
208 };
210 usbphy1: usb-phy@40350000 {
211 compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
212 reg = <0x40350000 0x1000>;
213 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;
215 #phy-cells = <0>;
216 };
218 usdhc0: mmc@40370000 {
219 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
220 reg = <0x40370000 0x10000>;
221 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
223 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
224 <&pcc2 IMX7ULP_CLK_USDHC0>;
225 clock-names = "ipg", "ahb", "per";
226 bus-width = <4>;
227 fsl,tuning-start-tap = <20>;
228 fsl,tuning-step = <2>;
229 status = "disabled";
230 };
232 usdhc1: mmc@40380000 {
233 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
234 reg = <0x40380000 0x10000>;
235 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
237 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
238 <&pcc2 IMX7ULP_CLK_USDHC1>;
239 clock-names = "ipg", "ahb", "per";
240 bus-width = <4>;
241 fsl,tuning-start-tap = <20>;
242 fsl,tuning-step = <2>;
243 status = "disabled";
244 };
246 scg1: clock-controller@403e0000 {
247 compatible = "fsl,imx7ulp-scg1";
248 reg = <0x403e0000 0x10000>;
249 clocks = <&rosc>, <&sosc>, <&sirc>,
250 <&firc>, <&upll>;
251 clock-names = "rosc", "sosc", "sirc",
252 "firc", "upll";
253 #clock-cells = <1>;
254 };
256 wdog1: watchdog@403d0000 {
257 compatible = "fsl,imx7ulp-wdt";
258 reg = <0x403d0000 0x10000>;
259 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
261 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
262 assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
263 timeout-sec = <40>;
264 };
266 pcc2: clock-controller@403f0000 {
267 compatible = "fsl,imx7ulp-pcc2";
268 reg = <0x403f0000 0x10000>;
269 #clock-cells = <1>;
270 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
271 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
272 <&scg1 IMX7ULP_CLK_DDR_DIV>,
273 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
274 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
275 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
276 <&scg1 IMX7ULP_CLK_UPLL>,
277 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
278 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
279 <&scg1 IMX7ULP_CLK_ROSC>,
280 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
281 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
282 "apll_pfd2", "apll_pfd1", "apll_pfd0",
283 "upll", "sosc_bus_clk",
284 "firc_bus_clk", "rosc", "spll_bus_clk";
285 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
286 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
287 };
289 smc1: clock-controller@40410000 {
290 compatible = "fsl,imx7ulp-smc1";
291 reg = <0x40410000 0x1000>;
292 #clock-cells = <1>;
293 clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
294 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
295 clock-names = "divcore", "hsrun_divcore";
296 };
298 pcc3: clock-controller@40b30000 {
299 compatible = "fsl,imx7ulp-pcc3";
300 reg = <0x40b30000 0x10000>;
301 #clock-cells = <1>;
302 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
303 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
304 <&scg1 IMX7ULP_CLK_DDR_DIV>,
305 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
306 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
307 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
308 <&scg1 IMX7ULP_CLK_UPLL>,
309 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
310 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
311 <&scg1 IMX7ULP_CLK_ROSC>,
312 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
313 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
314 "apll_pfd2", "apll_pfd1", "apll_pfd0",
315 "upll", "sosc_bus_clk",
316 "firc_bus_clk", "rosc", "spll_bus_clk";
317 };
318 };
320 ahbbridge1: bus@40800000 {
321 compatible = "simple-bus";
322 #address-cells = <1>;
323 #size-cells = <1>;
324 reg = <0x40800000 0x800000>;
325 ranges;
327 lpi2c6: i2c@40a40000 {
328 compatible = "fsl,imx7ulp-lpi2c";
329 reg = <0x40a40000 0x10000>;
330 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
332 clock-names = "ipg";
333 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
334 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
335 assigned-clock-rates = <48000000>;
336 status = "disabled";
337 };
339 lpi2c7: i2c@40a50000 {
340 compatible = "fsl,imx7ulp-lpi2c";
341 reg = <0x40a50000 0x10000>;
342 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
344 clock-names = "ipg";
345 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
346 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
347 assigned-clock-rates = <48000000>;
348 status = "disabled";
349 };
351 lpuart6: serial@40a60000 {
352 compatible = "fsl,imx7ulp-lpuart";
353 reg = <0x40a60000 0x1000>;
354 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
356 clock-names = "ipg";
357 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
358 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
359 assigned-clock-rates = <48000000>;
360 status = "disabled";
361 };
363 lpuart7: serial@40a70000 {
364 compatible = "fsl,imx7ulp-lpuart";
365 reg = <0x40a70000 0x1000>;
366 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
368 clock-names = "ipg";
369 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
370 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
371 assigned-clock-rates = <48000000>;
372 status = "disabled";
373 };
375 memory-controller@40ab0000 {
376 compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
377 reg = <0x40ab0000 0x1000>;
378 clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
379 };
381 iomuxc1: pinctrl@40ac0000 {
382 compatible = "fsl,imx7ulp-iomuxc1";
383 reg = <0x40ac0000 0x1000>;
384 };
386 gpio_ptc: gpio@40ae0000 {
387 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
388 reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
389 gpio-controller;
390 #gpio-cells = <2>;
391 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
395 <&pcc3 IMX7ULP_CLK_PCTLC>;
396 clock-names = "gpio", "port";
397 gpio-ranges = <&iomuxc1 0 0 32>;
398 };
400 gpio_ptd: gpio@40af0000 {
401 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
402 reg = <0x40af0000 0x1000 0x400f0040 0x40>;
403 gpio-controller;
404 #gpio-cells = <2>;
405 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
406 interrupt-controller;
407 #interrupt-cells = <2>;
408 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
409 <&pcc3 IMX7ULP_CLK_PCTLD>;
410 clock-names = "gpio", "port";
411 gpio-ranges = <&iomuxc1 0 32 32>;
412 };
414 gpio_pte: gpio@40b00000 {
415 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
416 reg = <0x40b00000 0x1000 0x400f0080 0x40>;
417 gpio-controller;
418 #gpio-cells = <2>;
419 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
420 interrupt-controller;
421 #interrupt-cells = <2>;
422 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
423 <&pcc3 IMX7ULP_CLK_PCTLE>;
424 clock-names = "gpio", "port";
425 gpio-ranges = <&iomuxc1 0 64 32>;
426 };
428 gpio_ptf: gpio@40b10000 {
429 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
430 reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
431 gpio-controller;
432 #gpio-cells = <2>;
433 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
434 interrupt-controller;
435 #interrupt-cells = <2>;
436 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
437 <&pcc3 IMX7ULP_CLK_PCTLF>;
438 clock-names = "gpio", "port";
439 gpio-ranges = <&iomuxc1 0 96 32>;
440 };
441 };
443 m4aips1: bus@41080000 {
444 compatible = "simple-bus";
445 #address-cells = <1>;
446 #size-cells = <1>;
447 reg = <0x41080000 0x80000>;
448 ranges;
450 sim: sim@410a3000 {
451 compatible = "fsl,imx7ulp-sim", "syscon";
452 reg = <0x410a3000 0x1000>;
453 };
455 ocotp: ocotp-ctrl@410a6000 {
456 compatible = "fsl,imx7ulp-ocotp", "syscon";
457 reg = <0x410a6000 0x4000>;
458 clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
459 };
460 };
461 };