| blob | 760a68c163c834213e396c55620152ce97967dd2 |
1 /*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/thermal/thermal.h>
51 / {
52 #address-cells = <2>;
53 #size-cells = <2>;
54 compatible = "fsl,ls1021a";
55 interrupt-parent = <&gic>;
57 aliases {
58 crypto = &crypto;
59 ethernet0 = &enet0;
60 ethernet1 = &enet1;
61 ethernet2 = &enet2;
62 serial0 = &lpuart0;
63 serial1 = &lpuart1;
64 serial2 = &lpuart2;
65 serial3 = &lpuart3;
66 serial4 = &lpuart4;
67 serial5 = &lpuart5;
68 sysclk = &sysclk;
69 };
71 cpus {
72 #address-cells = <1>;
73 #size-cells = <0>;
75 cpu0: cpu@f00 {
76 compatible = "arm,cortex-a7";
77 device_type = "cpu";
78 reg = <0xf00>;
79 clocks = <&clockgen 1 0>;
80 #cooling-cells = <2>;
81 };
83 cpu1: cpu@f01 {
84 compatible = "arm,cortex-a7";
85 device_type = "cpu";
86 reg = <0xf01>;
87 clocks = <&clockgen 1 0>;
88 #cooling-cells = <2>;
89 };
90 };
92 memory {
93 device_type = "memory";
94 reg = <0x0 0x0 0x0 0x0>;
95 };
97 sysclk: sysclk {
98 compatible = "fixed-clock";
99 #clock-cells = <0>;
100 clock-frequency = <100000000>;
101 clock-output-names = "sysclk";
102 };
104 timer {
105 compatible = "arm,armv7-timer";
106 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
107 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
108 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
109 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
110 };
112 pmu {
113 compatible = "arm,cortex-a7-pmu";
114 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
116 interrupt-affinity = <&cpu0>, <&cpu1>;
117 };
119 reboot {
120 compatible = "syscon-reboot";
121 regmap = <&dcfg>;
122 offset = <0xb0>;
123 mask = <0x02>;
124 };
126 soc {
127 compatible = "simple-bus";
128 #address-cells = <2>;
129 #size-cells = <2>;
130 device_type = "soc";
131 interrupt-parent = <&gic>;
132 ranges;
134 ddr: memory-controller@1080000 {
135 compatible = "fsl,qoriq-memory-controller";
136 reg = <0x0 0x1080000 0x0 0x1000>;
137 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
138 big-endian;
139 };
141 gic: interrupt-controller@1400000 {
142 compatible = "arm,gic-400", "arm,cortex-a7-gic";
143 #interrupt-cells = <3>;
144 interrupt-controller;
145 reg = <0x0 0x1401000 0x0 0x1000>,
146 <0x0 0x1402000 0x0 0x2000>,
147 <0x0 0x1404000 0x0 0x2000>,
148 <0x0 0x1406000 0x0 0x2000>;
149 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
151 };
153 msi1: msi-controller@1570e00 {
154 compatible = "fsl,ls1021a-msi";
155 reg = <0x0 0x1570e00 0x0 0x8>;
156 msi-controller;
157 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
158 };
160 msi2: msi-controller@1570e08 {
161 compatible = "fsl,ls1021a-msi";
162 reg = <0x0 0x1570e08 0x0 0x8>;
163 msi-controller;
164 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
165 };
167 ifc: ifc@1530000 {
168 compatible = "fsl,ifc", "simple-bus";
169 reg = <0x0 0x1530000 0x0 0x10000>;
170 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
171 };
173 dcfg: dcfg@1ee0000 {
174 compatible = "fsl,ls1021a-dcfg", "syscon";
175 reg = <0x0 0x1ee0000 0x0 0x10000>;
176 big-endian;
177 };
179 qspi: spi@1550000 {
180 compatible = "fsl,ls1021a-qspi";
181 #address-cells = <1>;
182 #size-cells = <0>;
183 reg = <0x0 0x1550000 0x0 0x10000>,
184 <0x0 0x40000000 0x0 0x40000000>;
185 reg-names = "QuadSPI", "QuadSPI-memory";
186 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
187 clock-names = "qspi_en", "qspi";
188 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
189 status = "disabled";
190 };
192 esdhc: esdhc@1560000 {
193 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
194 reg = <0x0 0x1560000 0x0 0x10000>;
195 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
196 clock-frequency = <0>;
197 voltage-ranges = <1800 1800 3300 3300>;
198 sdhci,auto-cmd12;
199 big-endian;
200 bus-width = <4>;
201 status = "disabled";
202 };
204 sata: sata@3200000 {
205 compatible = "fsl,ls1021a-ahci";
206 reg = <0x0 0x3200000 0x0 0x10000>,
207 <0x0 0x20220520 0x0 0x4>;
208 reg-names = "ahci", "sata-ecc";
209 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&clockgen 4 1>;
211 dma-coherent;
212 status = "disabled";
213 };
215 scfg: scfg@1570000 {
216 compatible = "fsl,ls1021a-scfg", "syscon";
217 reg = <0x0 0x1570000 0x0 0x10000>;
218 big-endian;
219 #address-cells = <1>;
220 #size-cells = <1>;
221 ranges = <0x0 0x0 0x1570000 0x10000>;
223 extirq: interrupt-controller@1ac {
224 compatible = "fsl,ls1021a-extirq";
225 #interrupt-cells = <2>;
226 #address-cells = <0>;
227 interrupt-controller;
228 reg = <0x1ac 4>;
229 interrupt-map =
230 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
231 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
232 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
233 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
234 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
235 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
236 interrupt-map-mask = <0xffffffff 0x0>;
237 };
238 };
240 crypto: crypto@1700000 {
241 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
242 fsl,sec-era = <7>;
243 #address-cells = <1>;
244 #size-cells = <1>;
245 reg = <0x0 0x1700000 0x0 0x100000>;
246 ranges = <0x0 0x0 0x1700000 0x100000>;
247 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
249 sec_jr0: jr@10000 {
250 compatible = "fsl,sec-v5.0-job-ring",
251 "fsl,sec-v4.0-job-ring";
252 reg = <0x10000 0x10000>;
253 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
254 };
256 sec_jr1: jr@20000 {
257 compatible = "fsl,sec-v5.0-job-ring",
258 "fsl,sec-v4.0-job-ring";
259 reg = <0x20000 0x10000>;
260 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
261 };
263 sec_jr2: jr@30000 {
264 compatible = "fsl,sec-v5.0-job-ring",
265 "fsl,sec-v4.0-job-ring";
266 reg = <0x30000 0x10000>;
267 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
268 };
270 sec_jr3: jr@40000 {
271 compatible = "fsl,sec-v5.0-job-ring",
272 "fsl,sec-v4.0-job-ring";
273 reg = <0x40000 0x10000>;
274 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
275 };
277 };
279 clockgen: clocking@1ee1000 {
280 compatible = "fsl,ls1021a-clockgen";
281 reg = <0x0 0x1ee1000 0x0 0x1000>;
282 #clock-cells = <2>;
283 clocks = <&sysclk>;
284 };
286 tmu: tmu@1f00000 {
287 compatible = "fsl,qoriq-tmu";
288 reg = <0x0 0x1f00000 0x0 0x10000>;
289 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
290 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
291 fsl,tmu-calibration = <0x00000000 0x0000000f
292 0x00000001 0x00000017
293 0x00000002 0x0000001e
294 0x00000003 0x00000026
295 0x00000004 0x0000002e
296 0x00000005 0x00000035
297 0x00000006 0x0000003d
298 0x00000007 0x00000044
299 0x00000008 0x0000004c
300 0x00000009 0x00000053
301 0x0000000a 0x0000005b
302 0x0000000b 0x00000064
304 0x00010000 0x00000011
305 0x00010001 0x0000001c
306 0x00010002 0x00000024
307 0x00010003 0x0000002b
308 0x00010004 0x00000034
309 0x00010005 0x00000039
310 0x00010006 0x00000042
311 0x00010007 0x0000004c
312 0x00010008 0x00000051
313 0x00010009 0x0000005a
314 0x0001000a 0x00000063
316 0x00020000 0x00000013
317 0x00020001 0x00000019
318 0x00020002 0x00000024
319 0x00020003 0x0000002c
320 0x00020004 0x00000035
321 0x00020005 0x0000003d
322 0x00020006 0x00000046
323 0x00020007 0x00000050
324 0x00020008 0x00000059
326 0x00030000 0x00000002
327 0x00030001 0x0000000d
328 0x00030002 0x00000019
329 0x00030003 0x00000024>;
330 #thermal-sensor-cells = <1>;
331 };
333 thermal-zones {
334 cpu_thermal: cpu-thermal {
335 polling-delay-passive = <1000>;
336 polling-delay = <5000>;
338 thermal-sensors = <&tmu 0>;
340 trips {
341 cpu_alert: cpu-alert {
342 temperature = <85000>;
343 hysteresis = <2000>;
344 type = "passive";
345 };
346 cpu_crit: cpu-crit {
347 temperature = <95000>;
348 hysteresis = <2000>;
349 type = "critical";
350 };
351 };
353 cooling-maps {
354 map0 {
355 trip = <&cpu_alert>;
356 cooling-device =
357 <&cpu0 THERMAL_NO_LIMIT
358 THERMAL_NO_LIMIT>,
359 <&cpu1 THERMAL_NO_LIMIT
360 THERMAL_NO_LIMIT>;
361 };
362 };
363 };
364 };
366 dspi0: spi@2100000 {
367 compatible = "fsl,ls1021a-v1.0-dspi";
368 #address-cells = <1>;
369 #size-cells = <0>;
370 reg = <0x0 0x2100000 0x0 0x10000>;
371 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
372 clock-names = "dspi";
373 clocks = <&clockgen 4 1>;
374 spi-num-chipselects = <6>;
375 big-endian;
376 status = "disabled";
377 };
379 dspi1: spi@2110000 {
380 compatible = "fsl,ls1021a-v1.0-dspi";
381 #address-cells = <1>;
382 #size-cells = <0>;
383 reg = <0x0 0x2110000 0x0 0x10000>;
384 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
385 clock-names = "dspi";
386 clocks = <&clockgen 4 1>;
387 spi-num-chipselects = <6>;
388 big-endian;
389 status = "disabled";
390 };
392 i2c0: i2c@2180000 {
393 compatible = "fsl,vf610-i2c";
394 #address-cells = <1>;
395 #size-cells = <0>;
396 reg = <0x0 0x2180000 0x0 0x10000>;
397 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
398 clock-names = "i2c";
399 clocks = <&clockgen 4 1>;
400 dma-names = "tx", "rx";
401 dmas = <&edma0 1 39>, <&edma0 1 38>;
402 status = "disabled";
403 };
405 i2c1: i2c@2190000 {
406 compatible = "fsl,vf610-i2c";
407 #address-cells = <1>;
408 #size-cells = <0>;
409 reg = <0x0 0x2190000 0x0 0x10000>;
410 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
411 clock-names = "i2c";
412 clocks = <&clockgen 4 1>;
413 dma-names = "tx", "rx";
414 dmas = <&edma0 1 37>, <&edma0 1 36>;
415 status = "disabled";
416 };
418 i2c2: i2c@21a0000 {
419 compatible = "fsl,vf610-i2c";
420 #address-cells = <1>;
421 #size-cells = <0>;
422 reg = <0x0 0x21a0000 0x0 0x10000>;
423 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
424 clock-names = "i2c";
425 clocks = <&clockgen 4 1>;
426 dma-names = "tx", "rx";
427 dmas = <&edma0 1 35>, <&edma0 1 34>;
428 status = "disabled";
429 };
431 uart0: serial@21c0500 {
432 compatible = "fsl,16550-FIFO64", "ns16550a";
433 reg = <0x0 0x21c0500 0x0 0x100>;
434 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
435 clock-frequency = <0>;
436 fifo-size = <15>;
437 status = "disabled";
438 };
440 uart1: serial@21c0600 {
441 compatible = "fsl,16550-FIFO64", "ns16550a";
442 reg = <0x0 0x21c0600 0x0 0x100>;
443 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
444 clock-frequency = <0>;
445 fifo-size = <15>;
446 status = "disabled";
447 };
449 uart2: serial@21d0500 {
450 compatible = "fsl,16550-FIFO64", "ns16550a";
451 reg = <0x0 0x21d0500 0x0 0x100>;
452 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
453 clock-frequency = <0>;
454 fifo-size = <15>;
455 status = "disabled";
456 };
458 uart3: serial@21d0600 {
459 compatible = "fsl,16550-FIFO64", "ns16550a";
460 reg = <0x0 0x21d0600 0x0 0x100>;
461 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
462 clock-frequency = <0>;
463 fifo-size = <15>;
464 status = "disabled";
465 };
467 counter0: counter@29d0000 {
468 compatible = "fsl,ftm-quaddec";
469 reg = <0x0 0x29d0000 0x0 0x10000>;
470 big-endian;
471 status = "disabled";
472 };
474 counter1: counter@29e0000 {
475 compatible = "fsl,ftm-quaddec";
476 reg = <0x0 0x29e0000 0x0 0x10000>;
477 big-endian;
478 status = "disabled";
479 };
481 counter2: counter@29f0000 {
482 compatible = "fsl,ftm-quaddec";
483 reg = <0x0 0x29f0000 0x0 0x10000>;
484 big-endian;
485 status = "disabled";
486 };
488 counter3: counter@2a00000 {
489 compatible = "fsl,ftm-quaddec";
490 reg = <0x0 0x2a00000 0x0 0x10000>;
491 big-endian;
492 status = "disabled";
493 };
495 gpio0: gpio@2300000 {
496 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
497 reg = <0x0 0x2300000 0x0 0x10000>;
498 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
499 gpio-controller;
500 #gpio-cells = <2>;
501 interrupt-controller;
502 #interrupt-cells = <2>;
503 };
505 gpio1: gpio@2310000 {
506 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
507 reg = <0x0 0x2310000 0x0 0x10000>;
508 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
509 gpio-controller;
510 #gpio-cells = <2>;
511 interrupt-controller;
512 #interrupt-cells = <2>;
513 };
515 gpio2: gpio@2320000 {
516 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
517 reg = <0x0 0x2320000 0x0 0x10000>;
518 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
519 gpio-controller;
520 #gpio-cells = <2>;
521 interrupt-controller;
522 #interrupt-cells = <2>;
523 };
525 gpio3: gpio@2330000 {
526 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
527 reg = <0x0 0x2330000 0x0 0x10000>;
528 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
529 gpio-controller;
530 #gpio-cells = <2>;
531 interrupt-controller;
532 #interrupt-cells = <2>;
533 };
535 lpuart0: serial@2950000 {
536 compatible = "fsl,ls1021a-lpuart";
537 reg = <0x0 0x2950000 0x0 0x1000>;
538 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&sysclk>;
540 clock-names = "ipg";
541 status = "disabled";
542 };
544 lpuart1: serial@2960000 {
545 compatible = "fsl,ls1021a-lpuart";
546 reg = <0x0 0x2960000 0x0 0x1000>;
547 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&clockgen 4 1>;
549 clock-names = "ipg";
550 status = "disabled";
551 };
553 lpuart2: serial@2970000 {
554 compatible = "fsl,ls1021a-lpuart";
555 reg = <0x0 0x2970000 0x0 0x1000>;
556 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&clockgen 4 1>;
558 clock-names = "ipg";
559 status = "disabled";
560 };
562 lpuart3: serial@2980000 {
563 compatible = "fsl,ls1021a-lpuart";
564 reg = <0x0 0x2980000 0x0 0x1000>;
565 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&clockgen 4 1>;
567 clock-names = "ipg";
568 status = "disabled";
569 };
571 lpuart4: serial@2990000 {
572 compatible = "fsl,ls1021a-lpuart";
573 reg = <0x0 0x2990000 0x0 0x1000>;
574 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&clockgen 4 1>;
576 clock-names = "ipg";
577 status = "disabled";
578 };
580 lpuart5: serial@29a0000 {
581 compatible = "fsl,ls1021a-lpuart";
582 reg = <0x0 0x29a0000 0x0 0x1000>;
583 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&clockgen 4 1>;
585 clock-names = "ipg";
586 status = "disabled";
587 };
589 pwm0: pwm@29d0000 {
590 compatible = "fsl,vf610-ftm-pwm";
591 #pwm-cells = <3>;
592 reg = <0x0 0x29d0000 0x0 0x10000>;
593 clock-names = "ftm_sys", "ftm_ext",
594 "ftm_fix", "ftm_cnt_clk_en";
595 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
596 <&clockgen 4 1>, <&clockgen 4 1>;
597 big-endian;
598 status = "disabled";
599 };
601 pwm1: pwm@29e0000 {
602 compatible = "fsl,vf610-ftm-pwm";
603 #pwm-cells = <3>;
604 reg = <0x0 0x29e0000 0x0 0x10000>;
605 clock-names = "ftm_sys", "ftm_ext",
606 "ftm_fix", "ftm_cnt_clk_en";
607 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
608 <&clockgen 4 1>, <&clockgen 4 1>;
609 big-endian;
610 status = "disabled";
611 };
613 pwm2: pwm@29f0000 {
614 compatible = "fsl,vf610-ftm-pwm";
615 #pwm-cells = <3>;
616 reg = <0x0 0x29f0000 0x0 0x10000>;
617 clock-names = "ftm_sys", "ftm_ext",
618 "ftm_fix", "ftm_cnt_clk_en";
619 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
620 <&clockgen 4 1>, <&clockgen 4 1>;
621 big-endian;
622 status = "disabled";
623 };
625 pwm3: pwm@2a00000 {
626 compatible = "fsl,vf610-ftm-pwm";
627 #pwm-cells = <3>;
628 reg = <0x0 0x2a00000 0x0 0x10000>;
629 clock-names = "ftm_sys", "ftm_ext",
630 "ftm_fix", "ftm_cnt_clk_en";
631 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
632 <&clockgen 4 1>, <&clockgen 4 1>;
633 big-endian;
634 status = "disabled";
635 };
637 pwm4: pwm@2a10000 {
638 compatible = "fsl,vf610-ftm-pwm";
639 #pwm-cells = <3>;
640 reg = <0x0 0x2a10000 0x0 0x10000>;
641 clock-names = "ftm_sys", "ftm_ext",
642 "ftm_fix", "ftm_cnt_clk_en";
643 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
644 <&clockgen 4 1>, <&clockgen 4 1>;
645 big-endian;
646 status = "disabled";
647 };
649 pwm5: pwm@2a20000 {
650 compatible = "fsl,vf610-ftm-pwm";
651 #pwm-cells = <3>;
652 reg = <0x0 0x2a20000 0x0 0x10000>;
653 clock-names = "ftm_sys", "ftm_ext",
654 "ftm_fix", "ftm_cnt_clk_en";
655 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
656 <&clockgen 4 1>, <&clockgen 4 1>;
657 big-endian;
658 status = "disabled";
659 };
661 pwm6: pwm@2a30000 {
662 compatible = "fsl,vf610-ftm-pwm";
663 #pwm-cells = <3>;
664 reg = <0x0 0x2a30000 0x0 0x10000>;
665 clock-names = "ftm_sys", "ftm_ext",
666 "ftm_fix", "ftm_cnt_clk_en";
667 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
668 <&clockgen 4 1>, <&clockgen 4 1>;
669 big-endian;
670 status = "disabled";
671 };
673 pwm7: pwm@2a40000 {
674 compatible = "fsl,vf610-ftm-pwm";
675 #pwm-cells = <3>;
676 reg = <0x0 0x2a40000 0x0 0x10000>;
677 clock-names = "ftm_sys", "ftm_ext",
678 "ftm_fix", "ftm_cnt_clk_en";
679 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
680 <&clockgen 4 1>, <&clockgen 4 1>;
681 big-endian;
682 status = "disabled";
683 };
685 wdog0: watchdog@2ad0000 {
686 compatible = "fsl,imx21-wdt";
687 reg = <0x0 0x2ad0000 0x0 0x10000>;
688 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&clockgen 4 1>;
690 clock-names = "wdog-en";
691 big-endian;
692 };
694 sai1: sai@2b50000 {
695 #sound-dai-cells = <0>;
696 compatible = "fsl,vf610-sai";
697 reg = <0x0 0x2b50000 0x0 0x10000>;
698 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
700 <&clockgen 4 1>, <&clockgen 4 1>;
701 clock-names = "bus", "mclk1", "mclk2", "mclk3";
702 dma-names = "tx", "rx";
703 dmas = <&edma0 1 47>,
704 <&edma0 1 46>;
705 status = "disabled";
706 };
708 sai2: sai@2b60000 {
709 #sound-dai-cells = <0>;
710 compatible = "fsl,vf610-sai";
711 reg = <0x0 0x2b60000 0x0 0x10000>;
712 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
714 <&clockgen 4 1>, <&clockgen 4 1>;
715 clock-names = "bus", "mclk1", "mclk2", "mclk3";
716 dma-names = "tx", "rx";
717 dmas = <&edma0 1 45>,
718 <&edma0 1 44>;
719 status = "disabled";
720 };
722 edma0: edma@2c00000 {
723 #dma-cells = <2>;
724 compatible = "fsl,vf610-edma";
725 reg = <0x0 0x2c00000 0x0 0x10000>,
726 <0x0 0x2c10000 0x0 0x10000>,
727 <0x0 0x2c20000 0x0 0x10000>;
728 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
729 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
730 interrupt-names = "edma-tx", "edma-err";
731 dma-channels = <32>;
732 big-endian;
733 clock-names = "dmamux0", "dmamux1";
734 clocks = <&clockgen 4 1>,
735 <&clockgen 4 1>;
736 };
738 dcu: dcu@2ce0000 {
739 compatible = "fsl,ls1021a-dcu";
740 reg = <0x0 0x2ce0000 0x0 0x10000>;
741 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
742 clocks = <&clockgen 4 0>,
743 <&clockgen 4 0>;
744 clock-names = "dcu", "pix";
745 big-endian;
746 status = "disabled";
747 };
749 mdio0: mdio@2d24000 {
750 compatible = "gianfar";
751 device_type = "mdio";
752 #address-cells = <1>;
753 #size-cells = <0>;
754 reg = <0x0 0x2d24000 0x0 0x4000>,
755 <0x0 0x2d10030 0x0 0x4>;
756 };
758 mdio1: mdio@2d64000 {
759 compatible = "gianfar";
760 device_type = "mdio";
761 #address-cells = <1>;
762 #size-cells = <0>;
763 reg = <0x0 0x2d64000 0x0 0x4000>,
764 <0x0 0x2d50030 0x0 0x4>;
765 };
767 ptp_clock@2d10e00 {
768 compatible = "fsl,etsec-ptp";
769 reg = <0x0 0x2d10e00 0x0 0xb0>;
770 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
771 fsl,tclk-period = <5>;
772 fsl,tmr-prsc = <2>;
773 fsl,tmr-add = <0xaaaaaaab>;
774 fsl,tmr-fiper1 = <999999995>;
775 fsl,tmr-fiper2 = <99990>;
776 fsl,max-adj = <499999999>;
777 fsl,extts-fifo;
778 };
780 enet0: ethernet@2d10000 {
781 compatible = "fsl,etsec2";
782 device_type = "network";
783 #address-cells = <2>;
784 #size-cells = <2>;
785 interrupt-parent = <&gic>;
786 model = "eTSEC";
787 fsl,magic-packet;
788 ranges;
789 dma-coherent;
791 queue-group@2d10000 {
792 #address-cells = <2>;
793 #size-cells = <2>;
794 reg = <0x0 0x2d10000 0x0 0x1000>;
795 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
796 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
797 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
798 };
800 queue-group@2d14000 {
801 #address-cells = <2>;
802 #size-cells = <2>;
803 reg = <0x0 0x2d14000 0x0 0x1000>;
804 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
806 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
807 };
808 };
810 enet1: ethernet@2d50000 {
811 compatible = "fsl,etsec2";
812 device_type = "network";
813 #address-cells = <2>;
814 #size-cells = <2>;
815 interrupt-parent = <&gic>;
816 model = "eTSEC";
817 ranges;
818 dma-coherent;
820 queue-group@2d50000 {
821 #address-cells = <2>;
822 #size-cells = <2>;
823 reg = <0x0 0x2d50000 0x0 0x1000>;
824 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
825 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
826 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
827 };
829 queue-group@2d54000 {
830 #address-cells = <2>;
831 #size-cells = <2>;
832 reg = <0x0 0x2d54000 0x0 0x1000>;
833 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
836 };
837 };
839 enet2: ethernet@2d90000 {
840 compatible = "fsl,etsec2";
841 device_type = "network";
842 #address-cells = <2>;
843 #size-cells = <2>;
844 interrupt-parent = <&gic>;
845 model = "eTSEC";
846 ranges;
847 dma-coherent;
849 queue-group@2d90000 {
850 #address-cells = <2>;
851 #size-cells = <2>;
852 reg = <0x0 0x2d90000 0x0 0x1000>;
853 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
854 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
855 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
856 };
858 queue-group@2d94000 {
859 #address-cells = <2>;
860 #size-cells = <2>;
861 reg = <0x0 0x2d94000 0x0 0x1000>;
862 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
863 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
864 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
865 };
866 };
868 usb2: usb@8600000 {
869 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
870 reg = <0x0 0x8600000 0x0 0x1000>;
871 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
872 dr_mode = "host";
873 phy_type = "ulpi";
874 };
876 usb3: usb3@3100000 {
877 compatible = "snps,dwc3";
878 reg = <0x0 0x3100000 0x0 0x10000>;
879 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
880 dr_mode = "host";
881 snps,quirk-frame-length-adjustment = <0x20>;
882 snps,dis_rxdet_inp3_quirk;
883 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
884 };
886 pcie@3400000 {
887 compatible = "fsl,ls1021a-pcie";
888 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
889 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
890 reg-names = "regs", "config";
891 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
892 fsl,pcie-scfg = <&scfg 0>;
893 #address-cells = <3>;
894 #size-cells = <2>;
895 device_type = "pci";
896 num-viewport = <6>;
897 bus-range = <0x0 0xff>;
898 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
899 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
900 msi-parent = <&msi1>, <&msi2>;
901 #interrupt-cells = <1>;
902 interrupt-map-mask = <0 0 0 7>;
903 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
904 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
905 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
906 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
907 status = "disabled";
908 };
910 pcie@3500000 {
911 compatible = "fsl,ls1021a-pcie";
912 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
913 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
914 reg-names = "regs", "config";
915 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
916 fsl,pcie-scfg = <&scfg 1>;
917 #address-cells = <3>;
918 #size-cells = <2>;
919 device_type = "pci";
920 num-viewport = <6>;
921 bus-range = <0x0 0xff>;
922 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
923 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
924 msi-parent = <&msi1>, <&msi2>;
925 #interrupt-cells = <1>;
926 interrupt-map-mask = <0 0 0 7>;
927 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
928 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
929 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
930 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
931 status = "disabled";
932 };
934 can0: can@2a70000 {
935 compatible = "fsl,ls1021ar2-flexcan";
936 reg = <0x0 0x2a70000 0x0 0x1000>;
937 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
939 clock-names = "ipg", "per";
940 big-endian;
941 };
943 can1: can@2a80000 {
944 compatible = "fsl,ls1021ar2-flexcan";
945 reg = <0x0 0x2a80000 0x0 0x1000>;
946 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
948 clock-names = "ipg", "per";
949 big-endian;
950 };
952 can2: can@2a90000 {
953 compatible = "fsl,ls1021ar2-flexcan";
954 reg = <0x0 0x2a90000 0x0 0x1000>;
955 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
957 clock-names = "ipg", "per";
958 big-endian;
959 };
961 can3: can@2aa0000 {
962 compatible = "fsl,ls1021ar2-flexcan";
963 reg = <0x0 0x2aa0000 0x0 0x1000>;
964 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
965 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
966 clock-names = "ipg", "per";
967 big-endian;
968 };
970 ocram1: sram@10000000 {
971 compatible = "mmio-sram";
972 reg = <0x0 0x10000000 0x0 0x10000>;
973 #address-cells = <1>;
974 #size-cells = <1>;
975 ranges = <0x0 0x0 0x10000000 0x10000>;
976 };
978 ocram2: sram@10010000 {
979 compatible = "mmio-sram";
980 reg = <0x0 0x10010000 0x0 0x10000>;
981 #address-cells = <1>;
982 #size-cells = <1>;
983 ranges = <0x0 0x0 0x10010000 0x10000>;
984 };
986 qdma: dma-controller@8390000 {
987 compatible = "fsl,ls1021a-qdma";
988 reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
989 <0x0 0x8389000 0x0 0x1000>, /* Status regs */
990 <0x0 0x838a000 0x0 0x2000>; /* Block regs */
991 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
994 interrupt-names = "qdma-error",
995 "qdma-queue0", "qdma-queue1";
996 dma-channels = <8>;
997 block-number = <1>;
998 block-offset = <0x1000>;
999 fsl,dma-queues = <2>;
1000 status-sizes = <64>;
1001 queue-sizes = <64 64>;
1002 big-endian;
1003 };
1005 };
1006 };