arch/arm/boot/dts/omap2.dtsi

   1 /*
   2  * Device Tree Source for OMAP2 SoC
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/bus/ti-sysc.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14 #include <dt-bindings/pinctrl/omap.h>
  15
  16 / {
  17         compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
  18         interrupt-parent = <&intc>;
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21         chosen { };
  22
  23         aliases {
  24                 serial0 = &uart1;
  25                 serial1 = &uart2;
  26                 serial2 = &uart3;
  27                 i2c0 = &i2c1;
  28                 i2c1 = &i2c2;
  29         };
  30
  31         cpus {
  32                 #address-cells = <0>;
  33                 #size-cells = <0>;
  34
  35                 cpu {
  36                         compatible = "arm,arm1136jf-s";
  37                         device_type = "cpu";
  38                 };
  39         };
  40
  41         pmu {
  42                 compatible = "arm,arm1136-pmu";
  43                 interrupts = <3>;
  44         };
  45
  46         soc {
  47                 compatible = "ti,omap-infra";
  48                 mpu {
  49                         compatible = "ti,omap2-mpu";
  50                         ti,hwmods = "mpu";
  51                 };
  52         };
  53
  54         ocp {
  55                 compatible = "simple-bus";
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 ranges;
  59                 ti,hwmods = "l3_main";
  60
  61                 aes: aes@480a6000 {
  62                         compatible = "ti,omap2-aes";
  63                         ti,hwmods = "aes";
  64                         reg = <0x480a6000 0x50>;
  65                         dmas = <&sdma 9 &sdma 10>;
  66                         dma-names = "tx", "rx";
  67                 };
  68
  69                 hdq1w: 1w@480b2000 {
  70                         compatible = "ti,omap2420-1w";
  71                         ti,hwmods = "hdq1w";
  72                         reg = <0x480b2000 0x1000>;
  73                         interrupts = <58>;
  74                 };
  75
  76                 intc: interrupt-controller@1 {
  77                         compatible = "ti,omap2-intc";
  78                         interrupt-controller;
  79                         #interrupt-cells = <1>;
  80                         reg = <0x480FE000 0x1000>;
  81                 };
  82
  83                 target-module@48056000 {
  84                         compatible = "ti,sysc-omap2", "ti,sysc";
  85                         reg = <0x48056000 0x4>,
  86                               <0x4805602c 0x4>,
  87                               <0x48056028 0x4>;
  88                         reg-names = "rev", "sysc", "syss";
  89                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
  90                                          SYSC_OMAP2_EMUFREE |
  91                                          SYSC_OMAP2_SOFTRESET |
  92                                          SYSC_OMAP2_AUTOIDLE)>;
  93                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
  94                                         <SYSC_IDLE_NO>,
  95                                         <SYSC_IDLE_SMART>;
  96                         ti,syss-mask = <1>;
  97                         clocks = <&core_l3_ck>;
  98                         clock-names = "fck";
  99                         #address-cells = <1>;
 100                         #size-cells = <1>;
 101                         ranges = <0 0x48056000 0x1000>;
 102
 103                         sdma: dma-controller@0 {
 104                                 compatible = "ti,omap2420-sdma", "ti,omap-sdma";
 105                                 reg = <0 0x1000>;
 106                                 interrupts = <12>,
 107                                              <13>,
 108                                              <14>,
 109                                              <15>;
 110                                 #dma-cells = <1>;
 111                                 dma-channels = <32>;
 112                                 dma-requests = <64>;
 113                         };
 114                 };
 115
 116                 i2c1: i2c@48070000 {
 117                         compatible = "ti,omap2-i2c";
 118                         ti,hwmods = "i2c1";
 119                         reg = <0x48070000 0x80>;
 120                         #address-cells = <1>;
 121                         #size-cells = <0>;
 122                         interrupts = <56>;
 123                         dmas = <&sdma 27 &sdma 28>;
 124                         dma-names = "tx", "rx";
 125                 };
 126
 127                 i2c2: i2c@48072000 {
 128                         compatible = "ti,omap2-i2c";
 129                         ti,hwmods = "i2c2";
 130                         reg = <0x48072000 0x80>;
 131                         #address-cells = <1>;
 132                         #size-cells = <0>;
 133                         interrupts = <57>;
 134                         dmas = <&sdma 29 &sdma 30>;
 135                         dma-names = "tx", "rx";
 136                 };
 137
 138                 mcspi1: spi@48098000 {
 139                         compatible = "ti,omap2-mcspi";
 140                         ti,hwmods = "mcspi1";
 141                         reg = <0x48098000 0x100>;
 142                         interrupts = <65>;
 143                         dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
 144                                 &sdma 39 &sdma 40 &sdma 41 &sdma 42>;
 145                         dma-names = "tx0", "rx0", "tx1", "rx1",
 146                                     "tx2", "rx2", "tx3", "rx3";
 147                 };
 148
 149                 mcspi2: spi@4809a000 {
 150                         compatible = "ti,omap2-mcspi";
 151                         ti,hwmods = "mcspi2";
 152                         reg = <0x4809a000 0x100>;
 153                         interrupts = <66>;
 154                         dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
 155                         dma-names = "tx0", "rx0", "tx1", "rx1";
 156                 };
 157
 158                 rng: rng@480a0000 {
 159                         compatible = "ti,omap2-rng";
 160                         ti,hwmods = "rng";
 161                         reg = <0x480a0000 0x50>;
 162                         interrupts = <52>;
 163                 };
 164
 165                 sham: sham@480a4000 {
 166                         compatible = "ti,omap2-sham";
 167                         ti,hwmods = "sham";
 168                         reg = <0x480a4000 0x64>;
 169                         interrupts = <51>;
 170                         dmas = <&sdma 13>;
 171                         dma-names = "rx";
 172                 };
 173
 174                 uart1: serial@4806a000 {
 175                         compatible = "ti,omap2-uart";
 176                         ti,hwmods = "uart1";
 177                         reg = <0x4806a000 0x2000>;
 178                         interrupts = <72>;
 179                         dmas = <&sdma 49 &sdma 50>;
 180                         dma-names = "tx", "rx";
 181                         clock-frequency = <48000000>;
 182                 };
 183
 184                 uart2: serial@4806c000 {
 185                         compatible = "ti,omap2-uart";
 186                         ti,hwmods = "uart2";
 187                         reg = <0x4806c000 0x400>;
 188                         interrupts = <73>;
 189                         dmas = <&sdma 51 &sdma 52>;
 190                         dma-names = "tx", "rx";
 191                         clock-frequency = <48000000>;
 192                 };
 193
 194                 uart3: serial@4806e000 {
 195                         compatible = "ti,omap2-uart";
 196                         ti,hwmods = "uart3";
 197                         reg = <0x4806e000 0x400>;
 198                         interrupts = <74>;
 199                         dmas = <&sdma 53 &sdma 54>;
 200                         dma-names = "tx", "rx";
 201                         clock-frequency = <48000000>;
 202                 };
 203
 204                 timer2: timer@4802a000 {
 205                         compatible = "ti,omap2420-timer";
 206                         reg = <0x4802a000 0x400>;
 207                         interrupts = <38>;
 208                         ti,hwmods = "timer2";
 209                 };
 210
 211                 timer3: timer@48078000 {
 212                         compatible = "ti,omap2420-timer";
 213                         reg = <0x48078000 0x400>;
 214                         interrupts = <39>;
 215                         ti,hwmods = "timer3";
 216                 };
 217
 218                 timer4: timer@4807a000 {
 219                         compatible = "ti,omap2420-timer";
 220                         reg = <0x4807a000 0x400>;
 221                         interrupts = <40>;
 222                         ti,hwmods = "timer4";
 223                 };
 224
 225                 timer5: timer@4807c000 {
 226                         compatible = "ti,omap2420-timer";
 227                         reg = <0x4807c000 0x400>;
 228                         interrupts = <41>;
 229                         ti,hwmods = "timer5";
 230                         ti,timer-dsp;
 231                 };
 232
 233                 timer6: timer@4807e000 {
 234                         compatible = "ti,omap2420-timer";
 235                         reg = <0x4807e000 0x400>;
 236                         interrupts = <42>;
 237                         ti,hwmods = "timer6";
 238                         ti,timer-dsp;
 239                 };
 240
 241                 timer7: timer@48080000 {
 242                         compatible = "ti,omap2420-timer";
 243                         reg = <0x48080000 0x400>;
 244                         interrupts = <43>;
 245                         ti,hwmods = "timer7";
 246                         ti,timer-dsp;
 247                 };
 248
 249                 timer8: timer@48082000 {
 250                         compatible = "ti,omap2420-timer";
 251                         reg = <0x48082000 0x400>;
 252                         interrupts = <44>;
 253                         ti,hwmods = "timer8";
 254                         ti,timer-dsp;
 255                 };
 256
 257                 timer9: timer@48084000 {
 258                         compatible = "ti,omap2420-timer";
 259                         reg = <0x48084000 0x400>;
 260                         interrupts = <45>;
 261                         ti,hwmods = "timer9";
 262                         ti,timer-pwm;
 263                 };
 264
 265                 timer10: timer@48086000 {
 266                         compatible = "ti,omap2420-timer";
 267                         reg = <0x48086000 0x400>;
 268                         interrupts = <46>;
 269                         ti,hwmods = "timer10";
 270                         ti,timer-pwm;
 271                 };
 272
 273                 timer11: timer@48088000 {
 274                         compatible = "ti,omap2420-timer";
 275                         reg = <0x48088000 0x400>;
 276                         interrupts = <47>;
 277                         ti,hwmods = "timer11";
 278                         ti,timer-pwm;
 279                 };
 280
 281                 timer12: timer@4808a000 {
 282                         compatible = "ti,omap2420-timer";
 283                         reg = <0x4808a000 0x400>;
 284                         interrupts = <48>;
 285                         ti,hwmods = "timer12";
 286                         ti,timer-pwm;
 287                 };
 288
 289                 dss: dss@48050000 {
 290                         compatible = "ti,omap2-dss";
 291                         reg = <0x48050000 0x400>;
 292                         status = "disabled";
 293                         ti,hwmods = "dss_core";
 294                         #address-cells = <1>;
 295                         #size-cells = <1>;
 296                         ranges;
 297
 298                         dispc@48050400 {
 299                                 compatible = "ti,omap2-dispc";
 300                                 reg = <0x48050400 0x400>;
 301                                 interrupts = <25>;
 302                                 ti,hwmods = "dss_dispc";
 303                         };
 304
 305                         rfbi: encoder@48050800 {
 306                                 compatible = "ti,omap2-rfbi";
 307                                 reg = <0x48050800 0x400>;
 308                                 status = "disabled";
 309                                 ti,hwmods = "dss_rfbi";
 310                         };
 311
 312                         venc: encoder@48050c00 {
 313                                 compatible = "ti,omap2-venc";
 314                                 reg = <0x48050c00 0x400>;
 315                                 status = "disabled";
 316                                 ti,hwmods = "dss_venc";
 317                         };
 318                 };
 319         };
 320 };