| blob | 2012b7407c605d16eabfac20f823f4be7577bc7f |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
4 *
5 * Copyright (C) 2015 Atmel,
6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 */
9 #include <dt-bindings/dma/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
14 / {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 model = "Atmel SAMA5D2 family SoC";
18 compatible = "atmel,sama5d2";
19 interrupt-parent = <&aic>;
21 aliases {
22 serial0 = &uart1;
23 serial1 = &uart3;
24 tcb0 = &tcb0;
25 tcb1 = &tcb1;
26 i2s0 = &i2s0;
27 i2s1 = &i2s1;
28 };
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu@0 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a5";
37 reg = <0>;
38 next-level-cache = <&L2>;
39 };
40 };
42 pmu {
43 compatible = "arm,cortex-a5-pmu";
44 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
45 };
47 etb {
48 compatible = "arm,coresight-etb10", "arm,primecell";
49 reg = <0x740000 0x1000>;
51 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
52 clock-names = "apb_pclk";
54 in-ports {
55 port {
56 etb_in: endpoint {
57 remote-endpoint = <&etm_out>;
58 };
59 };
60 };
61 };
63 etm {
64 compatible = "arm,coresight-etm3x", "arm,primecell";
65 reg = <0x73C000 0x1000>;
67 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
68 clock-names = "apb_pclk";
70 out-ports {
71 port {
72 etm_out: endpoint {
73 remote-endpoint = <&etb_in>;
74 };
75 };
76 };
77 };
79 memory {
80 device_type = "memory";
81 reg = <0x20000000 0x20000000>;
82 };
84 clocks {
85 slow_xtal: slow_xtal {
86 compatible = "fixed-clock";
87 #clock-cells = <0>;
88 clock-frequency = <0>;
89 };
91 main_xtal: main_xtal {
92 compatible = "fixed-clock";
93 #clock-cells = <0>;
94 clock-frequency = <0>;
95 };
96 };
98 ns_sram: sram@200000 {
99 compatible = "mmio-sram";
100 reg = <0x00200000 0x20000>;
101 };
103 ahb {
104 compatible = "simple-bus";
105 #address-cells = <1>;
106 #size-cells = <1>;
107 ranges;
109 nfc_sram: sram@100000 {
110 compatible = "mmio-sram";
111 no-memory-wc;
112 reg = <0x00100000 0x2400>;
113 };
115 usb0: gadget@300000 {
116 #address-cells = <1>;
117 #size-cells = <0>;
118 compatible = "atmel,sama5d3-udc";
119 reg = <0x00300000 0x100000
120 0xfc02c000 0x400>;
121 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
122 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
123 clock-names = "pclk", "hclk";
124 status = "disabled";
126 ep@0 {
127 reg = <0>;
128 atmel,fifo-size = <64>;
129 atmel,nb-banks = <1>;
130 };
132 ep@1 {
133 reg = <1>;
134 atmel,fifo-size = <1024>;
135 atmel,nb-banks = <3>;
136 atmel,can-dma;
137 atmel,can-isoc;
138 };
140 ep@2 {
141 reg = <2>;
142 atmel,fifo-size = <1024>;
143 atmel,nb-banks = <3>;
144 atmel,can-dma;
145 atmel,can-isoc;
146 };
148 ep@3 {
149 reg = <3>;
150 atmel,fifo-size = <1024>;
151 atmel,nb-banks = <2>;
152 atmel,can-dma;
153 atmel,can-isoc;
154 };
156 ep@4 {
157 reg = <4>;
158 atmel,fifo-size = <1024>;
159 atmel,nb-banks = <2>;
160 atmel,can-dma;
161 atmel,can-isoc;
162 };
164 ep@5 {
165 reg = <5>;
166 atmel,fifo-size = <1024>;
167 atmel,nb-banks = <2>;
168 atmel,can-dma;
169 atmel,can-isoc;
170 };
172 ep@6 {
173 reg = <6>;
174 atmel,fifo-size = <1024>;
175 atmel,nb-banks = <2>;
176 atmel,can-dma;
177 atmel,can-isoc;
178 };
180 ep@7 {
181 reg = <7>;
182 atmel,fifo-size = <1024>;
183 atmel,nb-banks = <2>;
184 atmel,can-dma;
185 atmel,can-isoc;
186 };
188 ep@8 {
189 reg = <8>;
190 atmel,fifo-size = <1024>;
191 atmel,nb-banks = <2>;
192 atmel,can-isoc;
193 };
195 ep@9 {
196 reg = <9>;
197 atmel,fifo-size = <1024>;
198 atmel,nb-banks = <2>;
199 atmel,can-isoc;
200 };
202 ep@10 {
203 reg = <10>;
204 atmel,fifo-size = <1024>;
205 atmel,nb-banks = <2>;
206 atmel,can-isoc;
207 };
209 ep@11 {
210 reg = <11>;
211 atmel,fifo-size = <1024>;
212 atmel,nb-banks = <2>;
213 atmel,can-isoc;
214 };
216 ep@12 {
217 reg = <12>;
218 atmel,fifo-size = <1024>;
219 atmel,nb-banks = <2>;
220 atmel,can-isoc;
221 };
223 ep@13 {
224 reg = <13>;
225 atmel,fifo-size = <1024>;
226 atmel,nb-banks = <2>;
227 atmel,can-isoc;
228 };
230 ep@14 {
231 reg = <14>;
232 atmel,fifo-size = <1024>;
233 atmel,nb-banks = <2>;
234 atmel,can-isoc;
235 };
237 ep@15 {
238 reg = <15>;
239 atmel,fifo-size = <1024>;
240 atmel,nb-banks = <2>;
241 atmel,can-isoc;
242 };
243 };
245 usb1: ohci@400000 {
246 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
247 reg = <0x00400000 0x100000>;
248 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
249 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>;
250 clock-names = "ohci_clk", "hclk", "uhpck";
251 status = "disabled";
252 };
254 usb2: ehci@500000 {
255 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
256 reg = <0x00500000 0x100000>;
257 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
258 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>;
259 clock-names = "usb_clk", "ehci_clk";
260 status = "disabled";
261 };
263 L2: cache-controller@a00000 {
264 compatible = "arm,pl310-cache";
265 reg = <0x00a00000 0x1000>;
266 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
267 cache-unified;
268 cache-level = <2>;
269 };
271 ebi: ebi@10000000 {
272 compatible = "atmel,sama5d3-ebi";
273 #address-cells = <2>;
274 #size-cells = <1>;
275 atmel,smc = <&hsmc>;
276 reg = <0x10000000 0x10000000
277 0x60000000 0x30000000>;
278 ranges = <0x0 0x0 0x10000000 0x10000000
279 0x1 0x0 0x60000000 0x10000000
280 0x2 0x0 0x70000000 0x10000000
281 0x3 0x0 0x80000000 0x10000000>;
282 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
283 status = "disabled";
285 nand_controller: nand-controller {
286 compatible = "atmel,sama5d3-nand-controller";
287 atmel,nfc-sram = <&nfc_sram>;
288 atmel,nfc-io = <&nfc_io>;
289 ecc-engine = <&pmecc>;
290 #address-cells = <2>;
291 #size-cells = <1>;
292 ranges;
293 status = "disabled";
294 };
295 };
297 sdmmc0: sdio-host@a0000000 {
298 compatible = "atmel,sama5d2-sdhci";
299 reg = <0xa0000000 0x300>;
300 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
301 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
302 clock-names = "hclock", "multclk", "baseclk";
303 assigned-clocks = <&pmc PMC_TYPE_GCK 31>;
304 assigned-clock-rates = <480000000>;
305 status = "disabled";
306 };
308 sdmmc1: sdio-host@b0000000 {
309 compatible = "atmel,sama5d2-sdhci";
310 reg = <0xb0000000 0x300>;
311 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
312 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
313 clock-names = "hclock", "multclk", "baseclk";
314 assigned-clocks = <&pmc PMC_TYPE_GCK 32>;
315 assigned-clock-rates = <480000000>;
316 status = "disabled";
317 };
319 nfc_io: nfc-io@c0000000 {
320 compatible = "atmel,sama5d3-nfc-io", "syscon";
321 reg = <0xc0000000 0x8000000>;
322 };
324 apb {
325 compatible = "simple-bus";
326 #address-cells = <1>;
327 #size-cells = <1>;
328 ranges;
330 hlcdc: hlcdc@f0000000 {
331 compatible = "atmel,sama5d2-hlcdc";
332 reg = <0xf0000000 0x2000>;
333 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
334 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
335 clock-names = "periph_clk","sys_clk", "slow_clk";
336 status = "disabled";
338 hlcdc-display-controller {
339 compatible = "atmel,hlcdc-display-controller";
340 #address-cells = <1>;
341 #size-cells = <0>;
343 port@0 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 reg = <0>;
347 };
348 };
350 hlcdc_pwm: hlcdc-pwm {
351 compatible = "atmel,hlcdc-pwm";
352 #pwm-cells = <3>;
353 };
354 };
356 isc: isc@f0008000 {
357 compatible = "atmel,sama5d2-isc";
358 reg = <0xf0008000 0x4000>;
359 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
360 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>;
361 clock-names = "hclock", "iscck", "gck";
362 #clock-cells = <0>;
363 clock-output-names = "isc-mck";
364 status = "disabled";
365 };
367 ramc0: ramc@f000c000 {
368 compatible = "atmel,sama5d3-ddramc";
369 reg = <0xf000c000 0x200>;
370 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>;
371 clock-names = "ddrck", "mpddr";
372 };
374 dma0: dma-controller@f0010000 {
375 compatible = "atmel,sama5d4-dma";
376 reg = <0xf0010000 0x1000>;
377 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
378 #dma-cells = <1>;
379 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
380 clock-names = "dma_clk";
381 };
383 /* Place dma1 here despite its address */
384 dma1: dma-controller@f0004000 {
385 compatible = "atmel,sama5d4-dma";
386 reg = <0xf0004000 0x1000>;
387 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
388 #dma-cells = <1>;
389 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
390 clock-names = "dma_clk";
391 };
393 pmc: pmc@f0014000 {
394 compatible = "atmel,sama5d2-pmc", "syscon";
395 reg = <0xf0014000 0x160>;
396 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
397 #clock-cells = <2>;
398 clocks = <&clk32k>, <&main_xtal>;
399 clock-names = "slow_clk", "main_xtal";
400 };
402 qspi0: spi@f0020000 {
403 compatible = "atmel,sama5d2-qspi";
404 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
405 reg-names = "qspi_base", "qspi_mmap";
406 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
407 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
408 #address-cells = <1>;
409 #size-cells = <0>;
410 status = "disabled";
411 };
413 qspi1: spi@f0024000 {
414 compatible = "atmel,sama5d2-qspi";
415 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
416 reg-names = "qspi_base", "qspi_mmap";
417 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
418 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
419 #address-cells = <1>;
420 #size-cells = <0>;
421 status = "disabled";
422 };
424 sha@f0028000 {
425 compatible = "atmel,at91sam9g46-sha";
426 reg = <0xf0028000 0x100>;
427 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
428 dmas = <&dma0
429 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
430 AT91_XDMAC_DT_PERID(30))>;
431 dma-names = "tx";
432 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
433 clock-names = "sha_clk";
434 status = "okay";
435 };
437 aes@f002c000 {
438 compatible = "atmel,at91sam9g46-aes";
439 reg = <0xf002c000 0x100>;
440 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
441 dmas = <&dma0
442 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
443 AT91_XDMAC_DT_PERID(26))>,
444 <&dma0
445 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
446 AT91_XDMAC_DT_PERID(27))>;
447 dma-names = "tx", "rx";
448 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
449 clock-names = "aes_clk";
450 status = "okay";
451 };
453 spi0: spi@f8000000 {
454 compatible = "atmel,at91rm9200-spi";
455 reg = <0xf8000000 0x100>;
456 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
457 dmas = <&dma0
458 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
459 AT91_XDMAC_DT_PERID(6))>,
460 <&dma0
461 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
462 AT91_XDMAC_DT_PERID(7))>;
463 dma-names = "tx", "rx";
464 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
465 clock-names = "spi_clk";
466 atmel,fifo-size = <16>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 status = "disabled";
470 };
472 ssc0: ssc@f8004000 {
473 compatible = "atmel,at91sam9g45-ssc";
474 reg = <0xf8004000 0x4000>;
475 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
476 dmas = <&dma0
477 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
478 AT91_XDMAC_DT_PERID(21))>,
479 <&dma0
480 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
481 AT91_XDMAC_DT_PERID(22))>;
482 dma-names = "tx", "rx";
483 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
484 clock-names = "pclk";
485 status = "disabled";
486 };
488 macb0: ethernet@f8008000 {
489 compatible = "atmel,sama5d2-gem";
490 reg = <0xf8008000 0x1000>;
491 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
492 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
493 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
494 #address-cells = <1>;
495 #size-cells = <0>;
496 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>;
497 clock-names = "hclk", "pclk";
498 status = "disabled";
499 };
501 tcb0: timer@f800c000 {
502 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
503 #address-cells = <1>;
504 #size-cells = <0>;
505 reg = <0xf800c000 0x100>;
506 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
507 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&clk32k>;
508 clock-names = "t0_clk", "slow_clk";
509 };
511 tcb1: timer@f8010000 {
512 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
513 #address-cells = <1>;
514 #size-cells = <0>;
515 reg = <0xf8010000 0x100>;
516 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
517 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&clk32k>;
518 clock-names = "t0_clk", "slow_clk";
519 };
521 hsmc: hsmc@f8014000 {
522 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
523 reg = <0xf8014000 0x1000>;
524 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
525 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
526 #address-cells = <1>;
527 #size-cells = <1>;
528 ranges;
530 pmecc: ecc-engine@f8014070 {
531 compatible = "atmel,sama5d2-pmecc";
532 reg = <0xf8014070 0x490>,
533 <0xf8014500 0x100>;
534 };
535 };
537 pdmic: pdmic@f8018000 {
538 compatible = "atmel,sama5d2-pdmic";
539 reg = <0xf8018000 0x124>;
540 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
541 dmas = <&dma0
542 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
543 | AT91_XDMAC_DT_PERID(50))>;
544 dma-names = "rx";
545 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>;
546 clock-names = "pclk", "gclk";
547 status = "disabled";
548 };
550 uart0: serial@f801c000 {
551 compatible = "atmel,at91sam9260-usart";
552 reg = <0xf801c000 0x100>;
553 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
554 dmas = <&dma0
555 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
556 AT91_XDMAC_DT_PERID(35))>,
557 <&dma0
558 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
559 AT91_XDMAC_DT_PERID(36))>;
560 dma-names = "tx", "rx";
561 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
562 clock-names = "usart";
563 status = "disabled";
564 };
566 uart1: serial@f8020000 {
567 compatible = "atmel,at91sam9260-usart";
568 reg = <0xf8020000 0x100>;
569 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
570 dmas = <&dma0
571 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
572 AT91_XDMAC_DT_PERID(37))>,
573 <&dma0
574 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
575 AT91_XDMAC_DT_PERID(38))>;
576 dma-names = "tx", "rx";
577 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
578 clock-names = "usart";
579 status = "disabled";
580 };
582 uart2: serial@f8024000 {
583 compatible = "atmel,at91sam9260-usart";
584 reg = <0xf8024000 0x100>;
585 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
586 dmas = <&dma0
587 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
588 AT91_XDMAC_DT_PERID(39))>,
589 <&dma0
590 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
591 AT91_XDMAC_DT_PERID(40))>;
592 dma-names = "tx", "rx";
593 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
594 clock-names = "usart";
595 status = "disabled";
596 };
598 i2c0: i2c@f8028000 {
599 compatible = "atmel,sama5d2-i2c";
600 reg = <0xf8028000 0x100>;
601 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
602 dmas = <&dma0
603 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
604 AT91_XDMAC_DT_PERID(0))>,
605 <&dma0
606 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
607 AT91_XDMAC_DT_PERID(1))>;
608 dma-names = "tx", "rx";
609 #address-cells = <1>;
610 #size-cells = <0>;
611 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
612 atmel,fifo-size = <16>;
613 status = "disabled";
614 };
616 pwm0: pwm@f802c000 {
617 compatible = "atmel,sama5d2-pwm";
618 reg = <0xf802c000 0x4000>;
619 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
620 #pwm-cells = <3>;
621 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
622 status = "disabled";
623 };
625 sfr: sfr@f8030000 {
626 compatible = "atmel,sama5d2-sfr", "syscon";
627 reg = <0xf8030000 0x98>;
628 };
630 flx0: flexcom@f8034000 {
631 compatible = "atmel,sama5d2-flexcom";
632 reg = <0xf8034000 0x200>;
633 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
634 #address-cells = <1>;
635 #size-cells = <1>;
636 ranges = <0x0 0xf8034000 0x800>;
637 status = "disabled";
638 };
640 flx1: flexcom@f8038000 {
641 compatible = "atmel,sama5d2-flexcom";
642 reg = <0xf8038000 0x200>;
643 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
644 #address-cells = <1>;
645 #size-cells = <1>;
646 ranges = <0x0 0xf8038000 0x800>;
647 status = "disabled";
648 };
650 securam: sram@f8044000 {
651 compatible = "atmel,sama5d2-securam", "mmio-sram";
652 reg = <0xf8044000 0x1420>;
653 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>;
654 #address-cells = <1>;
655 #size-cells = <1>;
656 ranges = <0 0xf8044000 0x1420>;
657 };
659 reset_controller: rstc@f8048000 {
660 compatible = "atmel,sama5d3-rstc";
661 reg = <0xf8048000 0x10>;
662 clocks = <&clk32k>;
663 };
665 shutdown_controller: shdwc@f8048010 {
666 compatible = "atmel,sama5d2-shdwc";
667 reg = <0xf8048010 0x10>;
668 clocks = <&clk32k>;
669 #address-cells = <1>;
670 #size-cells = <0>;
671 atmel,wakeup-rtc-timer;
672 };
674 pit: timer@f8048030 {
675 compatible = "atmel,at91sam9260-pit";
676 reg = <0xf8048030 0x10>;
677 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
678 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
679 };
681 watchdog: watchdog@f8048040 {
682 compatible = "atmel,sama5d4-wdt";
683 reg = <0xf8048040 0x10>;
684 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
685 clocks = <&clk32k>;
686 status = "disabled";
687 };
689 clk32k: sckc@f8048050 {
690 compatible = "atmel,sama5d4-sckc";
691 reg = <0xf8048050 0x4>;
693 clocks = <&slow_xtal>;
694 #clock-cells = <0>;
695 };
697 rtc: rtc@f80480b0 {
698 compatible = "atmel,at91rm9200-rtc";
699 reg = <0xf80480b0 0x30>;
700 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
701 clocks = <&clk32k>;
702 };
704 i2s0: i2s@f8050000 {
705 compatible = "atmel,sama5d2-i2s";
706 reg = <0xf8050000 0x100>;
707 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
708 dmas = <&dma0
709 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
710 AT91_XDMAC_DT_PERID(31))>,
711 <&dma0
712 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
713 AT91_XDMAC_DT_PERID(32))>;
714 dma-names = "tx", "rx";
715 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>;
716 clock-names = "pclk", "gclk";
717 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>;
718 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>;
719 status = "disabled";
720 };
722 can0: can@f8054000 {
723 compatible = "bosch,m_can";
724 reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
725 reg-names = "m_can", "message_ram";
726 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
727 <64 IRQ_TYPE_LEVEL_HIGH 7>;
728 interrupt-names = "int0", "int1";
729 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>;
730 clock-names = "hclk", "cclk";
731 assigned-clocks = <&pmc PMC_TYPE_GCK 56>;
732 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
733 assigned-clock-rates = <40000000>;
734 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
735 status = "disabled";
736 };
738 spi1: spi@fc000000 {
739 compatible = "atmel,at91rm9200-spi";
740 reg = <0xfc000000 0x100>;
741 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
742 dmas = <&dma0
743 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
744 AT91_XDMAC_DT_PERID(8))>,
745 <&dma0
746 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
747 AT91_XDMAC_DT_PERID(9))>;
748 dma-names = "tx", "rx";
749 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
750 clock-names = "spi_clk";
751 atmel,fifo-size = <16>;
752 #address-cells = <1>;
753 #size-cells = <0>;
754 status = "disabled";
755 };
757 uart3: serial@fc008000 {
758 compatible = "atmel,at91sam9260-usart";
759 reg = <0xfc008000 0x100>;
760 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
761 dmas = <&dma1
762 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
763 AT91_XDMAC_DT_PERID(41))>,
764 <&dma1
765 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
766 AT91_XDMAC_DT_PERID(42))>;
767 dma-names = "tx", "rx";
768 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
769 clock-names = "usart";
770 status = "disabled";
771 };
773 uart4: serial@fc00c000 {
774 compatible = "atmel,at91sam9260-usart";
775 reg = <0xfc00c000 0x100>;
776 dmas = <&dma0
777 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
778 AT91_XDMAC_DT_PERID(43))>,
779 <&dma0
780 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
781 AT91_XDMAC_DT_PERID(44))>;
782 dma-names = "tx", "rx";
783 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
784 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
785 clock-names = "usart";
786 status = "disabled";
787 };
789 flx2: flexcom@fc010000 {
790 compatible = "atmel,sama5d2-flexcom";
791 reg = <0xfc010000 0x200>;
792 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
793 #address-cells = <1>;
794 #size-cells = <1>;
795 ranges = <0x0 0xfc010000 0x800>;
796 status = "disabled";
797 };
799 flx3: flexcom@fc014000 {
800 compatible = "atmel,sama5d2-flexcom";
801 reg = <0xfc014000 0x200>;
802 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
803 #address-cells = <1>;
804 #size-cells = <1>;
805 ranges = <0x0 0xfc014000 0x800>;
806 status = "disabled";
807 };
809 flx4: flexcom@fc018000 {
810 compatible = "atmel,sama5d2-flexcom";
811 reg = <0xfc018000 0x200>;
812 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
813 #address-cells = <1>;
814 #size-cells = <1>;
815 ranges = <0x0 0xfc018000 0x800>;
816 status = "disabled";
817 };
819 trng@fc01c000 {
820 compatible = "atmel,at91sam9g45-trng";
821 reg = <0xfc01c000 0x100>;
822 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
823 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
824 };
826 aic: interrupt-controller@fc020000 {
827 #interrupt-cells = <3>;
828 compatible = "atmel,sama5d2-aic";
829 interrupt-controller;
830 reg = <0xfc020000 0x200>;
831 atmel,external-irqs = <49>;
832 };
834 i2c1: i2c@fc028000 {
835 compatible = "atmel,sama5d2-i2c";
836 reg = <0xfc028000 0x100>;
837 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
838 dmas = <&dma0
839 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
840 AT91_XDMAC_DT_PERID(2))>,
841 <&dma0
842 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
843 AT91_XDMAC_DT_PERID(3))>;
844 dma-names = "tx", "rx";
845 #address-cells = <1>;
846 #size-cells = <0>;
847 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
848 atmel,fifo-size = <16>;
849 status = "disabled";
850 };
852 adc: adc@fc030000 {
853 compatible = "atmel,sama5d2-adc";
854 reg = <0xfc030000 0x100>;
855 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
856 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
857 clock-names = "adc_clk";
858 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
859 dma-names = "rx";
860 atmel,min-sample-rate-hz = <200000>;
861 atmel,max-sample-rate-hz = <20000000>;
862 atmel,startup-time-ms = <4>;
863 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
864 #io-channel-cells = <1>;
865 status = "disabled";
866 };
868 resistive_touch: resistive-touch {
869 compatible = "resistive-adc-touch";
870 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>,
871 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>,
872 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>;
873 io-channel-names = "x", "y", "pressure";
874 touchscreen-min-pressure = <50000>;
875 status = "disabled";
876 };
878 pioA: pinctrl@fc038000 {
879 compatible = "atmel,sama5d2-pinctrl";
880 reg = <0xfc038000 0x600>;
881 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
882 <68 IRQ_TYPE_LEVEL_HIGH 7>,
883 <69 IRQ_TYPE_LEVEL_HIGH 7>,
884 <70 IRQ_TYPE_LEVEL_HIGH 7>;
885 interrupt-controller;
886 #interrupt-cells = <2>;
887 gpio-controller;
888 #gpio-cells = <2>;
889 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
890 };
892 pioBU: secumod@fc040000 {
893 compatible = "atmel,sama5d2-secumod", "syscon";
894 reg = <0xfc040000 0x100>;
896 gpio-controller;
897 #gpio-cells = <2>;
898 };
900 tdes@fc044000 {
901 compatible = "atmel,at91sam9g46-tdes";
902 reg = <0xfc044000 0x100>;
903 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
904 dmas = <&dma0
905 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
906 AT91_XDMAC_DT_PERID(28))>,
907 <&dma0
908 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
909 AT91_XDMAC_DT_PERID(29))>;
910 dma-names = "tx", "rx";
911 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
912 clock-names = "tdes_clk";
913 status = "okay";
914 };
916 classd: classd@fc048000 {
917 compatible = "atmel,sama5d2-classd";
918 reg = <0xfc048000 0x100>;
919 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
920 dmas = <&dma0
921 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
922 AT91_XDMAC_DT_PERID(47))>;
923 dma-names = "tx";
924 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
925 clock-names = "pclk", "gclk";
926 status = "disabled";
927 };
929 i2s1: i2s@fc04c000 {
930 compatible = "atmel,sama5d2-i2s";
931 reg = <0xfc04c000 0x100>;
932 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>;
933 dmas = <&dma0
934 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
935 AT91_XDMAC_DT_PERID(33))>,
936 <&dma0
937 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
938 AT91_XDMAC_DT_PERID(34))>;
939 dma-names = "tx", "rx";
940 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>;
941 clock-names = "pclk", "gclk";
942 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>;
943 assigned-parrents = <&pmc PMC_TYPE_GCK 55>;
944 status = "disabled";
945 };
947 can1: can@fc050000 {
948 compatible = "bosch,m_can";
949 reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
950 reg-names = "m_can", "message_ram";
951 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
952 <65 IRQ_TYPE_LEVEL_HIGH 7>;
953 interrupt-names = "int0", "int1";
954 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
955 clock-names = "hclk", "cclk";
956 assigned-clocks = <&pmc PMC_TYPE_GCK 57>;
957 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
958 assigned-clock-rates = <40000000>;
959 bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
960 status = "disabled";
961 };
963 sfrbu: sfr@fc05c000 {
964 compatible = "atmel,sama5d2-sfrbu", "syscon";
965 reg = <0xfc05c000 0x20>;
966 };
968 chipid@fc069000 {
969 compatible = "atmel,sama5d2-chipid";
970 reg = <0xfc069000 0x8>;
971 };
972 };
973 };
974 };