| blob | 7c36c37260a413f297c358aae75319dac10f4720 |
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2014 STMicroelectronics Limited.
4 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
5 */
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-resets.h>
10 #include <dt-bindings/interrupt-controller/irq-st.h>
11 / {
12 #address-cells = <1>;
13 #size-cells = <1>;
15 reserved-memory {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges;
20 gp0_reserved: rproc@45000000 {
21 compatible = "shared-dma-pool";
22 reg = <0x45000000 0x00400000>;
23 no-map;
24 };
26 delta_reserved: rproc@44000000 {
27 compatible = "shared-dma-pool";
28 reg = <0x44000000 0x01000000>;
29 no-map;
30 };
31 };
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36 cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a9";
39 reg = <0>;
41 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
42 cpu-release-addr = <0x94100A4>;
44 /* kHz uV */
45 operating-points = <1500000 0
46 1200000 0
47 800000 0
48 500000 0>;
50 clocks = <&clk_m_a9>;
51 clock-names = "cpu";
52 clock-latency = <100000>;
53 cpu0-supply = <&pwm_regulator>;
54 st,syscfg = <&syscfg_core 0x8e0>;
55 };
56 cpu@1 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a9";
59 reg = <1>;
61 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
62 cpu-release-addr = <0x94100A4>;
64 /* kHz uV */
65 operating-points = <1500000 0
66 1200000 0
67 800000 0
68 500000 0>;
69 };
70 };
72 intc: interrupt-controller@8761000 {
73 compatible = "arm,cortex-a9-gic";
74 #interrupt-cells = <3>;
75 interrupt-controller;
76 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
77 };
79 scu@8760000 {
80 compatible = "arm,cortex-a9-scu";
81 reg = <0x08760000 0x1000>;
82 };
84 timer@8760200 {
85 interrupt-parent = <&intc>;
86 compatible = "arm,cortex-a9-global-timer";
87 reg = <0x08760200 0x100>;
88 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&arm_periph_clk>;
90 };
92 l2: cache-controller@8762000 {
93 compatible = "arm,pl310-cache";
94 reg = <0x08762000 0x1000>;
95 arm,data-latency = <3 3 3>;
96 arm,tag-latency = <2 2 2>;
97 cache-unified;
98 cache-level = <2>;
99 };
101 arm-pmu {
102 interrupt-parent = <&intc>;
103 compatible = "arm,cortex-a9-pmu";
104 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
105 };
107 pwm_regulator: pwm-regulator {
108 compatible = "pwm-regulator";
109 pwms = <&pwm1 3 8448>;
110 regulator-name = "CPU_1V0_AVS";
111 regulator-min-microvolt = <784000>;
112 regulator-max-microvolt = <1299000>;
113 regulator-always-on;
114 max-duty-cycle = <255>;
115 status = "okay";
116 };
118 soc {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 interrupt-parent = <&intc>;
122 ranges;
123 compatible = "simple-bus";
125 restart: restart-controller@0 {
126 compatible = "st,stih407-restart";
127 reg = <0 0>;
128 st,syscfg = <&syscfg_sbc_reg>;
129 status = "okay";
130 };
132 powerdown: powerdown-controller@0 {
133 compatible = "st,stih407-powerdown";
134 reg = <0 0>;
135 #reset-cells = <1>;
136 };
138 softreset: softreset-controller@0 {
139 compatible = "st,stih407-softreset";
140 reg = <0 0>;
141 #reset-cells = <1>;
142 };
144 picophyreset: picophyreset-controller@0 {
145 compatible = "st,stih407-picophyreset";
146 reg = <0 0>;
147 #reset-cells = <1>;
148 };
150 syscfg_sbc: sbc-syscfg@9620000 {
151 compatible = "st,stih407-sbc-syscfg", "syscon";
152 reg = <0x9620000 0x1000>;
153 };
155 syscfg_front: front-syscfg@9280000 {
156 compatible = "st,stih407-front-syscfg", "syscon";
157 reg = <0x9280000 0x1000>;
158 };
160 syscfg_rear: rear-syscfg@9290000 {
161 compatible = "st,stih407-rear-syscfg", "syscon";
162 reg = <0x9290000 0x1000>;
163 };
165 syscfg_flash: flash-syscfg@92a0000 {
166 compatible = "st,stih407-flash-syscfg", "syscon";
167 reg = <0x92a0000 0x1000>;
168 };
170 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
171 compatible = "st,stih407-sbc-reg-syscfg", "syscon";
172 reg = <0x9600000 0x1000>;
173 };
175 syscfg_core: core-syscfg@92b0000 {
176 compatible = "st,stih407-core-syscfg", "syscon";
177 reg = <0x92b0000 0x1000>;
179 sti_sasg_codec: sti-sasg-codec {
180 compatible = "st,stih407-sas-codec";
181 #sound-dai-cells = <1>;
182 status = "disabled";
183 st,syscfg = <&syscfg_core>;
184 };
185 };
187 syscfg_lpm: lpm-syscfg@94b5100 {
188 compatible = "st,stih407-lpm-syscfg", "syscon";
189 reg = <0x94b5100 0x1000>;
190 };
192 irq-syscfg@0 {
193 compatible = "st,stih407-irq-syscfg";
194 reg = <0 0>;
195 st,syscfg = <&syscfg_core>;
196 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
197 <ST_IRQ_SYSCFG_PMU_1>;
198 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
199 <ST_IRQ_SYSCFG_DISABLED>;
200 };
202 /* Display */
203 vtg_main: sti-vtg-main@8d02800 {
204 compatible = "st,vtg";
205 reg = <0x8d02800 0x200>;
206 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
207 };
209 vtg_aux: sti-vtg-aux@8d00200 {
210 compatible = "st,vtg";
211 reg = <0x8d00200 0x100>;
212 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
213 };
215 serial@9830000 {
216 compatible = "st,asc";
217 reg = <0x9830000 0x2c>;
218 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
220 /* Pinctrl moved out to a per-board configuration */
222 status = "disabled";
223 };
225 serial@9831000 {
226 compatible = "st,asc";
227 reg = <0x9831000 0x2c>;
228 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_serial1>;
231 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
233 status = "disabled";
234 };
236 serial@9832000 {
237 compatible = "st,asc";
238 reg = <0x9832000 0x2c>;
239 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_serial2>;
242 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
244 status = "disabled";
245 };
247 /* SBC_ASC0 - UART10 */
248 sbc_serial0: serial@9530000 {
249 compatible = "st,asc";
250 reg = <0x9530000 0x2c>;
251 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_sbc_serial0>;
254 clocks = <&clk_sysin>;
256 status = "disabled";
257 };
259 serial@9531000 {
260 compatible = "st,asc";
261 reg = <0x9531000 0x2c>;
262 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_sbc_serial1>;
265 clocks = <&clk_sysin>;
267 status = "disabled";
268 };
270 i2c@9840000 {
271 compatible = "st,comms-ssc4-i2c";
272 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
273 reg = <0x9840000 0x110>;
274 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
275 clock-names = "ssc";
276 clock-frequency = <400000>;
277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_i2c0_default>;
279 #address-cells = <1>;
280 #size-cells = <0>;
282 status = "disabled";
283 };
285 i2c@9841000 {
286 compatible = "st,comms-ssc4-i2c";
287 reg = <0x9841000 0x110>;
288 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
290 clock-names = "ssc";
291 clock-frequency = <400000>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_i2c1_default>;
294 #address-cells = <1>;
295 #size-cells = <0>;
297 status = "disabled";
298 };
300 i2c@9842000 {
301 compatible = "st,comms-ssc4-i2c";
302 reg = <0x9842000 0x110>;
303 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
305 clock-names = "ssc";
306 clock-frequency = <400000>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_i2c2_default>;
309 #address-cells = <1>;
310 #size-cells = <0>;
312 status = "disabled";
313 };
315 i2c@9843000 {
316 compatible = "st,comms-ssc4-i2c";
317 reg = <0x9843000 0x110>;
318 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
320 clock-names = "ssc";
321 clock-frequency = <400000>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&pinctrl_i2c3_default>;
324 #address-cells = <1>;
325 #size-cells = <0>;
327 status = "disabled";
328 };
330 i2c@9844000 {
331 compatible = "st,comms-ssc4-i2c";
332 reg = <0x9844000 0x110>;
333 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
335 clock-names = "ssc";
336 clock-frequency = <400000>;
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_i2c4_default>;
339 #address-cells = <1>;
340 #size-cells = <0>;
342 status = "disabled";
343 };
345 i2c@9845000 {
346 compatible = "st,comms-ssc4-i2c";
347 reg = <0x9845000 0x110>;
348 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
350 clock-names = "ssc";
351 clock-frequency = <400000>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&pinctrl_i2c5_default>;
354 #address-cells = <1>;
355 #size-cells = <0>;
357 status = "disabled";
358 };
361 /* SSCs on SBC */
362 i2c@9540000 {
363 compatible = "st,comms-ssc4-i2c";
364 reg = <0x9540000 0x110>;
365 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&clk_sysin>;
367 clock-names = "ssc";
368 clock-frequency = <400000>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_i2c10_default>;
371 #address-cells = <1>;
372 #size-cells = <0>;
374 status = "disabled";
375 };
377 i2c@9541000 {
378 compatible = "st,comms-ssc4-i2c";
379 reg = <0x9541000 0x110>;
380 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&clk_sysin>;
382 clock-names = "ssc";
383 clock-frequency = <400000>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_i2c11_default>;
386 #address-cells = <1>;
387 #size-cells = <0>;
389 status = "disabled";
390 };
392 usb2_picophy0: phy1@0 {
393 compatible = "st,stih407-usb2-phy";
394 reg = <0 0>;
395 #phy-cells = <0>;
396 st,syscfg = <&syscfg_core 0x100 0xf4>;
397 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
398 <&picophyreset STIH407_PICOPHY2_RESET>;
399 reset-names = "global", "port";
400 };
402 miphy28lp_phy: miphy28lp@0 {
403 compatible = "st,miphy28lp-phy";
404 st,syscfg = <&syscfg_core>;
405 #address-cells = <1>;
406 #size-cells = <1>;
407 ranges;
408 reg = <0 0>;
410 phy_port0: port@9b22000 {
411 reg = <0x9b22000 0xff>,
412 <0x9b09000 0xff>,
413 <0x9b04000 0xff>;
414 reg-names = "sata-up",
415 "pcie-up",
416 "pipew";
418 st,syscfg = <0x114 0x818 0xe0 0xec>;
419 #phy-cells = <1>;
421 reset-names = "miphy-sw-rst";
422 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
423 };
425 phy_port1: port@9b2a000 {
426 reg = <0x9b2a000 0xff>,
427 <0x9b19000 0xff>,
428 <0x9b14000 0xff>;
429 reg-names = "sata-up",
430 "pcie-up",
431 "pipew";
433 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
435 #phy-cells = <1>;
437 reset-names = "miphy-sw-rst";
438 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
439 };
441 phy_port2: port@8f95000 {
442 reg = <0x8f95000 0xff>,
443 <0x8f90000 0xff>;
444 reg-names = "pipew",
445 "usb3-up";
447 st,syscfg = <0x11c 0x820>;
449 #phy-cells = <1>;
451 reset-names = "miphy-sw-rst";
452 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
453 };
454 };
456 spi@9840000 {
457 compatible = "st,comms-ssc4-spi";
458 reg = <0x9840000 0x110>;
459 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
461 clock-names = "ssc";
462 pinctrl-0 = <&pinctrl_spi0_default>;
463 pinctrl-names = "default";
464 #address-cells = <1>;
465 #size-cells = <0>;
467 status = "disabled";
468 };
470 spi@9841000 {
471 compatible = "st,comms-ssc4-spi";
472 reg = <0x9841000 0x110>;
473 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
475 clock-names = "ssc";
476 pinctrl-names = "default";
477 pinctrl-0 = <&pinctrl_spi1_default>;
478 #address-cells = <1>;
479 #size-cells = <0>;
481 status = "disabled";
482 };
484 spi@9842000 {
485 compatible = "st,comms-ssc4-spi";
486 reg = <0x9842000 0x110>;
487 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
489 clock-names = "ssc";
490 pinctrl-names = "default";
491 pinctrl-0 = <&pinctrl_spi2_default>;
492 #address-cells = <1>;
493 #size-cells = <0>;
495 status = "disabled";
496 };
498 spi@9843000 {
499 compatible = "st,comms-ssc4-spi";
500 reg = <0x9843000 0x110>;
501 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
503 clock-names = "ssc";
504 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_spi3_default>;
506 #address-cells = <1>;
507 #size-cells = <0>;
509 status = "disabled";
510 };
512 spi@9844000 {
513 compatible = "st,comms-ssc4-spi";
514 reg = <0x9844000 0x110>;
515 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
517 clock-names = "ssc";
518 pinctrl-names = "default";
519 pinctrl-0 = <&pinctrl_spi4_default>;
520 #address-cells = <1>;
521 #size-cells = <0>;
523 status = "disabled";
524 };
526 /* SBC SSC */
527 spi@9540000 {
528 compatible = "st,comms-ssc4-spi";
529 reg = <0x9540000 0x110>;
530 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&clk_sysin>;
532 clock-names = "ssc";
533 pinctrl-names = "default";
534 pinctrl-0 = <&pinctrl_spi10_default>;
535 #address-cells = <1>;
536 #size-cells = <0>;
538 status = "disabled";
539 };
541 spi@9541000 {
542 compatible = "st,comms-ssc4-spi";
543 reg = <0x9541000 0x110>;
544 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&clk_sysin>;
546 clock-names = "ssc";
547 pinctrl-names = "default";
548 pinctrl-0 = <&pinctrl_spi11_default>;
549 #address-cells = <1>;
550 #size-cells = <0>;
552 status = "disabled";
553 };
555 spi@9542000 {
556 compatible = "st,comms-ssc4-spi";
557 reg = <0x9542000 0x110>;
558 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&clk_sysin>;
560 clock-names = "ssc";
561 pinctrl-names = "default";
562 pinctrl-0 = <&pinctrl_spi12_default>;
563 #address-cells = <1>;
564 #size-cells = <0>;
566 status = "disabled";
567 };
569 mmc0: sdhci@9060000 {
570 compatible = "st,sdhci-stih407", "st,sdhci";
571 status = "disabled";
572 reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
573 reg-names = "mmc", "top-mmc-delay";
574 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
575 interrupt-names = "mmcirq";
576 pinctrl-names = "default";
577 pinctrl-0 = <&pinctrl_mmc0>;
578 clock-names = "mmc", "icn";
579 clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
580 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
581 bus-width = <8>;
582 };
584 mmc1: sdhci@9080000 {
585 compatible = "st,sdhci-stih407", "st,sdhci";
586 status = "disabled";
587 reg = <0x09080000 0x7ff>;
588 reg-names = "mmc";
589 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
590 interrupt-names = "mmcirq";
591 pinctrl-names = "default";
592 pinctrl-0 = <&pinctrl_sd1>;
593 clock-names = "mmc", "icn";
594 clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
595 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
596 resets = <&softreset STIH407_MMC1_SOFTRESET>;
597 bus-width = <4>;
598 };
600 /* Watchdog and Real-Time Clock */
601 lpc@8787000 {
602 compatible = "st,stih407-lpc";
603 reg = <0x8787000 0x1000>;
604 interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
605 clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
606 timeout-sec = <120>;
607 st,syscfg = <&syscfg_core>;
608 st,lpc-mode = <ST_LPC_MODE_WDT>;
609 };
611 lpc@8788000 {
612 compatible = "st,stih407-lpc";
613 reg = <0x8788000 0x1000>;
614 interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
615 clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
616 st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
617 };
619 sata0: sata@9b20000 {
620 compatible = "st,ahci";
621 reg = <0x9b20000 0x1000>;
623 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
624 interrupt-names = "hostc";
626 phys = <&phy_port0 PHY_TYPE_SATA>;
627 phy-names = "ahci_phy";
629 resets = <&powerdown STIH407_SATA0_POWERDOWN>,
630 <&softreset STIH407_SATA0_SOFTRESET>,
631 <&softreset STIH407_SATA0_PWR_SOFTRESET>;
632 reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
634 clock-names = "ahci_clk";
635 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
637 ports-implemented = <0x1>;
639 status = "disabled";
640 };
642 sata1: sata@9b28000 {
643 compatible = "st,ahci";
644 reg = <0x9b28000 0x1000>;
646 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
647 interrupt-names = "hostc";
649 phys = <&phy_port1 PHY_TYPE_SATA>;
650 phy-names = "ahci_phy";
652 resets = <&powerdown STIH407_SATA1_POWERDOWN>,
653 <&softreset STIH407_SATA1_SOFTRESET>,
654 <&softreset STIH407_SATA1_PWR_SOFTRESET>;
655 reset-names = "pwr-dwn",
656 "sw-rst",
657 "pwr-rst";
659 clock-names = "ahci_clk";
660 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
662 ports-implemented = <0x1>;
664 status = "disabled";
665 };
668 st_dwc3: dwc3@8f94000 {
669 compatible = "st,stih407-dwc3";
670 reg = <0x08f94000 0x1000>, <0x110 0x4>;
671 reg-names = "reg-glue", "syscfg-reg";
672 st,syscfg = <&syscfg_core>;
673 resets = <&powerdown STIH407_USB3_POWERDOWN>,
674 <&softreset STIH407_MIPHY2_SOFTRESET>;
675 reset-names = "powerdown", "softreset";
676 #address-cells = <1>;
677 #size-cells = <1>;
678 pinctrl-names = "default";
679 pinctrl-0 = <&pinctrl_usb3>;
680 ranges;
682 status = "disabled";
684 dwc3: dwc3@9900000 {
685 compatible = "snps,dwc3";
686 reg = <0x09900000 0x100000>;
687 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
688 dr_mode = "host";
689 phy-names = "usb2-phy", "usb3-phy";
690 phys = <&usb2_picophy0>,
691 <&phy_port2 PHY_TYPE_USB3>;
692 snps,dis_u3_susphy_quirk;
693 };
694 };
696 /* COMMS PWM Module */
697 pwm0: pwm@9810000 {
698 compatible = "st,sti-pwm";
699 #pwm-cells = <2>;
700 reg = <0x9810000 0x68>;
701 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
702 pinctrl-names = "default";
703 pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
704 clock-names = "pwm";
705 clocks = <&clk_sysin>;
706 st,pwm-num-chan = <1>;
708 status = "disabled";
709 };
711 /* SBC PWM Module */
712 pwm1: pwm@9510000 {
713 compatible = "st,sti-pwm";
714 #pwm-cells = <2>;
715 reg = <0x9510000 0x68>;
716 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
717 pinctrl-names = "default";
718 pinctrl-0 = <&pinctrl_pwm1_chan0_default
719 &pinctrl_pwm1_chan1_default
720 &pinctrl_pwm1_chan2_default
721 &pinctrl_pwm1_chan3_default>;
722 clock-names = "pwm";
723 clocks = <&clk_sysin>;
724 st,pwm-num-chan = <4>;
726 status = "disabled";
727 };
729 rng10: rng@8a89000 {
730 compatible = "st,rng";
731 reg = <0x08a89000 0x1000>;
732 clocks = <&clk_sysin>;
733 status = "okay";
734 };
736 rng11: rng@8a8a000 {
737 compatible = "st,rng";
738 reg = <0x08a8a000 0x1000>;
739 clocks = <&clk_sysin>;
740 status = "okay";
741 };
743 ethernet0: dwmac@9630000 {
744 device_type = "network";
745 status = "disabled";
746 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
747 reg = <0x9630000 0x8000>, <0x80 0x4>;
748 reg-names = "stmmaceth", "sti-ethconf";
750 st,syscon = <&syscfg_sbc_reg 0x80>;
751 st,gmac_en;
752 resets = <&softreset STIH407_ETH1_SOFTRESET>;
753 reset-names = "stmmaceth";
755 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
757 interrupt-names = "macirq", "eth_wake_irq";
759 /* DMA Bus Mode */
760 snps,pbl = <8>;
762 pinctrl-names = "default";
763 pinctrl-0 = <&pinctrl_rgmii1>;
765 clock-names = "stmmaceth", "sti-ethclk";
766 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
767 <&clk_s_c0_flexgen CLK_ETH_PHY>;
768 };
770 rng10: rng@8a89000 {
771 compatible = "st,rng";
772 reg = <0x08a89000 0x1000>;
773 clocks = <&clk_sysin>;
774 status = "okay";
775 };
777 rng11: rng@8a8a000 {
778 compatible = "st,rng";
779 reg = <0x08a8a000 0x1000>;
780 clocks = <&clk_sysin>;
781 status = "okay";
782 };
784 mailbox0: mailbox@8f00000 {
785 compatible = "st,stih407-mailbox";
786 reg = <0x8f00000 0x1000>;
787 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
788 #mbox-cells = <2>;
789 mbox-name = "a9";
790 status = "okay";
791 };
793 mailbox1: mailbox@8f01000 {
794 compatible = "st,stih407-mailbox";
795 reg = <0x8f01000 0x1000>;
796 #mbox-cells = <2>;
797 mbox-name = "st231_gp_1";
798 status = "okay";
799 };
801 mailbox2: mailbox@8f02000 {
802 compatible = "st,stih407-mailbox";
803 reg = <0x8f02000 0x1000>;
804 #mbox-cells = <2>;
805 mbox-name = "st231_gp_0";
806 status = "okay";
807 };
809 mailbox3: mailbox@8f03000 {
810 compatible = "st,stih407-mailbox";
811 reg = <0x8f03000 0x1000>;
812 #mbox-cells = <2>;
813 mbox-name = "st231_audio_video";
814 status = "okay";
815 };
817 st231_gp0: st231-gp0@0 {
818 compatible = "st,st231-rproc";
819 reg = <0 0>;
820 memory-region = <&gp0_reserved>;
821 resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
822 reset-names = "sw_reset";
823 clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
824 clock-frequency = <600000000>;
825 st,syscfg = <&syscfg_core 0x22c>;
826 #mbox-cells = <1>;
827 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
828 mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
829 };
831 st231_delta: st231-delta@0 {
832 compatible = "st,st231-rproc";
833 reg = <0 0>;
834 memory-region = <&delta_reserved>;
835 resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
836 reset-names = "sw_reset";
837 clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
838 clock-frequency = <600000000>;
839 st,syscfg = <&syscfg_core 0x224>;
840 #mbox-cells = <1>;
841 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
842 mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
843 };
845 /* fdma audio */
846 fdma0: dma-controller@8e20000 {
847 compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
848 reg = <0x8e20000 0x8000>,
849 <0x8e30000 0x3000>,
850 <0x8e37000 0x1000>,
851 <0x8e38000 0x8000>;
852 reg-names = "slimcore", "dmem", "peripherals", "imem";
853 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
854 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
855 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
856 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
857 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
858 dma-channels = <16>;
859 #dma-cells = <3>;
860 };
862 /* fdma app */
863 fdma1: dma-controller@8e40000 {
864 compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc";
865 reg = <0x8e40000 0x8000>,
866 <0x8e50000 0x3000>,
867 <0x8e57000 0x1000>,
868 <0x8e58000 0x8000>;
869 reg-names = "slimcore", "dmem", "peripherals", "imem";
870 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
871 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
872 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
873 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
875 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
876 dma-channels = <16>;
877 #dma-cells = <3>;
879 status = "disabled";
880 };
882 /* fdma free running */
883 fdma2: dma-controller@8e60000 {
884 compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc";
885 reg = <0x8e60000 0x8000>,
886 <0x8e70000 0x3000>,
887 <0x8e77000 0x1000>,
888 <0x8e78000 0x8000>;
889 reg-names = "slimcore", "dmem", "peripherals", "imem";
890 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
891 dma-channels = <16>;
892 #dma-cells = <3>;
893 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
894 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
895 <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
896 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
898 status = "disabled";
899 };
901 sti_uni_player0: sti-uni-player@8d80000 {
902 compatible = "st,stih407-uni-player-hdmi";
903 #sound-dai-cells = <0>;
904 st,syscfg = <&syscfg_core>;
905 clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
906 assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>;
907 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
908 assigned-clock-rates = <50000000>;
909 reg = <0x8d80000 0x158>;
910 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
911 dmas = <&fdma0 2 0 1>;
912 dma-names = "tx";
914 status = "disabled";
915 };
917 sti_uni_player1: sti-uni-player@8d81000 {
918 compatible = "st,stih407-uni-player-pcm-out";
919 #sound-dai-cells = <0>;
920 st,syscfg = <&syscfg_core>;
921 clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
922 assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
923 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
924 assigned-clock-rates = <50000000>;
925 reg = <0x8d81000 0x158>;
926 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
927 dmas = <&fdma0 3 0 1>;
928 dma-names = "tx";
930 status = "disabled";
931 };
933 sti_uni_player2: sti-uni-player@8d82000 {
934 compatible = "st,stih407-uni-player-dac";
935 #sound-dai-cells = <0>;
936 st,syscfg = <&syscfg_core>;
937 clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
938 assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>;
939 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
940 assigned-clock-rates = <50000000>;
941 reg = <0x8d82000 0x158>;
942 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
943 dmas = <&fdma0 4 0 1>;
944 dma-names = "tx";
946 status = "disabled";
947 };
949 sti_uni_player3: sti-uni-player@8d85000 {
950 compatible = "st,stih407-uni-player-spdif";
951 #sound-dai-cells = <0>;
952 st,syscfg = <&syscfg_core>;
953 clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
954 assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>;
955 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
956 assigned-clock-rates = <50000000>;
957 reg = <0x8d85000 0x158>;
958 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
959 dmas = <&fdma0 7 0 1>;
960 dma-names = "tx";
962 status = "disabled";
963 };
965 sti_uni_reader0: sti-uni-reader@8d83000 {
966 compatible = "st,stih407-uni-reader-pcm_in";
967 #sound-dai-cells = <0>;
968 st,syscfg = <&syscfg_core>;
969 reg = <0x8d83000 0x158>;
970 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
971 dmas = <&fdma0 5 0 1>;
972 dma-names = "rx";
974 status = "disabled";
975 };
977 sti_uni_reader1: sti-uni-reader@8d84000 {
978 compatible = "st,stih407-uni-reader-hdmi";
979 #sound-dai-cells = <0>;
980 st,syscfg = <&syscfg_core>;
981 reg = <0x8d84000 0x158>;
982 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
983 dmas = <&fdma0 6 0 1>;
984 dma-names = "rx";
986 status = "disabled";
987 };
989 delta0@0 {
990 compatible = "st,st-delta";
991 reg = <0 0>;
992 clock-names = "delta",
993 "delta-st231",
994 "delta-flash-promip";
995 clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
996 <&clk_s_c0_flexgen CLK_ST231_DMU>,
997 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
998 };
999 };
1000 };