| blob | fb41d0778b005dd155505a0a92e4c82a4284b504 |
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
10 / {
11 #address-cells = <1>;
12 #size-cells = <1>;
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a7";
20 device_type = "cpu";
21 reg = <0>;
22 };
23 };
25 psci {
26 compatible = "arm,psci";
27 method = "smc";
28 cpu_off = <0x84000002>;
29 cpu_on = <0x84000003>;
30 };
32 intc: interrupt-controller@a0021000 {
33 compatible = "arm,cortex-a7-gic";
34 #interrupt-cells = <3>;
35 interrupt-controller;
36 reg = <0xa0021000 0x1000>,
37 <0xa0022000 0x2000>;
38 };
40 timer {
41 compatible = "arm,armv7-timer";
42 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
43 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
44 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
45 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
46 interrupt-parent = <&intc>;
47 };
49 clocks {
50 clk_hse: clk-hse {
51 #clock-cells = <0>;
52 compatible = "fixed-clock";
53 clock-frequency = <24000000>;
54 };
56 clk_hsi: clk-hsi {
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <64000000>;
60 };
62 clk_lse: clk-lse {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <32768>;
66 };
68 clk_lsi: clk-lsi {
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-frequency = <32000>;
72 };
74 clk_csi: clk-csi {
75 #clock-cells = <0>;
76 compatible = "fixed-clock";
77 clock-frequency = <4000000>;
78 };
79 };
81 thermal-zones {
82 cpu_thermal: cpu-thermal {
83 polling-delay-passive = <0>;
84 polling-delay = <0>;
85 thermal-sensors = <&dts>;
87 trips {
88 cpu_alert1: cpu-alert1 {
89 temperature = <85000>;
90 hysteresis = <0>;
91 type = "passive";
92 };
94 cpu-crit {
95 temperature = <120000>;
96 hysteresis = <0>;
97 type = "critical";
98 };
99 };
101 cooling-maps {
102 };
103 };
104 };
106 booster: regulator-booster {
107 compatible = "st,stm32mp1-booster";
108 st,syscfg = <&syscfg>;
109 status = "disabled";
110 };
112 soc {
113 compatible = "simple-bus";
114 #address-cells = <1>;
115 #size-cells = <1>;
116 interrupt-parent = <&intc>;
117 ranges;
119 timers2: timer@40000000 {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 compatible = "st,stm32-timers";
123 reg = <0x40000000 0x400>;
124 clocks = <&rcc TIM2_K>;
125 clock-names = "int";
126 dmas = <&dmamux1 18 0x400 0x1>,
127 <&dmamux1 19 0x400 0x1>,
128 <&dmamux1 20 0x400 0x1>,
129 <&dmamux1 21 0x400 0x1>,
130 <&dmamux1 22 0x400 0x1>;
131 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
132 status = "disabled";
134 pwm {
135 compatible = "st,stm32-pwm";
136 #pwm-cells = <3>;
137 status = "disabled";
138 };
140 timer@1 {
141 compatible = "st,stm32h7-timer-trigger";
142 reg = <1>;
143 status = "disabled";
144 };
146 counter {
147 compatible = "st,stm32-timer-counter";
148 status = "disabled";
149 };
150 };
152 timers3: timer@40001000 {
153 #address-cells = <1>;
154 #size-cells = <0>;
155 compatible = "st,stm32-timers";
156 reg = <0x40001000 0x400>;
157 clocks = <&rcc TIM3_K>;
158 clock-names = "int";
159 dmas = <&dmamux1 23 0x400 0x1>,
160 <&dmamux1 24 0x400 0x1>,
161 <&dmamux1 25 0x400 0x1>,
162 <&dmamux1 26 0x400 0x1>,
163 <&dmamux1 27 0x400 0x1>,
164 <&dmamux1 28 0x400 0x1>;
165 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
166 status = "disabled";
168 pwm {
169 compatible = "st,stm32-pwm";
170 #pwm-cells = <3>;
171 status = "disabled";
172 };
174 timer@2 {
175 compatible = "st,stm32h7-timer-trigger";
176 reg = <2>;
177 status = "disabled";
178 };
180 counter {
181 compatible = "st,stm32-timer-counter";
182 status = "disabled";
183 };
184 };
186 timers4: timer@40002000 {
187 #address-cells = <1>;
188 #size-cells = <0>;
189 compatible = "st,stm32-timers";
190 reg = <0x40002000 0x400>;
191 clocks = <&rcc TIM4_K>;
192 clock-names = "int";
193 dmas = <&dmamux1 29 0x400 0x1>,
194 <&dmamux1 30 0x400 0x1>,
195 <&dmamux1 31 0x400 0x1>,
196 <&dmamux1 32 0x400 0x1>;
197 dma-names = "ch1", "ch2", "ch3", "ch4";
198 status = "disabled";
200 pwm {
201 compatible = "st,stm32-pwm";
202 #pwm-cells = <3>;
203 status = "disabled";
204 };
206 timer@3 {
207 compatible = "st,stm32h7-timer-trigger";
208 reg = <3>;
209 status = "disabled";
210 };
212 counter {
213 compatible = "st,stm32-timer-counter";
214 status = "disabled";
215 };
216 };
218 timers5: timer@40003000 {
219 #address-cells = <1>;
220 #size-cells = <0>;
221 compatible = "st,stm32-timers";
222 reg = <0x40003000 0x400>;
223 clocks = <&rcc TIM5_K>;
224 clock-names = "int";
225 dmas = <&dmamux1 55 0x400 0x1>,
226 <&dmamux1 56 0x400 0x1>,
227 <&dmamux1 57 0x400 0x1>,
228 <&dmamux1 58 0x400 0x1>,
229 <&dmamux1 59 0x400 0x1>,
230 <&dmamux1 60 0x400 0x1>;
231 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
232 status = "disabled";
234 pwm {
235 compatible = "st,stm32-pwm";
236 #pwm-cells = <3>;
237 status = "disabled";
238 };
240 timer@4 {
241 compatible = "st,stm32h7-timer-trigger";
242 reg = <4>;
243 status = "disabled";
244 };
246 counter {
247 compatible = "st,stm32-timer-counter";
248 status = "disabled";
249 };
250 };
252 timers6: timer@40004000 {
253 #address-cells = <1>;
254 #size-cells = <0>;
255 compatible = "st,stm32-timers";
256 reg = <0x40004000 0x400>;
257 clocks = <&rcc TIM6_K>;
258 clock-names = "int";
259 dmas = <&dmamux1 69 0x400 0x1>;
260 dma-names = "up";
261 status = "disabled";
263 timer@5 {
264 compatible = "st,stm32h7-timer-trigger";
265 reg = <5>;
266 status = "disabled";
267 };
268 };
270 timers7: timer@40005000 {
271 #address-cells = <1>;
272 #size-cells = <0>;
273 compatible = "st,stm32-timers";
274 reg = <0x40005000 0x400>;
275 clocks = <&rcc TIM7_K>;
276 clock-names = "int";
277 dmas = <&dmamux1 70 0x400 0x1>;
278 dma-names = "up";
279 status = "disabled";
281 timer@6 {
282 compatible = "st,stm32h7-timer-trigger";
283 reg = <6>;
284 status = "disabled";
285 };
286 };
288 timers12: timer@40006000 {
289 #address-cells = <1>;
290 #size-cells = <0>;
291 compatible = "st,stm32-timers";
292 reg = <0x40006000 0x400>;
293 clocks = <&rcc TIM12_K>;
294 clock-names = "int";
295 status = "disabled";
297 pwm {
298 compatible = "st,stm32-pwm";
299 #pwm-cells = <3>;
300 status = "disabled";
301 };
303 timer@11 {
304 compatible = "st,stm32h7-timer-trigger";
305 reg = <11>;
306 status = "disabled";
307 };
308 };
310 timers13: timer@40007000 {
311 #address-cells = <1>;
312 #size-cells = <0>;
313 compatible = "st,stm32-timers";
314 reg = <0x40007000 0x400>;
315 clocks = <&rcc TIM13_K>;
316 clock-names = "int";
317 status = "disabled";
319 pwm {
320 compatible = "st,stm32-pwm";
321 #pwm-cells = <3>;
322 status = "disabled";
323 };
325 timer@12 {
326 compatible = "st,stm32h7-timer-trigger";
327 reg = <12>;
328 status = "disabled";
329 };
330 };
332 timers14: timer@40008000 {
333 #address-cells = <1>;
334 #size-cells = <0>;
335 compatible = "st,stm32-timers";
336 reg = <0x40008000 0x400>;
337 clocks = <&rcc TIM14_K>;
338 clock-names = "int";
339 status = "disabled";
341 pwm {
342 compatible = "st,stm32-pwm";
343 #pwm-cells = <3>;
344 status = "disabled";
345 };
347 timer@13 {
348 compatible = "st,stm32h7-timer-trigger";
349 reg = <13>;
350 status = "disabled";
351 };
352 };
354 lptimer1: timer@40009000 {
355 #address-cells = <1>;
356 #size-cells = <0>;
357 compatible = "st,stm32-lptimer";
358 reg = <0x40009000 0x400>;
359 clocks = <&rcc LPTIM1_K>;
360 clock-names = "mux";
361 status = "disabled";
363 pwm {
364 compatible = "st,stm32-pwm-lp";
365 #pwm-cells = <3>;
366 status = "disabled";
367 };
369 trigger@0 {
370 compatible = "st,stm32-lptimer-trigger";
371 reg = <0>;
372 status = "disabled";
373 };
375 counter {
376 compatible = "st,stm32-lptimer-counter";
377 status = "disabled";
378 };
379 };
381 spi2: spi@4000b000 {
382 #address-cells = <1>;
383 #size-cells = <0>;
384 compatible = "st,stm32h7-spi";
385 reg = <0x4000b000 0x400>;
386 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&rcc SPI2_K>;
388 resets = <&rcc SPI2_R>;
389 dmas = <&dmamux1 39 0x400 0x05>,
390 <&dmamux1 40 0x400 0x05>;
391 dma-names = "rx", "tx";
392 status = "disabled";
393 };
395 i2s2: audio-controller@4000b000 {
396 compatible = "st,stm32h7-i2s";
397 #sound-dai-cells = <0>;
398 reg = <0x4000b000 0x400>;
399 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
400 dmas = <&dmamux1 39 0x400 0x01>,
401 <&dmamux1 40 0x400 0x01>;
402 dma-names = "rx", "tx";
403 status = "disabled";
404 };
406 spi3: spi@4000c000 {
407 #address-cells = <1>;
408 #size-cells = <0>;
409 compatible = "st,stm32h7-spi";
410 reg = <0x4000c000 0x400>;
411 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&rcc SPI3_K>;
413 resets = <&rcc SPI3_R>;
414 dmas = <&dmamux1 61 0x400 0x05>,
415 <&dmamux1 62 0x400 0x05>;
416 dma-names = "rx", "tx";
417 status = "disabled";
418 };
420 i2s3: audio-controller@4000c000 {
421 compatible = "st,stm32h7-i2s";
422 #sound-dai-cells = <0>;
423 reg = <0x4000c000 0x400>;
424 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
425 dmas = <&dmamux1 61 0x400 0x01>,
426 <&dmamux1 62 0x400 0x01>;
427 dma-names = "rx", "tx";
428 status = "disabled";
429 };
431 spdifrx: audio-controller@4000d000 {
432 compatible = "st,stm32h7-spdifrx";
433 #sound-dai-cells = <0>;
434 reg = <0x4000d000 0x400>;
435 clocks = <&rcc SPDIF_K>;
436 clock-names = "kclk";
437 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
438 dmas = <&dmamux1 93 0x400 0x01>,
439 <&dmamux1 94 0x400 0x01>;
440 dma-names = "rx", "rx-ctrl";
441 status = "disabled";
442 };
444 usart2: serial@4000e000 {
445 compatible = "st,stm32h7-uart";
446 reg = <0x4000e000 0x400>;
447 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&rcc USART2_K>;
449 status = "disabled";
450 };
452 usart3: serial@4000f000 {
453 compatible = "st,stm32h7-uart";
454 reg = <0x4000f000 0x400>;
455 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&rcc USART3_K>;
457 status = "disabled";
458 };
460 uart4: serial@40010000 {
461 compatible = "st,stm32h7-uart";
462 reg = <0x40010000 0x400>;
463 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&rcc UART4_K>;
465 status = "disabled";
466 };
468 uart5: serial@40011000 {
469 compatible = "st,stm32h7-uart";
470 reg = <0x40011000 0x400>;
471 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&rcc UART5_K>;
473 status = "disabled";
474 };
476 i2c1: i2c@40012000 {
477 compatible = "st,stm32f7-i2c";
478 reg = <0x40012000 0x400>;
479 interrupt-names = "event", "error";
480 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&rcc I2C1_K>;
483 resets = <&rcc I2C1_R>;
484 #address-cells = <1>;
485 #size-cells = <0>;
486 status = "disabled";
487 };
489 i2c2: i2c@40013000 {
490 compatible = "st,stm32f7-i2c";
491 reg = <0x40013000 0x400>;
492 interrupt-names = "event", "error";
493 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&rcc I2C2_K>;
496 resets = <&rcc I2C2_R>;
497 #address-cells = <1>;
498 #size-cells = <0>;
499 status = "disabled";
500 };
502 i2c3: i2c@40014000 {
503 compatible = "st,stm32f7-i2c";
504 reg = <0x40014000 0x400>;
505 interrupt-names = "event", "error";
506 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&rcc I2C3_K>;
509 resets = <&rcc I2C3_R>;
510 #address-cells = <1>;
511 #size-cells = <0>;
512 status = "disabled";
513 };
515 i2c5: i2c@40015000 {
516 compatible = "st,stm32f7-i2c";
517 reg = <0x40015000 0x400>;
518 interrupt-names = "event", "error";
519 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&rcc I2C5_K>;
522 resets = <&rcc I2C5_R>;
523 #address-cells = <1>;
524 #size-cells = <0>;
525 status = "disabled";
526 };
528 cec: cec@40016000 {
529 compatible = "st,stm32-cec";
530 reg = <0x40016000 0x400>;
531 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&rcc CEC_K>, <&clk_lse>;
533 clock-names = "cec", "hdmi-cec";
534 status = "disabled";
535 };
537 dac: dac@40017000 {
538 compatible = "st,stm32h7-dac-core";
539 reg = <0x40017000 0x400>;
540 clocks = <&rcc DAC12>;
541 clock-names = "pclk";
542 #address-cells = <1>;
543 #size-cells = <0>;
544 status = "disabled";
546 dac1: dac@1 {
547 compatible = "st,stm32-dac";
548 #io-channels-cells = <1>;
549 reg = <1>;
550 status = "disabled";
551 };
553 dac2: dac@2 {
554 compatible = "st,stm32-dac";
555 #io-channels-cells = <1>;
556 reg = <2>;
557 status = "disabled";
558 };
559 };
561 uart7: serial@40018000 {
562 compatible = "st,stm32h7-uart";
563 reg = <0x40018000 0x400>;
564 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&rcc UART7_K>;
566 status = "disabled";
567 };
569 uart8: serial@40019000 {
570 compatible = "st,stm32h7-uart";
571 reg = <0x40019000 0x400>;
572 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&rcc UART8_K>;
574 status = "disabled";
575 };
577 timers1: timer@44000000 {
578 #address-cells = <1>;
579 #size-cells = <0>;
580 compatible = "st,stm32-timers";
581 reg = <0x44000000 0x400>;
582 clocks = <&rcc TIM1_K>;
583 clock-names = "int";
584 dmas = <&dmamux1 11 0x400 0x1>,
585 <&dmamux1 12 0x400 0x1>,
586 <&dmamux1 13 0x400 0x1>,
587 <&dmamux1 14 0x400 0x1>,
588 <&dmamux1 15 0x400 0x1>,
589 <&dmamux1 16 0x400 0x1>,
590 <&dmamux1 17 0x400 0x1>;
591 dma-names = "ch1", "ch2", "ch3", "ch4",
592 "up", "trig", "com";
593 status = "disabled";
595 pwm {
596 compatible = "st,stm32-pwm";
597 #pwm-cells = <3>;
598 status = "disabled";
599 };
601 timer@0 {
602 compatible = "st,stm32h7-timer-trigger";
603 reg = <0>;
604 status = "disabled";
605 };
607 counter {
608 compatible = "st,stm32-timer-counter";
609 status = "disabled";
610 };
611 };
613 timers8: timer@44001000 {
614 #address-cells = <1>;
615 #size-cells = <0>;
616 compatible = "st,stm32-timers";
617 reg = <0x44001000 0x400>;
618 clocks = <&rcc TIM8_K>;
619 clock-names = "int";
620 dmas = <&dmamux1 47 0x400 0x1>,
621 <&dmamux1 48 0x400 0x1>,
622 <&dmamux1 49 0x400 0x1>,
623 <&dmamux1 50 0x400 0x1>,
624 <&dmamux1 51 0x400 0x1>,
625 <&dmamux1 52 0x400 0x1>,
626 <&dmamux1 53 0x400 0x1>;
627 dma-names = "ch1", "ch2", "ch3", "ch4",
628 "up", "trig", "com";
629 status = "disabled";
631 pwm {
632 compatible = "st,stm32-pwm";
633 #pwm-cells = <3>;
634 status = "disabled";
635 };
637 timer@7 {
638 compatible = "st,stm32h7-timer-trigger";
639 reg = <7>;
640 status = "disabled";
641 };
643 counter {
644 compatible = "st,stm32-timer-counter";
645 status = "disabled";
646 };
647 };
649 usart6: serial@44003000 {
650 compatible = "st,stm32h7-uart";
651 reg = <0x44003000 0x400>;
652 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&rcc USART6_K>;
654 status = "disabled";
655 };
657 spi1: spi@44004000 {
658 #address-cells = <1>;
659 #size-cells = <0>;
660 compatible = "st,stm32h7-spi";
661 reg = <0x44004000 0x400>;
662 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&rcc SPI1_K>;
664 resets = <&rcc SPI1_R>;
665 dmas = <&dmamux1 37 0x400 0x05>,
666 <&dmamux1 38 0x400 0x05>;
667 dma-names = "rx", "tx";
668 status = "disabled";
669 };
671 i2s1: audio-controller@44004000 {
672 compatible = "st,stm32h7-i2s";
673 #sound-dai-cells = <0>;
674 reg = <0x44004000 0x400>;
675 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
676 dmas = <&dmamux1 37 0x400 0x01>,
677 <&dmamux1 38 0x400 0x01>;
678 dma-names = "rx", "tx";
679 status = "disabled";
680 };
682 spi4: spi@44005000 {
683 #address-cells = <1>;
684 #size-cells = <0>;
685 compatible = "st,stm32h7-spi";
686 reg = <0x44005000 0x400>;
687 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&rcc SPI4_K>;
689 resets = <&rcc SPI4_R>;
690 dmas = <&dmamux1 83 0x400 0x05>,
691 <&dmamux1 84 0x400 0x05>;
692 dma-names = "rx", "tx";
693 status = "disabled";
694 };
696 timers15: timer@44006000 {
697 #address-cells = <1>;
698 #size-cells = <0>;
699 compatible = "st,stm32-timers";
700 reg = <0x44006000 0x400>;
701 clocks = <&rcc TIM15_K>;
702 clock-names = "int";
703 dmas = <&dmamux1 105 0x400 0x1>,
704 <&dmamux1 106 0x400 0x1>,
705 <&dmamux1 107 0x400 0x1>,
706 <&dmamux1 108 0x400 0x1>;
707 dma-names = "ch1", "up", "trig", "com";
708 status = "disabled";
710 pwm {
711 compatible = "st,stm32-pwm";
712 #pwm-cells = <3>;
713 status = "disabled";
714 };
716 timer@14 {
717 compatible = "st,stm32h7-timer-trigger";
718 reg = <14>;
719 status = "disabled";
720 };
721 };
723 timers16: timer@44007000 {
724 #address-cells = <1>;
725 #size-cells = <0>;
726 compatible = "st,stm32-timers";
727 reg = <0x44007000 0x400>;
728 clocks = <&rcc TIM16_K>;
729 clock-names = "int";
730 dmas = <&dmamux1 109 0x400 0x1>,
731 <&dmamux1 110 0x400 0x1>;
732 dma-names = "ch1", "up";
733 status = "disabled";
735 pwm {
736 compatible = "st,stm32-pwm";
737 #pwm-cells = <3>;
738 status = "disabled";
739 };
740 timer@15 {
741 compatible = "st,stm32h7-timer-trigger";
742 reg = <15>;
743 status = "disabled";
744 };
745 };
747 timers17: timer@44008000 {
748 #address-cells = <1>;
749 #size-cells = <0>;
750 compatible = "st,stm32-timers";
751 reg = <0x44008000 0x400>;
752 clocks = <&rcc TIM17_K>;
753 clock-names = "int";
754 dmas = <&dmamux1 111 0x400 0x1>,
755 <&dmamux1 112 0x400 0x1>;
756 dma-names = "ch1", "up";
757 status = "disabled";
759 pwm {
760 compatible = "st,stm32-pwm";
761 #pwm-cells = <3>;
762 status = "disabled";
763 };
765 timer@16 {
766 compatible = "st,stm32h7-timer-trigger";
767 reg = <16>;
768 status = "disabled";
769 };
770 };
772 spi5: spi@44009000 {
773 #address-cells = <1>;
774 #size-cells = <0>;
775 compatible = "st,stm32h7-spi";
776 reg = <0x44009000 0x400>;
777 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&rcc SPI5_K>;
779 resets = <&rcc SPI5_R>;
780 dmas = <&dmamux1 85 0x400 0x05>,
781 <&dmamux1 86 0x400 0x05>;
782 dma-names = "rx", "tx";
783 status = "disabled";
784 };
786 sai1: sai@4400a000 {
787 compatible = "st,stm32h7-sai";
788 #address-cells = <1>;
789 #size-cells = <1>;
790 ranges = <0 0x4400a000 0x400>;
791 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
792 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
793 resets = <&rcc SAI1_R>;
794 status = "disabled";
796 sai1a: audio-controller@4400a004 {
797 #sound-dai-cells = <0>;
799 compatible = "st,stm32-sai-sub-a";
800 reg = <0x4 0x1c>;
801 clocks = <&rcc SAI1_K>;
802 clock-names = "sai_ck";
803 dmas = <&dmamux1 87 0x400 0x01>;
804 status = "disabled";
805 };
807 sai1b: audio-controller@4400a024 {
808 #sound-dai-cells = <0>;
809 compatible = "st,stm32-sai-sub-b";
810 reg = <0x24 0x1c>;
811 clocks = <&rcc SAI1_K>;
812 clock-names = "sai_ck";
813 dmas = <&dmamux1 88 0x400 0x01>;
814 status = "disabled";
815 };
816 };
818 sai2: sai@4400b000 {
819 compatible = "st,stm32h7-sai";
820 #address-cells = <1>;
821 #size-cells = <1>;
822 ranges = <0 0x4400b000 0x400>;
823 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
824 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
825 resets = <&rcc SAI2_R>;
826 status = "disabled";
828 sai2a: audio-controller@4400b004 {
829 #sound-dai-cells = <0>;
830 compatible = "st,stm32-sai-sub-a";
831 reg = <0x4 0x1c>;
832 clocks = <&rcc SAI2_K>;
833 clock-names = "sai_ck";
834 dmas = <&dmamux1 89 0x400 0x01>;
835 status = "disabled";
836 };
838 sai2b: audio-controller@4400b024 {
839 #sound-dai-cells = <0>;
840 compatible = "st,stm32-sai-sub-b";
841 reg = <0x24 0x1c>;
842 clocks = <&rcc SAI2_K>;
843 clock-names = "sai_ck";
844 dmas = <&dmamux1 90 0x400 0x01>;
845 status = "disabled";
846 };
847 };
849 sai3: sai@4400c000 {
850 compatible = "st,stm32h7-sai";
851 #address-cells = <1>;
852 #size-cells = <1>;
853 ranges = <0 0x4400c000 0x400>;
854 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
855 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
856 resets = <&rcc SAI3_R>;
857 status = "disabled";
859 sai3a: audio-controller@4400c004 {
860 #sound-dai-cells = <0>;
861 compatible = "st,stm32-sai-sub-a";
862 reg = <0x04 0x1c>;
863 clocks = <&rcc SAI3_K>;
864 clock-names = "sai_ck";
865 dmas = <&dmamux1 113 0x400 0x01>;
866 status = "disabled";
867 };
869 sai3b: audio-controller@4400c024 {
870 #sound-dai-cells = <0>;
871 compatible = "st,stm32-sai-sub-b";
872 reg = <0x24 0x1c>;
873 clocks = <&rcc SAI3_K>;
874 clock-names = "sai_ck";
875 dmas = <&dmamux1 114 0x400 0x01>;
876 status = "disabled";
877 };
878 };
880 dfsdm: dfsdm@4400d000 {
881 compatible = "st,stm32mp1-dfsdm";
882 reg = <0x4400d000 0x800>;
883 clocks = <&rcc DFSDM_K>;
884 clock-names = "dfsdm";
885 #address-cells = <1>;
886 #size-cells = <0>;
887 status = "disabled";
889 dfsdm0: filter@0 {
890 compatible = "st,stm32-dfsdm-adc";
891 #io-channel-cells = <1>;
892 reg = <0>;
893 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
894 dmas = <&dmamux1 101 0x400 0x01>;
895 dma-names = "rx";
896 status = "disabled";
897 };
899 dfsdm1: filter@1 {
900 compatible = "st,stm32-dfsdm-adc";
901 #io-channel-cells = <1>;
902 reg = <1>;
903 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
904 dmas = <&dmamux1 102 0x400 0x01>;
905 dma-names = "rx";
906 status = "disabled";
907 };
909 dfsdm2: filter@2 {
910 compatible = "st,stm32-dfsdm-adc";
911 #io-channel-cells = <1>;
912 reg = <2>;
913 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
914 dmas = <&dmamux1 103 0x400 0x01>;
915 dma-names = "rx";
916 status = "disabled";
917 };
919 dfsdm3: filter@3 {
920 compatible = "st,stm32-dfsdm-adc";
921 #io-channel-cells = <1>;
922 reg = <3>;
923 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
924 dmas = <&dmamux1 104 0x400 0x01>;
925 dma-names = "rx";
926 status = "disabled";
927 };
929 dfsdm4: filter@4 {
930 compatible = "st,stm32-dfsdm-adc";
931 #io-channel-cells = <1>;
932 reg = <4>;
933 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
934 dmas = <&dmamux1 91 0x400 0x01>;
935 dma-names = "rx";
936 status = "disabled";
937 };
939 dfsdm5: filter@5 {
940 compatible = "st,stm32-dfsdm-adc";
941 #io-channel-cells = <1>;
942 reg = <5>;
943 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
944 dmas = <&dmamux1 92 0x400 0x01>;
945 dma-names = "rx";
946 status = "disabled";
947 };
948 };
950 dma1: dma-controller@48000000 {
951 compatible = "st,stm32-dma";
952 reg = <0x48000000 0x400>;
953 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
959 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
961 clocks = <&rcc DMA1>;
962 #dma-cells = <4>;
963 st,mem2mem;
964 dma-requests = <8>;
965 };
967 dma2: dma-controller@48001000 {
968 compatible = "st,stm32-dma";
969 reg = <0x48001000 0x400>;
970 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&rcc DMA2>;
979 #dma-cells = <4>;
980 st,mem2mem;
981 dma-requests = <8>;
982 };
984 dmamux1: dma-router@48002000 {
985 compatible = "st,stm32h7-dmamux";
986 reg = <0x48002000 0x1c>;
987 #dma-cells = <3>;
988 dma-requests = <128>;
989 dma-masters = <&dma1 &dma2>;
990 dma-channels = <16>;
991 clocks = <&rcc DMAMUX>;
992 };
994 adc: adc@48003000 {
995 compatible = "st,stm32mp1-adc-core";
996 reg = <0x48003000 0x400>;
997 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1000 clock-names = "bus", "adc";
1001 interrupt-controller;
1002 st,syscfg = <&syscfg>;
1003 #interrupt-cells = <1>;
1004 #address-cells = <1>;
1005 #size-cells = <0>;
1006 status = "disabled";
1008 adc1: adc@0 {
1009 compatible = "st,stm32mp1-adc";
1010 #io-channel-cells = <1>;
1011 reg = <0x0>;
1012 interrupt-parent = <&adc>;
1013 interrupts = <0>;
1014 dmas = <&dmamux1 9 0x400 0x01>;
1015 dma-names = "rx";
1016 status = "disabled";
1017 };
1019 adc2: adc@100 {
1020 compatible = "st,stm32mp1-adc";
1021 #io-channel-cells = <1>;
1022 reg = <0x100>;
1023 interrupt-parent = <&adc>;
1024 interrupts = <1>;
1025 dmas = <&dmamux1 10 0x400 0x01>;
1026 dma-names = "rx";
1027 status = "disabled";
1028 };
1029 };
1031 sdmmc3: sdmmc@48004000 {
1032 compatible = "arm,pl18x", "arm,primecell";
1033 arm,primecell-periphid = <0x10153180>;
1034 reg = <0x48004000 0x400>;
1035 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1036 interrupt-names = "cmd_irq";
1037 clocks = <&rcc SDMMC3_K>;
1038 clock-names = "apb_pclk";
1039 resets = <&rcc SDMMC3_R>;
1040 cap-sd-highspeed;
1041 cap-mmc-highspeed;
1042 max-frequency = <120000000>;
1043 status = "disabled";
1044 };
1046 usbotg_hs: usb-otg@49000000 {
1047 compatible = "snps,dwc2";
1048 reg = <0x49000000 0x10000>;
1049 clocks = <&rcc USBO_K>;
1050 clock-names = "otg";
1051 resets = <&rcc USBO_R>;
1052 reset-names = "dwc2";
1053 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1054 g-rx-fifo-size = <256>;
1055 g-np-tx-fifo-size = <32>;
1056 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
1057 dr_mode = "otg";
1058 status = "disabled";
1059 };
1061 ipcc: mailbox@4c001000 {
1062 compatible = "st,stm32mp1-ipcc";
1063 #mbox-cells = <1>;
1064 reg = <0x4c001000 0x400>;
1065 st,proc-id = <0>;
1066 interrupts-extended =
1067 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1068 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1069 <&exti 61 1>;
1070 interrupt-names = "rx", "tx", "wakeup";
1071 clocks = <&rcc IPCC>;
1072 wakeup-source;
1073 status = "disabled";
1074 };
1076 dcmi: dcmi@4c006000 {
1077 compatible = "st,stm32-dcmi";
1078 reg = <0x4c006000 0x400>;
1079 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1080 resets = <&rcc CAMITF_R>;
1081 clocks = <&rcc DCMI>;
1082 clock-names = "mclk";
1083 dmas = <&dmamux1 75 0x400 0x0d>;
1084 dma-names = "tx";
1085 status = "disabled";
1086 };
1088 rcc: rcc@50000000 {
1089 compatible = "st,stm32mp1-rcc", "syscon";
1090 reg = <0x50000000 0x1000>;
1091 #clock-cells = <1>;
1092 #reset-cells = <1>;
1093 };
1095 pwr_regulators: pwr@50001000 {
1096 compatible = "st,stm32mp1,pwr-reg";
1097 reg = <0x50001000 0x10>;
1099 reg11: reg11 {
1100 regulator-name = "reg11";
1101 regulator-min-microvolt = <1100000>;
1102 regulator-max-microvolt = <1100000>;
1103 };
1105 reg18: reg18 {
1106 regulator-name = "reg18";
1107 regulator-min-microvolt = <1800000>;
1108 regulator-max-microvolt = <1800000>;
1109 };
1111 usb33: usb33 {
1112 regulator-name = "usb33";
1113 regulator-min-microvolt = <3300000>;
1114 regulator-max-microvolt = <3300000>;
1115 };
1116 };
1118 exti: interrupt-controller@5000d000 {
1119 compatible = "st,stm32mp1-exti", "syscon";
1120 interrupt-controller;
1121 #interrupt-cells = <2>;
1122 reg = <0x5000d000 0x400>;
1123 };
1125 syscfg: syscon@50020000 {
1126 compatible = "st,stm32mp157-syscfg", "syscon";
1127 reg = <0x50020000 0x400>;
1128 clocks = <&rcc SYSCFG>;
1129 };
1131 lptimer2: timer@50021000 {
1132 #address-cells = <1>;
1133 #size-cells = <0>;
1134 compatible = "st,stm32-lptimer";
1135 reg = <0x50021000 0x400>;
1136 clocks = <&rcc LPTIM2_K>;
1137 clock-names = "mux";
1138 status = "disabled";
1140 pwm {
1141 compatible = "st,stm32-pwm-lp";
1142 #pwm-cells = <3>;
1143 status = "disabled";
1144 };
1146 trigger@1 {
1147 compatible = "st,stm32-lptimer-trigger";
1148 reg = <1>;
1149 status = "disabled";
1150 };
1152 counter {
1153 compatible = "st,stm32-lptimer-counter";
1154 status = "disabled";
1155 };
1156 };
1158 lptimer3: timer@50022000 {
1159 #address-cells = <1>;
1160 #size-cells = <0>;
1161 compatible = "st,stm32-lptimer";
1162 reg = <0x50022000 0x400>;
1163 clocks = <&rcc LPTIM3_K>;
1164 clock-names = "mux";
1165 status = "disabled";
1167 pwm {
1168 compatible = "st,stm32-pwm-lp";
1169 #pwm-cells = <3>;
1170 status = "disabled";
1171 };
1173 trigger@2 {
1174 compatible = "st,stm32-lptimer-trigger";
1175 reg = <2>;
1176 status = "disabled";
1177 };
1178 };
1180 lptimer4: timer@50023000 {
1181 compatible = "st,stm32-lptimer";
1182 reg = <0x50023000 0x400>;
1183 clocks = <&rcc LPTIM4_K>;
1184 clock-names = "mux";
1185 status = "disabled";
1187 pwm {
1188 compatible = "st,stm32-pwm-lp";
1189 #pwm-cells = <3>;
1190 status = "disabled";
1191 };
1192 };
1194 lptimer5: timer@50024000 {
1195 compatible = "st,stm32-lptimer";
1196 reg = <0x50024000 0x400>;
1197 clocks = <&rcc LPTIM5_K>;
1198 clock-names = "mux";
1199 status = "disabled";
1201 pwm {
1202 compatible = "st,stm32-pwm-lp";
1203 #pwm-cells = <3>;
1204 status = "disabled";
1205 };
1206 };
1208 vrefbuf: vrefbuf@50025000 {
1209 compatible = "st,stm32-vrefbuf";
1210 reg = <0x50025000 0x8>;
1211 regulator-min-microvolt = <1500000>;
1212 regulator-max-microvolt = <2500000>;
1213 clocks = <&rcc VREF>;
1214 status = "disabled";
1215 };
1217 sai4: sai@50027000 {
1218 compatible = "st,stm32h7-sai";
1219 #address-cells = <1>;
1220 #size-cells = <1>;
1221 ranges = <0 0x50027000 0x400>;
1222 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1223 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1224 resets = <&rcc SAI4_R>;
1225 status = "disabled";
1227 sai4a: audio-controller@50027004 {
1228 #sound-dai-cells = <0>;
1229 compatible = "st,stm32-sai-sub-a";
1230 reg = <0x04 0x1c>;
1231 clocks = <&rcc SAI4_K>;
1232 clock-names = "sai_ck";
1233 dmas = <&dmamux1 99 0x400 0x01>;
1234 status = "disabled";
1235 };
1237 sai4b: audio-controller@50027024 {
1238 #sound-dai-cells = <0>;
1239 compatible = "st,stm32-sai-sub-b";
1240 reg = <0x24 0x1c>;
1241 clocks = <&rcc SAI4_K>;
1242 clock-names = "sai_ck";
1243 dmas = <&dmamux1 100 0x400 0x01>;
1244 status = "disabled";
1245 };
1246 };
1248 dts: thermal@50028000 {
1249 compatible = "st,stm32-thermal";
1250 reg = <0x50028000 0x100>;
1251 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1252 clocks = <&rcc TMPSENS>;
1253 clock-names = "pclk";
1254 #thermal-sensor-cells = <0>;
1255 status = "disabled";
1256 };
1258 hash1: hash@54002000 {
1259 compatible = "st,stm32f756-hash";
1260 reg = <0x54002000 0x400>;
1261 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&rcc HASH1>;
1263 resets = <&rcc HASH1_R>;
1264 dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1265 dma-names = "in";
1266 dma-maxburst = <2>;
1267 status = "disabled";
1268 };
1270 rng1: rng@54003000 {
1271 compatible = "st,stm32-rng";
1272 reg = <0x54003000 0x400>;
1273 clocks = <&rcc RNG1_K>;
1274 resets = <&rcc RNG1_R>;
1275 status = "disabled";
1276 };
1278 mdma1: dma-controller@58000000 {
1279 compatible = "st,stm32h7-mdma";
1280 reg = <0x58000000 0x1000>;
1281 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1282 clocks = <&rcc MDMA>;
1283 #dma-cells = <5>;
1284 dma-channels = <32>;
1285 dma-requests = <48>;
1286 };
1288 fmc: nand-controller@58002000 {
1289 compatible = "st,stm32mp15-fmc2";
1290 reg = <0x58002000 0x1000>,
1291 <0x80000000 0x1000>,
1292 <0x88010000 0x1000>,
1293 <0x88020000 0x1000>,
1294 <0x81000000 0x1000>,
1295 <0x89010000 0x1000>,
1296 <0x89020000 0x1000>;
1297 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1298 dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
1299 <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
1300 <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
1301 dma-names = "tx", "rx", "ecc";
1302 clocks = <&rcc FMC_K>;
1303 resets = <&rcc FMC_R>;
1304 status = "disabled";
1305 };
1307 qspi: spi@58003000 {
1308 compatible = "st,stm32f469-qspi";
1309 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1310 reg-names = "qspi", "qspi_mm";
1311 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1312 dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
1313 <&mdma1 22 0x10 0x100008 0x0 0x0>;
1314 dma-names = "tx", "rx";
1315 clocks = <&rcc QSPI_K>;
1316 resets = <&rcc QSPI_R>;
1317 status = "disabled";
1318 };
1320 sdmmc1: sdmmc@58005000 {
1321 compatible = "arm,pl18x", "arm,primecell";
1322 arm,primecell-periphid = <0x10153180>;
1323 reg = <0x58005000 0x1000>;
1324 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1325 interrupt-names = "cmd_irq";
1326 clocks = <&rcc SDMMC1_K>;
1327 clock-names = "apb_pclk";
1328 resets = <&rcc SDMMC1_R>;
1329 cap-sd-highspeed;
1330 cap-mmc-highspeed;
1331 max-frequency = <120000000>;
1332 status = "disabled";
1333 };
1335 sdmmc2: sdmmc@58007000 {
1336 compatible = "arm,pl18x", "arm,primecell";
1337 arm,primecell-periphid = <0x10153180>;
1338 reg = <0x58007000 0x1000>;
1339 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1340 interrupt-names = "cmd_irq";
1341 clocks = <&rcc SDMMC2_K>;
1342 clock-names = "apb_pclk";
1343 resets = <&rcc SDMMC2_R>;
1344 cap-sd-highspeed;
1345 cap-mmc-highspeed;
1346 max-frequency = <120000000>;
1347 status = "disabled";
1348 };
1350 crc1: crc@58009000 {
1351 compatible = "st,stm32f7-crc";
1352 reg = <0x58009000 0x400>;
1353 clocks = <&rcc CRC1>;
1354 status = "disabled";
1355 };
1357 stmmac_axi_config_0: stmmac-axi-config {
1358 snps,wr_osr_lmt = <0x7>;
1359 snps,rd_osr_lmt = <0x7>;
1360 snps,blen = <0 0 0 0 16 8 4>;
1361 };
1363 ethernet0: ethernet@5800a000 {
1364 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1365 reg = <0x5800a000 0x2000>;
1366 reg-names = "stmmaceth";
1367 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1368 interrupt-names = "macirq";
1369 clock-names = "stmmaceth",
1370 "mac-clk-tx",
1371 "mac-clk-rx",
1372 "ethstp";
1373 clocks = <&rcc ETHMAC>,
1374 <&rcc ETHTX>,
1375 <&rcc ETHRX>,
1376 <&rcc ETHSTP>;
1377 st,syscon = <&syscfg 0x4>;
1378 snps,mixed-burst;
1379 snps,pbl = <2>;
1380 snps,en-tx-lpi-clockgating;
1381 snps,axi-config = <&stmmac_axi_config_0>;
1382 snps,tso;
1383 status = "disabled";
1384 };
1386 usbh_ohci: usbh-ohci@5800c000 {
1387 compatible = "generic-ohci";
1388 reg = <0x5800c000 0x1000>;
1389 clocks = <&rcc USBH>;
1390 resets = <&rcc USBH_R>;
1391 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1392 status = "disabled";
1393 };
1395 usbh_ehci: usbh-ehci@5800d000 {
1396 compatible = "generic-ehci";
1397 reg = <0x5800d000 0x1000>;
1398 clocks = <&rcc USBH>;
1399 resets = <&rcc USBH_R>;
1400 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1401 companion = <&usbh_ohci>;
1402 status = "disabled";
1403 };
1405 ltdc: display-controller@5a001000 {
1406 compatible = "st,stm32-ltdc";
1407 reg = <0x5a001000 0x400>;
1408 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1409 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1410 clocks = <&rcc LTDC_PX>;
1411 clock-names = "lcd";
1412 resets = <&rcc LTDC_R>;
1413 status = "disabled";
1414 };
1416 iwdg2: watchdog@5a002000 {
1417 compatible = "st,stm32mp1-iwdg";
1418 reg = <0x5a002000 0x400>;
1419 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1420 clock-names = "pclk", "lsi";
1421 status = "disabled";
1422 };
1424 usbphyc: usbphyc@5a006000 {
1425 #address-cells = <1>;
1426 #size-cells = <0>;
1427 compatible = "st,stm32mp1-usbphyc";
1428 reg = <0x5a006000 0x1000>;
1429 clocks = <&rcc USBPHY_K>;
1430 resets = <&rcc USBPHY_R>;
1431 status = "disabled";
1433 usbphyc_port0: usb-phy@0 {
1434 #phy-cells = <0>;
1435 reg = <0>;
1436 };
1438 usbphyc_port1: usb-phy@1 {
1439 #phy-cells = <1>;
1440 reg = <1>;
1441 };
1442 };
1444 usart1: serial@5c000000 {
1445 compatible = "st,stm32h7-uart";
1446 reg = <0x5c000000 0x400>;
1447 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1448 clocks = <&rcc USART1_K>;
1449 status = "disabled";
1450 };
1452 spi6: spi@5c001000 {
1453 #address-cells = <1>;
1454 #size-cells = <0>;
1455 compatible = "st,stm32h7-spi";
1456 reg = <0x5c001000 0x400>;
1457 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1458 clocks = <&rcc SPI6_K>;
1459 resets = <&rcc SPI6_R>;
1460 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1461 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1462 dma-names = "rx", "tx";
1463 status = "disabled";
1464 };
1466 i2c4: i2c@5c002000 {
1467 compatible = "st,stm32f7-i2c";
1468 reg = <0x5c002000 0x400>;
1469 interrupt-names = "event", "error";
1470 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1471 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1472 clocks = <&rcc I2C4_K>;
1473 resets = <&rcc I2C4_R>;
1474 #address-cells = <1>;
1475 #size-cells = <0>;
1476 status = "disabled";
1477 };
1479 rtc: rtc@5c004000 {
1480 compatible = "st,stm32mp1-rtc";
1481 reg = <0x5c004000 0x400>;
1482 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1483 clock-names = "pclk", "rtc_ck";
1484 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1485 status = "disabled";
1486 };
1488 bsec: efuse@5c005000 {
1489 compatible = "st,stm32mp15-bsec";
1490 reg = <0x5c005000 0x400>;
1491 #address-cells = <1>;
1492 #size-cells = <1>;
1493 ts_cal1: calib@5c {
1494 reg = <0x5c 0x2>;
1495 };
1496 ts_cal2: calib@5e {
1497 reg = <0x5e 0x2>;
1498 };
1499 };
1501 i2c6: i2c@5c009000 {
1502 compatible = "st,stm32f7-i2c";
1503 reg = <0x5c009000 0x400>;
1504 interrupt-names = "event", "error";
1505 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1506 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1507 clocks = <&rcc I2C6_K>;
1508 resets = <&rcc I2C6_R>;
1509 #address-cells = <1>;
1510 #size-cells = <0>;
1511 status = "disabled";
1512 };
1514 /*
1515 * Break node order to solve dependency probe issue between
1516 * pinctrl and exti.
1517 */
1518 pinctrl: pin-controller@50002000 {
1519 #address-cells = <1>;
1520 #size-cells = <1>;
1521 compatible = "st,stm32mp157-pinctrl";
1522 ranges = <0 0x50002000 0xa400>;
1523 interrupt-parent = <&exti>;
1524 st,syscfg = <&exti 0x60 0xff>;
1525 pins-are-numbered;
1527 gpioa: gpio@50002000 {
1528 gpio-controller;
1529 #gpio-cells = <2>;
1530 interrupt-controller;
1531 #interrupt-cells = <2>;
1532 reg = <0x0 0x400>;
1533 clocks = <&rcc GPIOA>;
1534 st,bank-name = "GPIOA";
1535 status = "disabled";
1536 };
1538 gpiob: gpio@50003000 {
1539 gpio-controller;
1540 #gpio-cells = <2>;
1541 interrupt-controller;
1542 #interrupt-cells = <2>;
1543 reg = <0x1000 0x400>;
1544 clocks = <&rcc GPIOB>;
1545 st,bank-name = "GPIOB";
1546 status = "disabled";
1547 };
1549 gpioc: gpio@50004000 {
1550 gpio-controller;
1551 #gpio-cells = <2>;
1552 interrupt-controller;
1553 #interrupt-cells = <2>;
1554 reg = <0x2000 0x400>;
1555 clocks = <&rcc GPIOC>;
1556 st,bank-name = "GPIOC";
1557 status = "disabled";
1558 };
1560 gpiod: gpio@50005000 {
1561 gpio-controller;
1562 #gpio-cells = <2>;
1563 interrupt-controller;
1564 #interrupt-cells = <2>;
1565 reg = <0x3000 0x400>;
1566 clocks = <&rcc GPIOD>;
1567 st,bank-name = "GPIOD";
1568 status = "disabled";
1569 };
1571 gpioe: gpio@50006000 {
1572 gpio-controller;
1573 #gpio-cells = <2>;
1574 interrupt-controller;
1575 #interrupt-cells = <2>;
1576 reg = <0x4000 0x400>;
1577 clocks = <&rcc GPIOE>;
1578 st,bank-name = "GPIOE";
1579 status = "disabled";
1580 };
1582 gpiof: gpio@50007000 {
1583 gpio-controller;
1584 #gpio-cells = <2>;
1585 interrupt-controller;
1586 #interrupt-cells = <2>;
1587 reg = <0x5000 0x400>;
1588 clocks = <&rcc GPIOF>;
1589 st,bank-name = "GPIOF";
1590 status = "disabled";
1591 };
1593 gpiog: gpio@50008000 {
1594 gpio-controller;
1595 #gpio-cells = <2>;
1596 interrupt-controller;
1597 #interrupt-cells = <2>;
1598 reg = <0x6000 0x400>;
1599 clocks = <&rcc GPIOG>;
1600 st,bank-name = "GPIOG";
1601 status = "disabled";
1602 };
1604 gpioh: gpio@50009000 {
1605 gpio-controller;
1606 #gpio-cells = <2>;
1607 interrupt-controller;
1608 #interrupt-cells = <2>;
1609 reg = <0x7000 0x400>;
1610 clocks = <&rcc GPIOH>;
1611 st,bank-name = "GPIOH";
1612 status = "disabled";
1613 };
1615 gpioi: gpio@5000a000 {
1616 gpio-controller;
1617 #gpio-cells = <2>;
1618 interrupt-controller;
1619 #interrupt-cells = <2>;
1620 reg = <0x8000 0x400>;
1621 clocks = <&rcc GPIOI>;
1622 st,bank-name = "GPIOI";
1623 status = "disabled";
1624 };
1626 gpioj: gpio@5000b000 {
1627 gpio-controller;
1628 #gpio-cells = <2>;
1629 interrupt-controller;
1630 #interrupt-cells = <2>;
1631 reg = <0x9000 0x400>;
1632 clocks = <&rcc GPIOJ>;
1633 st,bank-name = "GPIOJ";
1634 status = "disabled";
1635 };
1637 gpiok: gpio@5000c000 {
1638 gpio-controller;
1639 #gpio-cells = <2>;
1640 interrupt-controller;
1641 #interrupt-cells = <2>;
1642 reg = <0xa000 0x400>;
1643 clocks = <&rcc GPIOK>;
1644 st,bank-name = "GPIOK";
1645 status = "disabled";
1646 };
1647 };
1649 pinctrl_z: pin-controller-z@54004000 {
1650 #address-cells = <1>;
1651 #size-cells = <1>;
1652 compatible = "st,stm32mp157-z-pinctrl";
1653 ranges = <0 0x54004000 0x400>;
1654 pins-are-numbered;
1655 interrupt-parent = <&exti>;
1656 st,syscfg = <&exti 0x60 0xff>;
1658 gpioz: gpio@54004000 {
1659 gpio-controller;
1660 #gpio-cells = <2>;
1661 interrupt-controller;
1662 #interrupt-cells = <2>;
1663 reg = <0 0x400>;
1664 clocks = <&rcc GPIOZ>;
1665 st,bank-name = "GPIOZ";
1666 st,bank-ioport = <11>;
1667 status = "disabled";
1668 };
1669 };
1670 };
1672 mlahb: ahb {
1673 compatible = "st,mlahb", "simple-bus";
1674 #address-cells = <1>;
1675 #size-cells = <1>;
1676 ranges;
1677 dma-ranges = <0x00000000 0x38000000 0x10000>,
1678 <0x10000000 0x10000000 0x60000>,
1679 <0x30000000 0x30000000 0x60000>;
1681 m4_rproc: m4@10000000 {
1682 compatible = "st,stm32mp1-m4";
1683 reg = <0x10000000 0x40000>,
1684 <0x30000000 0x40000>,
1685 <0x38000000 0x10000>;
1686 resets = <&rcc MCU_R>;
1687 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1688 st,syscfg-tz = <&rcc 0x000 0x1>;
1689 status = "disabled";
1690 };
1691 };
1692 };