| blob | bf531efc0610e7f0921c2ed6b9e59fa7e148e233 |
1 /*
2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
49 / {
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
54 aliases {
55 ethernet0 = &emac;
56 };
58 chosen {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
63 framebuffer-lcd0-hdmi {
64 compatible = "allwinner,simple-framebuffer",
65 "simple-framebuffer";
66 allwinner,pipeline = "de_be0-lcd0-hdmi";
67 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
68 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
69 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
70 status = "disabled";
71 };
73 framebuffer-fe0-lcd0-hdmi {
74 compatible = "allwinner,simple-framebuffer",
75 "simple-framebuffer";
76 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
77 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
78 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
79 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
80 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
81 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
82 status = "disabled";
83 };
85 framebuffer-fe0-lcd0 {
86 compatible = "allwinner,simple-framebuffer",
87 "simple-framebuffer";
88 allwinner,pipeline = "de_fe0-de_be0-lcd0";
89 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
90 <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
91 <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>,
92 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
93 status = "disabled";
94 };
96 framebuffer-fe0-lcd0-tve0 {
97 compatible = "allwinner,simple-framebuffer",
98 "simple-framebuffer";
99 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
100 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
101 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
102 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
103 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
104 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
105 status = "disabled";
106 };
107 };
109 cpus {
110 #address-cells = <1>;
111 #size-cells = <0>;
112 cpu0: cpu@0 {
113 device_type = "cpu";
114 compatible = "arm,cortex-a8";
115 reg = <0x0>;
116 clocks = <&ccu CLK_CPU>;
117 clock-latency = <244144>; /* 8 32k periods */
118 operating-points = <
119 /* kHz uV */
120 1008000 1400000
121 912000 1350000
122 864000 1300000
123 624000 1250000
124 >;
125 #cooling-cells = <2>;
126 };
127 };
129 thermal-zones {
130 cpu-thermal {
131 /* milliseconds */
132 polling-delay-passive = <250>;
133 polling-delay = <1000>;
134 thermal-sensors = <&rtp>;
136 cooling-maps {
137 map0 {
138 trip = <&cpu_alert0>;
139 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
140 };
141 };
143 trips {
144 cpu_alert0: cpu-alert0 {
145 /* milliCelsius */
146 temperature = <850000>;
147 hysteresis = <2000>;
148 type = "passive";
149 };
151 cpu_crit: cpu-crit {
152 /* milliCelsius */
153 temperature = <100000>;
154 hysteresis = <2000>;
155 type = "critical";
156 };
157 };
158 };
159 };
161 clocks {
162 #address-cells = <1>;
163 #size-cells = <1>;
164 ranges;
166 osc24M: clk-24M {
167 #clock-cells = <0>;
168 compatible = "fixed-clock";
169 clock-frequency = <24000000>;
170 clock-output-names = "osc24M";
171 };
173 osc32k: clk-32k {
174 #clock-cells = <0>;
175 compatible = "fixed-clock";
176 clock-frequency = <32768>;
177 clock-output-names = "osc32k";
178 };
179 };
181 de: display-engine {
182 compatible = "allwinner,sun4i-a10-display-engine";
183 allwinner,pipelines = <&fe0>, <&fe1>;
184 status = "disabled";
185 };
187 pmu {
188 compatible = "arm,cortex-a8-pmu";
189 interrupts = <3>;
190 };
192 reserved-memory {
193 #address-cells = <1>;
194 #size-cells = <1>;
195 ranges;
197 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
198 default-pool {
199 compatible = "shared-dma-pool";
200 size = <0x6000000>;
201 alloc-ranges = <0x4a000000 0x6000000>;
202 reusable;
203 linux,cma-default;
204 };
205 };
207 soc {
208 compatible = "simple-bus";
209 #address-cells = <1>;
210 #size-cells = <1>;
211 ranges;
213 system-control@1c00000 {
214 compatible = "allwinner,sun4i-a10-system-control";
215 reg = <0x01c00000 0x30>;
216 #address-cells = <1>;
217 #size-cells = <1>;
218 ranges;
220 sram_a: sram@0 {
221 compatible = "mmio-sram";
222 reg = <0x00000000 0xc000>;
223 #address-cells = <1>;
224 #size-cells = <1>;
225 ranges = <0 0x00000000 0xc000>;
227 emac_sram: sram-section@8000 {
228 compatible = "allwinner,sun4i-a10-sram-a3-a4";
229 reg = <0x8000 0x4000>;
230 status = "disabled";
231 };
232 };
234 sram_d: sram@10000 {
235 compatible = "mmio-sram";
236 reg = <0x00010000 0x1000>;
237 #address-cells = <1>;
238 #size-cells = <1>;
239 ranges = <0 0x00010000 0x1000>;
241 otg_sram: sram-section@0 {
242 compatible = "allwinner,sun4i-a10-sram-d";
243 reg = <0x0000 0x1000>;
244 status = "disabled";
245 };
246 };
248 sram_c: sram@1d00000 {
249 compatible = "mmio-sram";
250 reg = <0x01d00000 0xd0000>;
251 #address-cells = <1>;
252 #size-cells = <1>;
253 ranges = <0 0x01d00000 0xd0000>;
255 ve_sram: sram-section@0 {
256 compatible = "allwinner,sun4i-a10-sram-c1";
257 reg = <0x000000 0x80000>;
258 };
259 };
260 };
262 dma: dma-controller@1c02000 {
263 compatible = "allwinner,sun4i-a10-dma";
264 reg = <0x01c02000 0x1000>;
265 interrupts = <27>;
266 clocks = <&ccu CLK_AHB_DMA>;
267 #dma-cells = <2>;
268 };
270 nfc: nand-controller@1c03000 {
271 compatible = "allwinner,sun4i-a10-nand";
272 reg = <0x01c03000 0x1000>;
273 interrupts = <37>;
274 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
275 clock-names = "ahb", "mod";
276 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
277 dma-names = "rxtx";
278 status = "disabled";
279 #address-cells = <1>;
280 #size-cells = <0>;
281 };
283 spi0: spi@1c05000 {
284 compatible = "allwinner,sun4i-a10-spi";
285 reg = <0x01c05000 0x1000>;
286 interrupts = <10>;
287 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
288 clock-names = "ahb", "mod";
289 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
290 <&dma SUN4I_DMA_DEDICATED 26>;
291 dma-names = "rx", "tx";
292 status = "disabled";
293 #address-cells = <1>;
294 #size-cells = <0>;
295 };
297 spi1: spi@1c06000 {
298 compatible = "allwinner,sun4i-a10-spi";
299 reg = <0x01c06000 0x1000>;
300 interrupts = <11>;
301 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
302 clock-names = "ahb", "mod";
303 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
304 <&dma SUN4I_DMA_DEDICATED 8>;
305 dma-names = "rx", "tx";
306 pinctrl-names = "default";
307 pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
308 status = "disabled";
309 #address-cells = <1>;
310 #size-cells = <0>;
311 };
313 emac: ethernet@1c0b000 {
314 compatible = "allwinner,sun4i-a10-emac";
315 reg = <0x01c0b000 0x1000>;
316 interrupts = <55>;
317 clocks = <&ccu CLK_AHB_EMAC>;
318 allwinner,sram = <&emac_sram 1>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&emac_pins>;
321 status = "disabled";
322 };
324 mdio: mdio@1c0b080 {
325 compatible = "allwinner,sun4i-a10-mdio";
326 reg = <0x01c0b080 0x14>;
327 status = "disabled";
328 #address-cells = <1>;
329 #size-cells = <0>;
330 };
332 tcon0: lcd-controller@1c0c000 {
333 compatible = "allwinner,sun4i-a10-tcon";
334 reg = <0x01c0c000 0x1000>;
335 interrupts = <44>;
336 resets = <&ccu RST_TCON0>;
337 reset-names = "lcd";
338 clocks = <&ccu CLK_AHB_LCD0>,
339 <&ccu CLK_TCON0_CH0>,
340 <&ccu CLK_TCON0_CH1>;
341 clock-names = "ahb",
342 "tcon-ch0",
343 "tcon-ch1";
344 clock-output-names = "tcon0-pixel-clock";
345 #clock-cells = <0>;
346 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
348 ports {
349 #address-cells = <1>;
350 #size-cells = <0>;
352 tcon0_in: port@0 {
353 #address-cells = <1>;
354 #size-cells = <0>;
355 reg = <0>;
357 tcon0_in_be0: endpoint@0 {
358 reg = <0>;
359 remote-endpoint = <&be0_out_tcon0>;
360 };
362 tcon0_in_be1: endpoint@1 {
363 reg = <1>;
364 remote-endpoint = <&be1_out_tcon0>;
365 };
366 };
368 tcon0_out: port@1 {
369 #address-cells = <1>;
370 #size-cells = <0>;
371 reg = <1>;
373 tcon0_out_hdmi: endpoint@1 {
374 reg = <1>;
375 remote-endpoint = <&hdmi_in_tcon0>;
376 allwinner,tcon-channel = <1>;
377 };
378 };
379 };
380 };
382 tcon1: lcd-controller@1c0d000 {
383 compatible = "allwinner,sun4i-a10-tcon";
384 reg = <0x01c0d000 0x1000>;
385 interrupts = <45>;
386 resets = <&ccu RST_TCON1>;
387 reset-names = "lcd";
388 clocks = <&ccu CLK_AHB_LCD1>,
389 <&ccu CLK_TCON1_CH0>,
390 <&ccu CLK_TCON1_CH1>;
391 clock-names = "ahb",
392 "tcon-ch0",
393 "tcon-ch1";
394 clock-output-names = "tcon1-pixel-clock";
395 #clock-cells = <0>;
396 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
398 ports {
399 #address-cells = <1>;
400 #size-cells = <0>;
402 tcon1_in: port@0 {
403 #address-cells = <1>;
404 #size-cells = <0>;
405 reg = <0>;
407 tcon1_in_be0: endpoint@0 {
408 reg = <0>;
409 remote-endpoint = <&be0_out_tcon1>;
410 };
412 tcon1_in_be1: endpoint@1 {
413 reg = <1>;
414 remote-endpoint = <&be1_out_tcon1>;
415 };
416 };
418 tcon1_out: port@1 {
419 #address-cells = <1>;
420 #size-cells = <0>;
421 reg = <1>;
423 tcon1_out_hdmi: endpoint@1 {
424 reg = <1>;
425 remote-endpoint = <&hdmi_in_tcon1>;
426 allwinner,tcon-channel = <1>;
427 };
428 };
429 };
430 };
432 video-codec@1c0e000 {
433 compatible = "allwinner,sun4i-a10-video-engine";
434 reg = <0x01c0e000 0x1000>;
435 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
436 <&ccu CLK_DRAM_VE>;
437 clock-names = "ahb", "mod", "ram";
438 resets = <&ccu RST_VE>;
439 interrupts = <53>;
440 allwinner,sram = <&ve_sram 1>;
441 };
443 mmc0: mmc@1c0f000 {
444 compatible = "allwinner,sun4i-a10-mmc";
445 reg = <0x01c0f000 0x1000>;
446 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
447 clock-names = "ahb", "mmc";
448 interrupts = <32>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&mmc0_pins>;
451 status = "disabled";
452 #address-cells = <1>;
453 #size-cells = <0>;
454 };
456 mmc1: mmc@1c10000 {
457 compatible = "allwinner,sun4i-a10-mmc";
458 reg = <0x01c10000 0x1000>;
459 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
460 clock-names = "ahb", "mmc";
461 interrupts = <33>;
462 status = "disabled";
463 #address-cells = <1>;
464 #size-cells = <0>;
465 };
467 mmc2: mmc@1c11000 {
468 compatible = "allwinner,sun4i-a10-mmc";
469 reg = <0x01c11000 0x1000>;
470 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
471 clock-names = "ahb", "mmc";
472 interrupts = <34>;
473 status = "disabled";
474 #address-cells = <1>;
475 #size-cells = <0>;
476 };
478 mmc3: mmc@1c12000 {
479 compatible = "allwinner,sun4i-a10-mmc";
480 reg = <0x01c12000 0x1000>;
481 clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
482 clock-names = "ahb", "mmc";
483 interrupts = <35>;
484 status = "disabled";
485 #address-cells = <1>;
486 #size-cells = <0>;
487 };
489 usb_otg: usb@1c13000 {
490 compatible = "allwinner,sun4i-a10-musb";
491 reg = <0x01c13000 0x0400>;
492 clocks = <&ccu CLK_AHB_OTG>;
493 interrupts = <38>;
494 interrupt-names = "mc";
495 phys = <&usbphy 0>;
496 phy-names = "usb";
497 extcon = <&usbphy 0>;
498 allwinner,sram = <&otg_sram 1>;
499 dr_mode = "otg";
500 status = "disabled";
501 };
503 usbphy: phy@1c13400 {
504 #phy-cells = <1>;
505 compatible = "allwinner,sun4i-a10-usb-phy";
506 reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
507 reg-names = "phy_ctrl", "pmu1", "pmu2";
508 clocks = <&ccu CLK_USB_PHY>;
509 clock-names = "usb_phy";
510 resets = <&ccu RST_USB_PHY0>,
511 <&ccu RST_USB_PHY1>,
512 <&ccu RST_USB_PHY2>;
513 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
514 status = "disabled";
515 };
517 ehci0: usb@1c14000 {
518 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
519 reg = <0x01c14000 0x100>;
520 interrupts = <39>;
521 clocks = <&ccu CLK_AHB_EHCI0>;
522 phys = <&usbphy 1>;
523 phy-names = "usb";
524 status = "disabled";
525 };
527 ohci0: usb@1c14400 {
528 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
529 reg = <0x01c14400 0x100>;
530 interrupts = <64>;
531 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
532 phys = <&usbphy 1>;
533 phy-names = "usb";
534 status = "disabled";
535 };
537 crypto: crypto-engine@1c15000 {
538 compatible = "allwinner,sun4i-a10-crypto";
539 reg = <0x01c15000 0x1000>;
540 interrupts = <86>;
541 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
542 clock-names = "ahb", "mod";
543 };
545 hdmi: hdmi@1c16000 {
546 compatible = "allwinner,sun4i-a10-hdmi";
547 reg = <0x01c16000 0x1000>;
548 interrupts = <58>;
549 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
550 <&ccu CLK_PLL_VIDEO0_2X>,
551 <&ccu CLK_PLL_VIDEO1_2X>;
552 clock-names = "ahb", "mod", "pll-0", "pll-1";
553 dmas = <&dma SUN4I_DMA_NORMAL 16>,
554 <&dma SUN4I_DMA_NORMAL 16>,
555 <&dma SUN4I_DMA_DEDICATED 24>;
556 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
557 status = "disabled";
559 ports {
560 #address-cells = <1>;
561 #size-cells = <0>;
563 hdmi_in: port@0 {
564 #address-cells = <1>;
565 #size-cells = <0>;
566 reg = <0>;
568 hdmi_in_tcon0: endpoint@0 {
569 reg = <0>;
570 remote-endpoint = <&tcon0_out_hdmi>;
571 };
573 hdmi_in_tcon1: endpoint@1 {
574 reg = <1>;
575 remote-endpoint = <&tcon1_out_hdmi>;
576 };
577 };
579 hdmi_out: port@1 {
580 reg = <1>;
581 };
582 };
583 };
585 spi2: spi@1c17000 {
586 compatible = "allwinner,sun4i-a10-spi";
587 reg = <0x01c17000 0x1000>;
588 interrupts = <12>;
589 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
590 clock-names = "ahb", "mod";
591 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
592 <&dma SUN4I_DMA_DEDICATED 28>;
593 dma-names = "rx", "tx";
594 status = "disabled";
595 #address-cells = <1>;
596 #size-cells = <0>;
597 };
599 ahci: sata@1c18000 {
600 compatible = "allwinner,sun4i-a10-ahci";
601 reg = <0x01c18000 0x1000>;
602 interrupts = <56>;
603 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
604 status = "disabled";
605 };
607 ehci1: usb@1c1c000 {
608 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
609 reg = <0x01c1c000 0x100>;
610 interrupts = <40>;
611 clocks = <&ccu CLK_AHB_EHCI1>;
612 phys = <&usbphy 2>;
613 phy-names = "usb";
614 status = "disabled";
615 };
617 ohci1: usb@1c1c400 {
618 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
619 reg = <0x01c1c400 0x100>;
620 interrupts = <65>;
621 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
622 phys = <&usbphy 2>;
623 phy-names = "usb";
624 status = "disabled";
625 };
627 csi1: csi@1c1d000 {
628 compatible = "allwinner,sun4i-a10-csi1";
629 reg = <0x01c1d000 0x1000>;
630 interrupts = <43>;
631 clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
632 clock-names = "bus", "ram";
633 resets = <&ccu RST_CSI1>;
634 status = "disabled";
635 };
637 spi3: spi@1c1f000 {
638 compatible = "allwinner,sun4i-a10-spi";
639 reg = <0x01c1f000 0x1000>;
640 interrupts = <50>;
641 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
642 clock-names = "ahb", "mod";
643 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
644 <&dma SUN4I_DMA_DEDICATED 30>;
645 dma-names = "rx", "tx";
646 status = "disabled";
647 #address-cells = <1>;
648 #size-cells = <0>;
649 };
651 ccu: clock@1c20000 {
652 compatible = "allwinner,sun4i-a10-ccu";
653 reg = <0x01c20000 0x400>;
654 clocks = <&osc24M>, <&osc32k>;
655 clock-names = "hosc", "losc";
656 #clock-cells = <1>;
657 #reset-cells = <1>;
658 };
660 intc: interrupt-controller@1c20400 {
661 compatible = "allwinner,sun4i-a10-ic";
662 reg = <0x01c20400 0x400>;
663 interrupt-controller;
664 #interrupt-cells = <1>;
665 };
667 pio: pinctrl@1c20800 {
668 compatible = "allwinner,sun4i-a10-pinctrl";
669 reg = <0x01c20800 0x400>;
670 interrupts = <28>;
671 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
672 clock-names = "apb", "hosc", "losc";
673 gpio-controller;
674 interrupt-controller;
675 #interrupt-cells = <3>;
676 #gpio-cells = <3>;
678 can0_ph_pins: can0-ph-pins {
679 pins = "PH20", "PH21";
680 function = "can";
681 };
683 /omit-if-no-ref/
684 csi1_8bits_pg_pins: csi1-8bits-pg-pins {
685 pins = "PG0", "PG2", "PG3", "PG4", "PG5",
686 "PG6", "PG7", "PG8", "PG9", "PG10",
687 "PG11";
688 function = "csi1";
689 };
691 /omit-if-no-ref/
692 csi1_24bits_ph_pins: csi1-24bits-ph-pins {
693 pins = "PH0", "PH1", "PH2", "PH3", "PH4",
694 "PH5", "PH6", "PH7", "PH8", "PH9",
695 "PH10", "PH11", "PH12", "PH13", "PH14",
696 "PH15", "PH16", "PH17", "PH18", "PH19",
697 "PH20", "PH21", "PH22", "PH23", "PH24",
698 "PH25", "PH26", "PH27";
699 function = "csi1";
700 };
702 /omit-if-no-ref/
703 csi1_clk_pg_pin: csi1-clk-pg-pin {
704 pins = "PG1";
705 function = "csi1";
706 };
708 emac_pins: emac0-pins {
709 pins = "PA0", "PA1", "PA2",
710 "PA3", "PA4", "PA5", "PA6",
711 "PA7", "PA8", "PA9", "PA10",
712 "PA11", "PA12", "PA13", "PA14",
713 "PA15", "PA16";
714 function = "emac";
715 };
717 i2c0_pins: i2c0-pins {
718 pins = "PB0", "PB1";
719 function = "i2c0";
720 };
722 i2c1_pins: i2c1-pins {
723 pins = "PB18", "PB19";
724 function = "i2c1";
725 };
727 i2c2_pins: i2c2-pins {
728 pins = "PB20", "PB21";
729 function = "i2c2";
730 };
732 ir0_rx_pins: ir0-rx-pin {
733 pins = "PB4";
734 function = "ir0";
735 };
737 ir0_tx_pins: ir0-tx-pin {
738 pins = "PB3";
739 function = "ir0";
740 };
742 ir1_rx_pins: ir1-rx-pin {
743 pins = "PB23";
744 function = "ir1";
745 };
747 ir1_tx_pins: ir1-tx-pin {
748 pins = "PB22";
749 function = "ir1";
750 };
752 mmc0_pins: mmc0-pins {
753 pins = "PF0", "PF1", "PF2",
754 "PF3", "PF4", "PF5";
755 function = "mmc0";
756 drive-strength = <30>;
757 bias-pull-up;
758 };
760 ps2_ch0_pins: ps2-ch0-pins {
761 pins = "PI20", "PI21";
762 function = "ps2";
763 };
765 ps2_ch1_ph_pins: ps2-ch1-ph-pins {
766 pins = "PH12", "PH13";
767 function = "ps2";
768 };
770 pwm0_pin: pwm0-pin {
771 pins = "PB2";
772 function = "pwm";
773 };
775 pwm1_pin: pwm1-pin {
776 pins = "PI3";
777 function = "pwm";
778 };
780 spdif_tx_pin: spdif-tx-pin {
781 pins = "PB13";
782 function = "spdif";
783 bias-pull-up;
784 };
786 spi0_pi_pins: spi0-pi-pins {
787 pins = "PI11", "PI12", "PI13";
788 function = "spi0";
789 };
791 spi0_cs0_pi_pin: spi0-cs0-pi-pin {
792 pins = "PI10";
793 function = "spi0";
794 };
796 spi1_pins: spi1-pins {
797 pins = "PI17", "PI18", "PI19";
798 function = "spi1";
799 };
801 spi1_cs0_pin: spi1-cs0-pin {
802 pins = "PI16";
803 function = "spi1";
804 };
806 spi2_pb_pins: spi2-pb-pins {
807 pins = "PB15", "PB16", "PB17";
808 function = "spi2";
809 };
811 spi2_pc_pins: spi2-pc-pins {
812 pins = "PC20", "PC21", "PC22";
813 function = "spi2";
814 };
816 spi2_cs0_pb_pin: spi2-cs0-pb-pin {
817 pins = "PB14";
818 function = "spi2";
819 };
821 spi2_cs0_pc_pins: spi2-cs0-pc-pin {
822 pins = "PC19";
823 function = "spi2";
824 };
826 uart0_pb_pins: uart0-pb-pins {
827 pins = "PB22", "PB23";
828 function = "uart0";
829 };
831 uart0_pf_pins: uart0-pf-pins {
832 pins = "PF2", "PF4";
833 function = "uart0";
834 };
836 uart1_pins: uart1-pins {
837 pins = "PA10", "PA11";
838 function = "uart1";
839 };
840 };
842 timer@1c20c00 {
843 compatible = "allwinner,sun4i-a10-timer";
844 reg = <0x01c20c00 0x90>;
845 interrupts = <22>,
846 <23>,
847 <24>,
848 <25>,
849 <67>,
850 <68>;
851 clocks = <&osc24M>;
852 };
854 wdt: watchdog@1c20c90 {
855 compatible = "allwinner,sun4i-a10-wdt";
856 reg = <0x01c20c90 0x10>;
857 interrupts = <24>;
858 clocks = <&osc24M>;
859 };
861 rtc: rtc@1c20d00 {
862 compatible = "allwinner,sun4i-a10-rtc";
863 reg = <0x01c20d00 0x20>;
864 interrupts = <24>;
865 };
867 pwm: pwm@1c20e00 {
868 compatible = "allwinner,sun4i-a10-pwm";
869 reg = <0x01c20e00 0xc>;
870 clocks = <&osc24M>;
871 #pwm-cells = <3>;
872 status = "disabled";
873 };
875 spdif: spdif@1c21000 {
876 #sound-dai-cells = <0>;
877 compatible = "allwinner,sun4i-a10-spdif";
878 reg = <0x01c21000 0x400>;
879 interrupts = <13>;
880 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
881 clock-names = "apb", "spdif";
882 dmas = <&dma SUN4I_DMA_NORMAL 2>,
883 <&dma SUN4I_DMA_NORMAL 2>;
884 dma-names = "rx", "tx";
885 status = "disabled";
886 };
888 ir0: ir@1c21800 {
889 compatible = "allwinner,sun4i-a10-ir";
890 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
891 clock-names = "apb", "ir";
892 interrupts = <5>;
893 reg = <0x01c21800 0x40>;
894 status = "disabled";
895 };
897 ir1: ir@1c21c00 {
898 compatible = "allwinner,sun4i-a10-ir";
899 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
900 clock-names = "apb", "ir";
901 interrupts = <6>;
902 reg = <0x01c21c00 0x40>;
903 status = "disabled";
904 };
906 i2s0: i2s@1c22400 {
907 #sound-dai-cells = <0>;
908 compatible = "allwinner,sun4i-a10-i2s";
909 reg = <0x01c22400 0x400>;
910 interrupts = <16>;
911 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
912 clock-names = "apb", "mod";
913 dmas = <&dma SUN4I_DMA_NORMAL 3>,
914 <&dma SUN4I_DMA_NORMAL 3>;
915 dma-names = "rx", "tx";
916 status = "disabled";
917 };
919 lradc: lradc@1c22800 {
920 compatible = "allwinner,sun4i-a10-lradc-keys";
921 reg = <0x01c22800 0x100>;
922 interrupts = <31>;
923 status = "disabled";
924 };
926 codec: codec@1c22c00 {
927 #sound-dai-cells = <0>;
928 compatible = "allwinner,sun4i-a10-codec";
929 reg = <0x01c22c00 0x40>;
930 interrupts = <30>;
931 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
932 clock-names = "apb", "codec";
933 dmas = <&dma SUN4I_DMA_NORMAL 19>,
934 <&dma SUN4I_DMA_NORMAL 19>;
935 dma-names = "rx", "tx";
936 status = "disabled";
937 };
939 sid: eeprom@1c23800 {
940 compatible = "allwinner,sun4i-a10-sid";
941 reg = <0x01c23800 0x10>;
942 };
944 rtp: rtp@1c25000 {
945 compatible = "allwinner,sun4i-a10-ts";
946 reg = <0x01c25000 0x100>;
947 interrupts = <29>;
948 #thermal-sensor-cells = <0>;
949 };
951 uart0: serial@1c28000 {
952 compatible = "snps,dw-apb-uart";
953 reg = <0x01c28000 0x400>;
954 interrupts = <1>;
955 reg-shift = <2>;
956 reg-io-width = <4>;
957 clocks = <&ccu CLK_APB1_UART0>;
958 status = "disabled";
959 };
961 uart1: serial@1c28400 {
962 compatible = "snps,dw-apb-uart";
963 reg = <0x01c28400 0x400>;
964 interrupts = <2>;
965 reg-shift = <2>;
966 reg-io-width = <4>;
967 clocks = <&ccu CLK_APB1_UART1>;
968 status = "disabled";
969 };
971 uart2: serial@1c28800 {
972 compatible = "snps,dw-apb-uart";
973 reg = <0x01c28800 0x400>;
974 interrupts = <3>;
975 reg-shift = <2>;
976 reg-io-width = <4>;
977 clocks = <&ccu CLK_APB1_UART2>;
978 status = "disabled";
979 };
981 uart3: serial@1c28c00 {
982 compatible = "snps,dw-apb-uart";
983 reg = <0x01c28c00 0x400>;
984 interrupts = <4>;
985 reg-shift = <2>;
986 reg-io-width = <4>;
987 clocks = <&ccu CLK_APB1_UART3>;
988 status = "disabled";
989 };
991 uart4: serial@1c29000 {
992 compatible = "snps,dw-apb-uart";
993 reg = <0x01c29000 0x400>;
994 interrupts = <17>;
995 reg-shift = <2>;
996 reg-io-width = <4>;
997 clocks = <&ccu CLK_APB1_UART4>;
998 status = "disabled";
999 };
1001 uart5: serial@1c29400 {
1002 compatible = "snps,dw-apb-uart";
1003 reg = <0x01c29400 0x400>;
1004 interrupts = <18>;
1005 reg-shift = <2>;
1006 reg-io-width = <4>;
1007 clocks = <&ccu CLK_APB1_UART5>;
1008 status = "disabled";
1009 };
1011 uart6: serial@1c29800 {
1012 compatible = "snps,dw-apb-uart";
1013 reg = <0x01c29800 0x400>;
1014 interrupts = <19>;
1015 reg-shift = <2>;
1016 reg-io-width = <4>;
1017 clocks = <&ccu CLK_APB1_UART6>;
1018 status = "disabled";
1019 };
1021 uart7: serial@1c29c00 {
1022 compatible = "snps,dw-apb-uart";
1023 reg = <0x01c29c00 0x400>;
1024 interrupts = <20>;
1025 reg-shift = <2>;
1026 reg-io-width = <4>;
1027 clocks = <&ccu CLK_APB1_UART7>;
1028 status = "disabled";
1029 };
1031 ps20: ps2@1c2a000 {
1032 compatible = "allwinner,sun4i-a10-ps2";
1033 reg = <0x01c2a000 0x400>;
1034 interrupts = <62>;
1035 clocks = <&ccu CLK_APB1_PS20>;
1036 status = "disabled";
1037 };
1039 ps21: ps2@1c2a400 {
1040 compatible = "allwinner,sun4i-a10-ps2";
1041 reg = <0x01c2a400 0x400>;
1042 interrupts = <63>;
1043 clocks = <&ccu CLK_APB1_PS21>;
1044 status = "disabled";
1045 };
1047 i2c0: i2c@1c2ac00 {
1048 compatible = "allwinner,sun4i-a10-i2c";
1049 reg = <0x01c2ac00 0x400>;
1050 interrupts = <7>;
1051 clocks = <&ccu CLK_APB1_I2C0>;
1052 pinctrl-names = "default";
1053 pinctrl-0 = <&i2c0_pins>;
1054 status = "disabled";
1055 #address-cells = <1>;
1056 #size-cells = <0>;
1057 };
1059 i2c1: i2c@1c2b000 {
1060 compatible = "allwinner,sun4i-a10-i2c";
1061 reg = <0x01c2b000 0x400>;
1062 interrupts = <8>;
1063 clocks = <&ccu CLK_APB1_I2C1>;
1064 pinctrl-names = "default";
1065 pinctrl-0 = <&i2c1_pins>;
1066 status = "disabled";
1067 #address-cells = <1>;
1068 #size-cells = <0>;
1069 };
1071 i2c2: i2c@1c2b400 {
1072 compatible = "allwinner,sun4i-a10-i2c";
1073 reg = <0x01c2b400 0x400>;
1074 interrupts = <9>;
1075 clocks = <&ccu CLK_APB1_I2C2>;
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&i2c2_pins>;
1078 status = "disabled";
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1081 };
1083 can0: can@1c2bc00 {
1084 compatible = "allwinner,sun4i-a10-can";
1085 reg = <0x01c2bc00 0x400>;
1086 interrupts = <26>;
1087 clocks = <&ccu CLK_APB1_CAN>;
1088 status = "disabled";
1089 };
1091 mali: gpu@1c40000 {
1092 compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
1093 reg = <0x01c40000 0x10000>;
1094 interrupts = <69>,
1095 <70>,
1096 <71>,
1097 <72>,
1098 <73>;
1099 interrupt-names = "gp",
1100 "gpmmu",
1101 "pp0",
1102 "ppmmu0",
1103 "pmu";
1104 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1105 clock-names = "bus", "core";
1106 resets = <&ccu RST_GPU>;
1108 assigned-clocks = <&ccu CLK_GPU>;
1109 assigned-clock-rates = <384000000>;
1110 };
1112 fe0: display-frontend@1e00000 {
1113 compatible = "allwinner,sun4i-a10-display-frontend";
1114 reg = <0x01e00000 0x20000>;
1115 interrupts = <47>;
1116 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1117 <&ccu CLK_DRAM_DE_FE0>;
1118 clock-names = "ahb", "mod",
1119 "ram";
1120 resets = <&ccu RST_DE_FE0>;
1122 ports {
1123 #address-cells = <1>;
1124 #size-cells = <0>;
1126 fe0_out: port@1 {
1127 #address-cells = <1>;
1128 #size-cells = <0>;
1129 reg = <1>;
1131 fe0_out_be0: endpoint@0 {
1132 reg = <0>;
1133 remote-endpoint = <&be0_in_fe0>;
1134 };
1136 fe0_out_be1: endpoint@1 {
1137 reg = <1>;
1138 remote-endpoint = <&be1_in_fe0>;
1139 };
1140 };
1141 };
1142 };
1144 fe1: display-frontend@1e20000 {
1145 compatible = "allwinner,sun4i-a10-display-frontend";
1146 reg = <0x01e20000 0x20000>;
1147 interrupts = <48>;
1148 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1149 <&ccu CLK_DRAM_DE_FE1>;
1150 clock-names = "ahb", "mod",
1151 "ram";
1152 resets = <&ccu RST_DE_FE1>;
1154 ports {
1155 #address-cells = <1>;
1156 #size-cells = <0>;
1158 fe1_out: port@1 {
1159 #address-cells = <1>;
1160 #size-cells = <0>;
1161 reg = <1>;
1163 fe1_out_be0: endpoint@0 {
1164 reg = <0>;
1165 remote-endpoint = <&be0_in_fe1>;
1166 };
1168 fe1_out_be1: endpoint@1 {
1169 reg = <1>;
1170 remote-endpoint = <&be1_in_fe1>;
1171 };
1172 };
1173 };
1174 };
1176 be1: display-backend@1e40000 {
1177 compatible = "allwinner,sun4i-a10-display-backend";
1178 reg = <0x01e40000 0x10000>;
1179 interrupts = <48>;
1180 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1181 <&ccu CLK_DRAM_DE_BE1>;
1182 clock-names = "ahb", "mod",
1183 "ram";
1184 resets = <&ccu RST_DE_BE1>;
1186 ports {
1187 #address-cells = <1>;
1188 #size-cells = <0>;
1190 be1_in: port@0 {
1191 #address-cells = <1>;
1192 #size-cells = <0>;
1193 reg = <0>;
1195 be1_in_fe0: endpoint@0 {
1196 reg = <0>;
1197 remote-endpoint = <&fe0_out_be1>;
1198 };
1200 be1_in_fe1: endpoint@1 {
1201 reg = <1>;
1202 remote-endpoint = <&fe1_out_be1>;
1203 };
1204 };
1206 be1_out: port@1 {
1207 #address-cells = <1>;
1208 #size-cells = <0>;
1209 reg = <1>;
1211 be1_out_tcon0: endpoint@0 {
1212 reg = <0>;
1213 remote-endpoint = <&tcon0_in_be1>;
1214 };
1216 be1_out_tcon1: endpoint@1 {
1217 reg = <1>;
1218 remote-endpoint = <&tcon1_in_be1>;
1219 };
1220 };
1221 };
1222 };
1224 be0: display-backend@1e60000 {
1225 compatible = "allwinner,sun4i-a10-display-backend";
1226 reg = <0x01e60000 0x10000>;
1227 interrupts = <47>;
1228 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1229 <&ccu CLK_DRAM_DE_BE0>;
1230 clock-names = "ahb", "mod",
1231 "ram";
1232 resets = <&ccu RST_DE_BE0>;
1234 ports {
1235 #address-cells = <1>;
1236 #size-cells = <0>;
1238 be0_in: port@0 {
1239 #address-cells = <1>;
1240 #size-cells = <0>;
1241 reg = <0>;
1243 be0_in_fe0: endpoint@0 {
1244 reg = <0>;
1245 remote-endpoint = <&fe0_out_be0>;
1246 };
1248 be0_in_fe1: endpoint@1 {
1249 reg = <1>;
1250 remote-endpoint = <&fe1_out_be0>;
1251 };
1252 };
1254 be0_out: port@1 {
1255 #address-cells = <1>;
1256 #size-cells = <0>;
1257 reg = <1>;
1259 be0_out_tcon0: endpoint@0 {
1260 reg = <0>;
1261 remote-endpoint = <&tcon0_in_be0>;
1262 };
1264 be0_out_tcon1: endpoint@1 {
1265 reg = <1>;
1266 remote-endpoint = <&tcon1_in_be0>;
1267 };
1268 };
1269 };
1270 };
1271 };
1272 };