arch/arm/boot/dts/sun8i-a33.dtsi

   1 /*
   2  * Copyright 2014 Chen-Yu Tsai
   3  *
   4  * Chen-Yu Tsai <wens@csie.org>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "sun8i-a23-a33.dtsi"
  46 #include <dt-bindings/thermal/thermal.h>
  47
  48 / {
  49         cpu0_opp_table: opp_table0 {
  50                 compatible = "operating-points-v2";
  51                 opp-shared;
  52
  53                 opp-120000000 {
  54                         opp-hz = /bits/ 64 <120000000>;
  55                         opp-microvolt = <1040000>;
  56                         clock-latency-ns = <244144>; /* 8 32k periods */
  57                 };
  58
  59                 opp-240000000 {
  60                         opp-hz = /bits/ 64 <240000000>;
  61                         opp-microvolt = <1040000>;
  62                         clock-latency-ns = <244144>; /* 8 32k periods */
  63                 };
  64
  65                 opp-312000000 {
  66                         opp-hz = /bits/ 64 <312000000>;
  67                         opp-microvolt = <1040000>;
  68                         clock-latency-ns = <244144>; /* 8 32k periods */
  69                 };
  70
  71                 opp-408000000 {
  72                         opp-hz = /bits/ 64 <408000000>;
  73                         opp-microvolt = <1040000>;
  74                         clock-latency-ns = <244144>; /* 8 32k periods */
  75                 };
  76
  77                 opp-480000000 {
  78                         opp-hz = /bits/ 64 <480000000>;
  79                         opp-microvolt = <1040000>;
  80                         clock-latency-ns = <244144>; /* 8 32k periods */
  81                 };
  82
  83                 opp-504000000 {
  84                         opp-hz = /bits/ 64 <504000000>;
  85                         opp-microvolt = <1040000>;
  86                         clock-latency-ns = <244144>; /* 8 32k periods */
  87                 };
  88
  89                 opp-600000000 {
  90                         opp-hz = /bits/ 64 <600000000>;
  91                         opp-microvolt = <1040000>;
  92                         clock-latency-ns = <244144>; /* 8 32k periods */
  93                 };
  94
  95                 opp-648000000 {
  96                         opp-hz = /bits/ 64 <648000000>;
  97                         opp-microvolt = <1040000>;
  98                         clock-latency-ns = <244144>; /* 8 32k periods */
  99                 };
 100
 101                 opp-720000000 {
 102                         opp-hz = /bits/ 64 <720000000>;
 103                         opp-microvolt = <1100000>;
 104                         clock-latency-ns = <244144>; /* 8 32k periods */
 105                 };
 106
 107                 opp-816000000 {
 108                         opp-hz = /bits/ 64 <816000000>;
 109                         opp-microvolt = <1100000>;
 110                         clock-latency-ns = <244144>; /* 8 32k periods */
 111                 };
 112
 113                 opp-912000000 {
 114                         opp-hz = /bits/ 64 <912000000>;
 115                         opp-microvolt = <1200000>;
 116                         clock-latency-ns = <244144>; /* 8 32k periods */
 117                 };
 118
 119                 opp-1008000000 {
 120                         opp-hz = /bits/ 64 <1008000000>;
 121                         opp-microvolt = <1200000>;
 122                         clock-latency-ns = <244144>; /* 8 32k periods */
 123                 };
 124         };
 125
 126         cpus {
 127                 cpu@0 {
 128                         clocks = <&ccu CLK_CPUX>;
 129                         clock-names = "cpu";
 130                         operating-points-v2 = <&cpu0_opp_table>;
 131                         #cooling-cells = <2>;
 132                 };
 133
 134                 cpu1: cpu@1 {
 135                         clocks = <&ccu CLK_CPUX>;
 136                         clock-names = "cpu";
 137                         operating-points-v2 = <&cpu0_opp_table>;
 138                         #cooling-cells = <2>;
 139                 };
 140
 141                 cpu2: cpu@2 {
 142                         compatible = "arm,cortex-a7";
 143                         device_type = "cpu";
 144                         reg = <2>;
 145                         clocks = <&ccu CLK_CPUX>;
 146                         clock-names = "cpu";
 147                         operating-points-v2 = <&cpu0_opp_table>;
 148                         #cooling-cells = <2>;
 149                 };
 150
 151                 cpu3: cpu@3 {
 152                         compatible = "arm,cortex-a7";
 153                         device_type = "cpu";
 154                         reg = <3>;
 155                         clocks = <&ccu CLK_CPUX>;
 156                         clock-names = "cpu";
 157                         operating-points-v2 = <&cpu0_opp_table>;
 158                         #cooling-cells = <2>;
 159                 };
 160         };
 161
 162         iio-hwmon {
 163                 compatible = "iio-hwmon";
 164                 io-channels = <&ths>;
 165         };
 166
 167         mali_opp_table: gpu-opp-table {
 168                 compatible = "operating-points-v2";
 169
 170                 opp-144000000 {
 171                         opp-hz = /bits/ 64 <144000000>;
 172                 };
 173
 174                 opp-240000000 {
 175                         opp-hz = /bits/ 64 <240000000>;
 176                 };
 177
 178                 opp-384000000 {
 179                         opp-hz = /bits/ 64 <384000000>;
 180                 };
 181         };
 182
 183         sound: sound {
 184                 compatible = "simple-audio-card";
 185                 simple-audio-card,name = "sun8i-a33-audio";
 186                 simple-audio-card,format = "i2s";
 187                 simple-audio-card,frame-master = <&link_codec>;
 188                 simple-audio-card,bitclock-master = <&link_codec>;
 189                 simple-audio-card,mclk-fs = <128>;
 190                 simple-audio-card,aux-devs = <&codec_analog>;
 191                 simple-audio-card,routing =
 192                         "Left DAC", "AIF1 Slot 0 Left",
 193                         "Right DAC", "AIF1 Slot 0 Right";
 194                 status = "disabled";
 195
 196                 simple-audio-card,cpu {
 197                         sound-dai = <&dai>;
 198                 };
 199
 200                 link_codec: simple-audio-card,codec {
 201                         sound-dai = <&codec>;
 202                 };
 203         };
 204
 205         soc {
 206                 video-codec@1c0e000 {
 207                         compatible = "allwinner,sun8i-a33-video-engine";
 208                         reg = <0x01c0e000 0x1000>;
 209                         clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
 210                                  <&ccu CLK_DRAM_VE>;
 211                         clock-names = "ahb", "mod", "ram";
 212                         resets = <&ccu RST_BUS_VE>;
 213                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 214                         allwinner,sram = <&ve_sram 1>;
 215                 };
 216
 217                 crypto: crypto-engine@1c15000 {
 218                         compatible = "allwinner,sun8i-a33-crypto";
 219                         reg = <0x01c15000 0x1000>;
 220                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 221                         clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
 222                         clock-names = "ahb", "mod";
 223                         resets = <&ccu RST_BUS_SS>;
 224                         reset-names = "ahb";
 225                 };
 226
 227                 dai: dai@1c22c00 {
 228                         #sound-dai-cells = <0>;
 229                         compatible = "allwinner,sun6i-a31-i2s";
 230                         reg = <0x01c22c00 0x200>;
 231                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 232                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 233                         clock-names = "apb", "mod";
 234                         resets = <&ccu RST_BUS_CODEC>;
 235                         dmas = <&dma 15>, <&dma 15>;
 236                         dma-names = "rx", "tx";
 237                         status = "disabled";
 238                 };
 239
 240                 codec: codec@1c22e00 {
 241                         #sound-dai-cells = <0>;
 242                         compatible = "allwinner,sun8i-a33-codec";
 243                         reg = <0x01c22e00 0x400>;
 244                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 245                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 246                         clock-names = "bus", "mod";
 247                         status = "disabled";
 248                 };
 249
 250                 ths: ths@1c25000 {
 251                         compatible = "allwinner,sun8i-a33-ths";
 252                         reg = <0x01c25000 0x100>;
 253                         #thermal-sensor-cells = <0>;
 254                         #io-channel-cells = <0>;
 255                 };
 256
 257                 dsi: dsi@1ca0000 {
 258                         compatible = "allwinner,sun6i-a31-mipi-dsi";
 259                         reg = <0x01ca0000 0x1000>;
 260                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 261                         clocks = <&ccu CLK_BUS_MIPI_DSI>,
 262                                  <&ccu CLK_DSI_SCLK>;
 263                         clock-names = "bus", "mod";
 264                         resets = <&ccu RST_BUS_MIPI_DSI>;
 265                         phys = <&dphy>;
 266                         phy-names = "dphy";
 267                         status = "disabled";
 268                         #address-cells = <1>;
 269                         #size-cells = <0>;
 270
 271                         port {
 272                                 dsi_in_tcon0: endpoint {
 273                                         remote-endpoint = <&tcon0_out_dsi>;
 274                                 };
 275                         };
 276                 };
 277
 278                 dphy: d-phy@1ca1000 {
 279                         compatible = "allwinner,sun6i-a31-mipi-dphy";
 280                         reg = <0x01ca1000 0x1000>;
 281                         clocks = <&ccu CLK_BUS_MIPI_DSI>,
 282                                  <&ccu CLK_DSI_DPHY>;
 283                         clock-names = "bus", "mod";
 284                         resets = <&ccu RST_BUS_MIPI_DSI>;
 285                         status = "disabled";
 286                         #phy-cells = <0>;
 287                 };
 288         };
 289
 290         thermal-zones {
 291                 cpu_thermal {
 292                         /* milliseconds */
 293                         polling-delay-passive = <250>;
 294                         polling-delay = <1000>;
 295                         thermal-sensors = <&ths>;
 296
 297                         cooling-maps {
 298                                 map0 {
 299                                         trip = <&cpu_alert0>;
 300                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 301                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 302                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 303                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 304                                 };
 305                                 map1 {
 306                                         trip = <&cpu_alert1>;
 307                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 308                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 309                                                          <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 310                                                          <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 311                                 };
 312
 313                                 map2 {
 314                                         trip = <&gpu_alert0>;
 315                                         cooling-device = <&mali 1 THERMAL_NO_LIMIT>;
 316                                 };
 317
 318                                 map3 {
 319                                         trip = <&gpu_alert1>;
 320                                         cooling-device = <&mali 2 THERMAL_NO_LIMIT>;
 321                                 };
 322                         };
 323
 324                         trips {
 325                                 cpu_alert0: cpu_alert0 {
 326                                         /* milliCelsius */
 327                                         temperature = <75000>;
 328                                         hysteresis = <2000>;
 329                                         type = "passive";
 330                                 };
 331
 332                                 gpu_alert0: gpu_alert0 {
 333                                         /* milliCelsius */
 334                                         temperature = <85000>;
 335                                         hysteresis = <2000>;
 336                                         type = "passive";
 337                                 };
 338
 339                                 cpu_alert1: cpu_alert1 {
 340                                         /* milliCelsius */
 341                                         temperature = <90000>;
 342                                         hysteresis = <2000>;
 343                                         type = "hot";
 344                                 };
 345
 346                                 gpu_alert1: gpu_alert1 {
 347                                         /* milliCelsius */
 348                                         temperature = <95000>;
 349                                         hysteresis = <2000>;
 350                                         type = "hot";
 351                                 };
 352
 353                                 cpu_crit: cpu_crit {
 354                                         /* milliCelsius */
 355                                         temperature = <110000>;
 356                                         hysteresis = <2000>;
 357                                         type = "critical";
 358                                 };
 359                         };
 360                 };
 361         };
 362 };
 363
 364 &be0 {
 365         compatible = "allwinner,sun8i-a33-display-backend";
 366         /* A33 has an extra "SAT" module packed inside the display backend */
 367         reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
 368         reg-names = "be", "sat";
 369         clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
 370                  <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
 371         clock-names = "ahb", "mod",
 372                       "ram", "sat";
 373         resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
 374         reset-names = "be", "sat";
 375         assigned-clocks = <&ccu CLK_DE_BE>;
 376         assigned-clock-rates = <300000000>;
 377 };
 378
 379 &ccu {
 380         compatible = "allwinner,sun8i-a33-ccu";
 381 };
 382
 383 &de {
 384         compatible = "allwinner,sun8i-a33-display-engine";
 385 };
 386
 387 &drc0 {
 388         compatible = "allwinner,sun8i-a33-drc";
 389 };
 390
 391 &fe0 {
 392         compatible = "allwinner,sun8i-a33-display-frontend";
 393 };
 394
 395 &mali {
 396         operating-points-v2 = <&mali_opp_table>;
 397 };
 398
 399 &pio {
 400         compatible = "allwinner,sun8i-a33-pinctrl";
 401         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 402                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 403
 404         uart0_pb_pins: uart0-pb-pins {
 405                 pins = "PB0", "PB1";
 406                 function = "uart0";
 407         };
 408
 409 };
 410
 411 &tcon0 {
 412         compatible = "allwinner,sun8i-a33-tcon";
 413 };
 414
 415 &tcon0_out {
 416         #address-cells = <1>;
 417         #size-cells = <0>;
 418
 419         tcon0_out_dsi: endpoint@1 {
 420                 reg = <1>;
 421                 remote-endpoint = <&dsi_in_tcon0>;
 422         };
 423 };
 424
 425 &usb_otg {
 426         compatible = "allwinner,sun8i-a33-musb";
 427 };
 428
 429 &usbphy {
 430         compatible = "allwinner,sun8i-a33-usb-phy";
 431         reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
 432         reg-names = "phy_ctrl", "pmu1";
 433 };