arch/arm/boot/dts/vf610-zii-dev-rev-c.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
   4  */
   5
   6 /dts-v1/;
   7 #include "vf610-zii-dev.dtsi"
   8
   9 / {
  10         model = "ZII VF610 Development Board, Rev C";
  11         compatible = "zii,vf610dev-c", "zii,vf610dev", "fsl,vf610";
  12
  13         mdio-mux {
  14                 compatible = "mdio-mux-gpio";
  15                 pinctrl-0 = <&pinctrl_mdio_mux>;
  16                 pinctrl-names = "default";
  17                 gpios = <&gpio0 8  GPIO_ACTIVE_HIGH
  18                          &gpio0 9  GPIO_ACTIVE_HIGH
  19                          &gpio0 25 GPIO_ACTIVE_HIGH>;
  20                 mdio-parent-bus = <&mdio1>;
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 mdio_mux_1: mdio@1 {
  25                         reg = <1>;
  26                         #address-cells = <1>;
  27                         #size-cells = <0>;
  28
  29                         switch0: switch@0 {
  30                                 compatible = "marvell,mv88e6190";
  31                                 pinctrl-0 = <&pinctrl_gpio_switch0>;
  32                                 pinctrl-names = "default";
  33                                 reg = <0>;
  34                                 dsa,member = <0 0>;
  35                                 eeprom-length = <65536>;
  36                                 interrupt-parent = <&gpio0>;
  37                                 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
  38                                 interrupt-controller;
  39                                 #interrupt-cells = <2>;
  40
  41                                 ports {
  42                                         #address-cells = <1>;
  43                                         #size-cells = <0>;
  44
  45                                         port@0 {
  46                                                 reg = <0>;
  47                                                 label = "cpu";
  48                                                 ethernet = <&fec1>;
  49
  50                                                 fixed-link {
  51                                                         speed = <100>;
  52                                                         full-duplex;
  53                                                 };
  54                                         };
  55
  56                                         port@1 {
  57                                                 reg = <1>;
  58                                                 label = "lan1";
  59                                                 phy-handle = <&switch0phy1>;
  60                                         };
  61
  62                                         port@2 {
  63                                                 reg = <2>;
  64                                                 label = "lan2";
  65                                                 phy-handle = <&switch0phy2>;
  66                                         };
  67
  68                                         port@3 {
  69                                                 reg = <3>;
  70                                                 label = "lan3";
  71                                                 phy-handle = <&switch0phy3>;
  72                                         };
  73
  74                                         port@4 {
  75                                                 reg = <4>;
  76                                                 label = "lan4";
  77                                                 phy-handle = <&switch0phy4>;
  78                                         };
  79
  80                                         switch0port10: port@10 {
  81                                                 reg = <10>;
  82                                                 label = "dsa";
  83                                                 phy-mode = "xaui";
  84                                                 link = <&switch1port10>;
  85                                         };
  86                                 };
  87
  88                                 mdio {
  89                                         #address-cells = <1>;
  90                                         #size-cells = <0>;
  91
  92                                         switch0phy1: switch0phy@1 {
  93                                                 reg = <1>;
  94                                                 interrupt-parent = <&switch0>;
  95                                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
  96                                         };
  97
  98                                         switch0phy2: switch0phy@2 {
  99                                                 reg = <2>;
 100                                                 interrupt-parent = <&switch0>;
 101                                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 102                                         };
 103
 104                                         switch0phy3: switch0phy@3 {
 105                                                 reg = <3>;
 106                                                 interrupt-parent = <&switch0>;
 107                                                 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 108                                         };
 109
 110                                         switch0phy4: switch0phy@4 {
 111                                                 reg = <4>;
 112                                                 interrupt-parent = <&switch0>;
 113                                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 114                                         };
 115                                 };
 116                         };
 117                 };
 118
 119                 mdio_mux_2: mdio@2 {
 120                         reg = <2>;
 121                         #address-cells = <1>;
 122                         #size-cells = <0>;
 123
 124                         switch1: switch@0 {
 125                                 compatible = "marvell,mv88e6190";
 126                                 pinctrl-0 = <&pinctrl_gpio_switch1>;
 127                                 pinctrl-names = "default";
 128                                 reg = <0>;
 129                                 dsa,member = <0 1>;
 130                                 eeprom-length = <65536>;
 131                                 interrupt-parent = <&gpio0>;
 132                                 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
 133                                 interrupt-controller;
 134                                 #interrupt-cells = <2>;
 135
 136                                 ports {
 137                                         #address-cells = <1>;
 138                                         #size-cells = <0>;
 139
 140                                         port@1 {
 141                                                 reg = <1>;
 142                                                 label = "lan5";
 143                                                 phy-handle = <&switch1phy1>;
 144                                         };
 145
 146                                         port@2 {
 147                                                 reg = <2>;
 148                                                 label = "lan6";
 149                                                 phy-handle = <&switch1phy2>;
 150                                         };
 151
 152                                         port@3 {
 153                                                 reg = <3>;
 154                                                 label = "lan7";
 155                                                 phy-handle = <&switch1phy3>;
 156                                         };
 157
 158                                         port@4 {
 159                                                 reg = <4>;
 160                                                 label = "lan8";
 161                                                 phy-handle = <&switch1phy4>;
 162                                         };
 163
 164                                         port@9 {
 165                                                 reg = <9>;
 166                                                 label = "sff2";
 167                                                 phy-mode = "sgmii";
 168                                                 managed = "in-band-status";
 169                                                 sfp = <&sff2>;
 170                                         };
 171
 172                                         switch1port10: port@10 {
 173                                                 reg = <10>;
 174                                                 label = "dsa";
 175                                                 phy-mode = "xaui";
 176                                                 link = <&switch0port10>;
 177                                         };
 178                                 };
 179                                 mdio {
 180                                         #address-cells = <1>;
 181                                         #size-cells = <0>;
 182
 183                                         switch1phy1: switch1phy@1 {
 184                                                 reg = <1>;
 185                                                 interrupt-parent = <&switch1>;
 186                                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 187                                         };
 188
 189                                         switch1phy2: switch1phy@2 {
 190                                                 reg = <2>;
 191                                                 interrupt-parent = <&switch1>;
 192                                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 193                                         };
 194
 195                                         switch1phy3: switch1phy@3 {
 196                                                 reg = <3>;
 197                                                 interrupt-parent = <&switch1>;
 198                                                 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 199                                         };
 200
 201                                         switch1phy4: switch1phy@4 {
 202                                                 reg = <4>;
 203                                                 interrupt-parent = <&switch1>;
 204                                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 205                                         };
 206                                 };
 207                         };
 208                 };
 209
 210                 mdio_mux_4: mdio@4 {
 211                         reg = <4>;
 212                         #address-cells = <1>;
 213                         #size-cells = <0>;
 214                 };
 215         };
 216
 217         sff2: sff2 {
 218                 /* lower */
 219                 compatible = "sff,sff";
 220                 i2c-bus = <&sff2_i2c>;
 221                 los-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
 222                 tx-disable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
 223         };
 224
 225         sff3: sff3 {
 226                 /* upper */
 227                 compatible = "sff,sff";
 228                 i2c-bus = <&sff3_i2c>;
 229                 los-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
 230                 tx-disable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
 231         };
 232 };
 233
 234 &dspi0 {
 235         bus-num = <0>;
 236         pinctrl-names = "default";
 237         pinctrl-0 = <&pinctrl_dspi0>;
 238         status = "okay";
 239         spi-num-chipselects = <2>;
 240
 241         flash@0 {
 242                 compatible = "m25p128", "jedec,spi-nor";
 243                 #address-cells = <1>;
 244                 #size-cells = <1>;
 245                 reg = <0>;
 246                 spi-max-frequency = <1000000>;
 247         };
 248
 249         atzb-rf-233@1 {
 250                 compatible = "atmel,at86rf233";
 251
 252                 pinctrl-names = "default";
 253                 pinctrl-0 = <&pinctr_atzb_rf_233>;
 254
 255                 spi-max-frequency = <7500000>;
 256                 reg = <1>;
 257                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 258                 interrupt-parent = <&gpio3>;
 259                 xtal-trim = /bits/ 8 <0x06>;
 260
 261                 sleep-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
 262                 reset-gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>;
 263
 264                 fsl,spi-cs-sck-delay = <180>;
 265                 fsl,spi-sck-cs-delay = <250>;
 266         };
 267 };
 268
 269 &i2c0 {
 270         /*
 271          * U712
 272          *
 273          * Exposed signals:
 274          *    P1 - WE2_CMD
 275          *    P2 - WE2_CLK
 276          */
 277         gpio5: io-expander@18 {
 278                 compatible = "nxp,pca9557";
 279                 reg = <0x18>;
 280                 gpio-controller;
 281                 #gpio-cells = <2>;
 282         };
 283
 284         /*
 285          * U121
 286          *
 287          * Exposed signals:
 288          *    I/O0  - ENET_SWR_EN
 289          *    I/O1  - ESW1_RESETn
 290          *    I/O2  - ARINC_RESET
 291          *    I/O3  - DD1_IO_RESET
 292          *    I/O4  - ESW2_RESETn
 293          *    I/O5  - ESW3_RESETn
 294          *    I/O6  - ESW4_RESETn
 295          *    I/O8  - TP909
 296          *    I/O9  - FEM_SEL
 297          *    I/O10 - WIFI_RESETn
 298          *    I/O11 - PHY_RSTn
 299          *    I/O12 - OPT1_SD
 300          *    I/O13 - OPT2_SD
 301          *    I/O14 - OPT1_TX_DIS
 302          *    I/O15 - OPT2_TX_DIS
 303          */
 304         gpio6: sx1503@20 {
 305                 compatible = "semtech,sx1503q";
 306
 307                 pinctrl-names = "default";
 308                 pinctrl-0 = <&pinctrl_sx1503_20>;
 309                 #gpio-cells = <2>;
 310                 #interrupt-cells = <2>;
 311                 reg = <0x20>;
 312                 interrupt-parent = <&gpio0>;
 313                 interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
 314                 gpio-controller;
 315                 interrupt-controller;
 316         };
 317
 318         /*
 319          * U715
 320          *
 321          * Exposed signals:
 322          *     IO0 - WE1_CLK
 323          *     IO1 - WE1_CMD
 324          */
 325         gpio7: io-expander@22 {
 326                 compatible = "nxp,pca9554";
 327                 reg = <0x22>;
 328                 gpio-controller;
 329                 #gpio-cells = <2>;
 330
 331         };
 332 };
 333
 334 &i2c1 {
 335         eeprom@50 {
 336                 compatible = "atmel,24c02";
 337                 reg = <0x50>;
 338                 read-only;
 339         };
 340 };
 341
 342 &i2c2 {
 343         tca9548@70 {
 344                 compatible = "nxp,pca9548";
 345                 pinctrl-0 = <&pinctrl_i2c_mux_reset>;
 346                 pinctrl-names = "default";
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 reg = <0x70>;
 350                 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 351
 352                 i2c@0 {
 353                         #address-cells = <1>;
 354                         #size-cells = <0>;
 355                         reg = <0>;
 356                 };
 357
 358                 sff2_i2c: i2c@1 {
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         reg = <1>;
 362                 };
 363
 364                 sff3_i2c: i2c@2 {
 365                         #address-cells = <1>;
 366                         #size-cells = <0>;
 367                         reg = <2>;
 368                 };
 369
 370                 i2c@3 {
 371                         #address-cells = <1>;
 372                         #size-cells = <0>;
 373                         reg = <3>;
 374                 };
 375         };
 376 };
 377
 378 &uart3 {
 379         pinctrl-names = "default";
 380         pinctrl-0 = <&pinctrl_uart3>;
 381         status = "okay";
 382 };
 383
 384 &gpio0 {
 385         eth0_intrp {
 386                 gpio-hog;
 387                 gpios = <23 GPIO_ACTIVE_HIGH>;
 388                 input;
 389                 line-name = "sx1503-irq";
 390         };
 391 };
 392
 393 &gpio3 {
 394         eth0_intrp {
 395                 gpio-hog;
 396                 gpios = <2 GPIO_ACTIVE_HIGH>;
 397                 input;
 398                 line-name = "eth0-intrp";
 399         };
 400 };
 401
 402 &fec0 {
 403         mdio {
 404                 #address-cells = <1>;
 405                 #size-cells = <0>;
 406                 status = "okay";
 407
 408                 ethernet-phy@0 {
 409                         compatible = "ethernet-phy-ieee802.3-c22";
 410
 411                         pinctrl-names = "default";
 412                         pinctrl-0 = <&pinctrl_fec0_phy_int>;
 413
 414                         interrupt-parent = <&gpio3>;
 415                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 416                         reg = <0>;
 417                 };
 418         };
 419 };
 420
 421 &iomuxc {
 422         pinctr_atzb_rf_233: pinctrl-atzb-rf-233 {
 423                 fsl,pins = <
 424                         VF610_PAD_PTB2__GPIO_24         0x31c2
 425                         VF610_PAD_PTE27__GPIO_132       0x33e2
 426                 >;
 427         };
 428
 429
 430         pinctrl_sx1503_20: pinctrl-sx1503-20 {
 431                 fsl,pins = <
 432                         VF610_PAD_PTB1__GPIO_23         0x219d
 433                 >;
 434         };
 435
 436         pinctrl_uart3: uart3grp {
 437                 fsl,pins = <
 438                         VF610_PAD_PTA20__UART3_TX       0x21a2
 439                         VF610_PAD_PTA21__UART3_RX       0x21a1
 440                 >;
 441         };
 442
 443         pinctrl_mdio_mux: pinctrl-mdio-mux {
 444                 fsl,pins = <
 445                         VF610_PAD_PTA18__GPIO_8         0x31c2
 446                         VF610_PAD_PTA19__GPIO_9         0x31c2
 447                         VF610_PAD_PTB3__GPIO_25         0x31c2
 448                 >;
 449         };
 450
 451         pinctrl_fec0_phy_int: pinctrl-fec0-phy-int {
 452                 fsl,pins = <
 453                         VF610_PAD_PTB28__GPIO_98        0x219d
 454                 >;
 455         };
 456 };