| blob | 68cd9d3fc82b825a26ffb8b4ea98d0081c15d958 |
1 /*
2 * DaVinci Power & Sleep Controller (PSC) defines
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 */
27 #ifndef __ASM_ARCH_PSC_H
28 #define __ASM_ARCH_PSC_H
30 /* Power and Sleep Controller (PSC) Domains */
31 #define DAVINCI_GPSC_ARMDOMAIN 0
32 #define DAVINCI_GPSC_DSPDOMAIN 1
34 #define DAVINCI_LPSC_VPSSMSTR 0
35 #define DAVINCI_LPSC_VPSSSLV 1
36 #define DAVINCI_LPSC_TPCC 2
37 #define DAVINCI_LPSC_TPTC0 3
38 #define DAVINCI_LPSC_TPTC1 4
39 #define DAVINCI_LPSC_EMAC 5
40 #define DAVINCI_LPSC_EMAC_WRAPPER 6
41 #define DAVINCI_LPSC_USB 9
42 #define DAVINCI_LPSC_ATA 10
43 #define DAVINCI_LPSC_VLYNQ 11
44 #define DAVINCI_LPSC_UHPI 12
45 #define DAVINCI_LPSC_DDR_EMIF 13
46 #define DAVINCI_LPSC_AEMIF 14
47 #define DAVINCI_LPSC_MMC_SD 15
48 #define DAVINCI_LPSC_McBSP 17
49 #define DAVINCI_LPSC_I2C 18
50 #define DAVINCI_LPSC_UART0 19
51 #define DAVINCI_LPSC_UART1 20
52 #define DAVINCI_LPSC_UART2 21
53 #define DAVINCI_LPSC_SPI 22
54 #define DAVINCI_LPSC_PWM0 23
55 #define DAVINCI_LPSC_PWM1 24
56 #define DAVINCI_LPSC_PWM2 25
57 #define DAVINCI_LPSC_GPIO 26
58 #define DAVINCI_LPSC_TIMER0 27
59 #define DAVINCI_LPSC_TIMER1 28
60 #define DAVINCI_LPSC_TIMER2 29
61 #define DAVINCI_LPSC_SYSTEM_SUBSYS 30
62 #define DAVINCI_LPSC_ARM 31
63 #define DAVINCI_LPSC_SCR2 32
64 #define DAVINCI_LPSC_SCR3 33
65 #define DAVINCI_LPSC_SCR4 34
66 #define DAVINCI_LPSC_CROSSBAR 35
67 #define DAVINCI_LPSC_CFG27 36
68 #define DAVINCI_LPSC_CFG3 37
69 #define DAVINCI_LPSC_CFG5 38
70 #define DAVINCI_LPSC_GEM 39
71 #define DAVINCI_LPSC_IMCOP 40
73 #define DM355_LPSC_TIMER3 5
74 #define DM355_LPSC_SPI1 6
75 #define DM355_LPSC_MMC_SD1 7
76 #define DM355_LPSC_McBSP1 8
77 #define DM355_LPSC_PWM3 10
78 #define DM355_LPSC_SPI2 11
79 #define DM355_LPSC_RTO 12
80 #define DM355_LPSC_VPSS_DAC 41
82 /* DM365 */
83 #define DM365_LPSC_TIMER3 5
84 #define DM365_LPSC_SPI1 6
85 #define DM365_LPSC_MMC_SD1 7
86 #define DM365_LPSC_McBSP1 8
87 #define DM365_LPSC_PWM3 10
88 #define DM365_LPSC_SPI2 11
89 #define DM365_LPSC_RTO 12
90 #define DM365_LPSC_TIMER4 17
91 #define DM365_LPSC_SPI0 22
92 #define DM365_LPSC_SPI3 38
93 #define DM365_LPSC_SPI4 39
94 #define DM365_LPSC_EMAC 40
95 #define DM365_LPSC_VOICE_CODEC 44
96 #define DM365_LPSC_DAC_CLK 46
97 #define DM365_LPSC_VPSSMSTR 47
98 #define DM365_LPSC_MJCP 50
100 /*
101 * LPSC Assignments
102 */
103 #define DM646X_LPSC_ARM 0
104 #define DM646X_LPSC_C64X_CPU 1
105 #define DM646X_LPSC_HDVICP0 2
106 #define DM646X_LPSC_HDVICP1 3
107 #define DM646X_LPSC_TPCC 4
108 #define DM646X_LPSC_TPTC0 5
109 #define DM646X_LPSC_TPTC1 6
110 #define DM646X_LPSC_TPTC2 7
111 #define DM646X_LPSC_TPTC3 8
112 #define DM646X_LPSC_PCI 13
113 #define DM646X_LPSC_EMAC 14
114 #define DM646X_LPSC_VDCE 15
115 #define DM646X_LPSC_VPSSMSTR 16
116 #define DM646X_LPSC_VPSSSLV 17
117 #define DM646X_LPSC_TSIF0 18
118 #define DM646X_LPSC_TSIF1 19
119 #define DM646X_LPSC_DDR_EMIF 20
120 #define DM646X_LPSC_AEMIF 21
121 #define DM646X_LPSC_McASP0 22
122 #define DM646X_LPSC_McASP1 23
123 #define DM646X_LPSC_CRGEN0 24
124 #define DM646X_LPSC_CRGEN1 25
125 #define DM646X_LPSC_UART0 26
126 #define DM646X_LPSC_UART1 27
127 #define DM646X_LPSC_UART2 28
128 #define DM646X_LPSC_PWM0 29
129 #define DM646X_LPSC_PWM1 30
130 #define DM646X_LPSC_I2C 31
131 #define DM646X_LPSC_SPI 32
132 #define DM646X_LPSC_GPIO 33
133 #define DM646X_LPSC_TIMER0 34
134 #define DM646X_LPSC_TIMER1 35
135 #define DM646X_LPSC_ARM_INTC 45
137 /* PSC0 defines */
138 #define DA8XX_LPSC0_TPCC 0
139 #define DA8XX_LPSC0_TPTC0 1
140 #define DA8XX_LPSC0_TPTC1 2
141 #define DA8XX_LPSC0_EMIF25 3
142 #define DA8XX_LPSC0_SPI0 4
143 #define DA8XX_LPSC0_MMC_SD 5
144 #define DA8XX_LPSC0_AINTC 6
145 #define DA8XX_LPSC0_ARM_RAM_ROM 7
146 #define DA8XX_LPSC0_SECU_MGR 8
147 #define DA8XX_LPSC0_UART0 9
148 #define DA8XX_LPSC0_SCR0_SS 10
149 #define DA8XX_LPSC0_SCR1_SS 11
150 #define DA8XX_LPSC0_SCR2_SS 12
151 #define DA8XX_LPSC0_PRUSS 13
152 #define DA8XX_LPSC0_ARM 14
153 #define DA8XX_LPSC0_GEM 15
155 /* PSC1 defines */
156 #define DA850_LPSC1_TPCC1 0
157 #define DA8XX_LPSC1_USB20 1
158 #define DA8XX_LPSC1_USB11 2
159 #define DA8XX_LPSC1_GPIO 3
160 #define DA8XX_LPSC1_UHPI 4
161 #define DA8XX_LPSC1_CPGMAC 5
162 #define DA8XX_LPSC1_EMIF3C 6
163 #define DA8XX_LPSC1_McASP0 7
164 #define DA830_LPSC1_McASP1 8
165 #define DA850_LPSC1_SATA 8
166 #define DA830_LPSC1_McASP2 9
167 #define DA850_LPSC1_VPIF 9
168 #define DA8XX_LPSC1_SPI1 10
169 #define DA8XX_LPSC1_I2C 11
170 #define DA8XX_LPSC1_UART1 12
171 #define DA8XX_LPSC1_UART2 13
172 #define DA850_LPSC1_McBSP0 14
173 #define DA850_LPSC1_McBSP1 15
174 #define DA8XX_LPSC1_LCDC 16
175 #define DA8XX_LPSC1_PWM 17
176 #define DA850_LPSC1_MMC_SD1 18
177 #define DA8XX_LPSC1_ECAP 20
178 #define DA830_LPSC1_EQEP 21
179 #define DA850_LPSC1_TPTC2 21
180 #define DA8XX_LPSC1_SCR_P0_SS 24
181 #define DA8XX_LPSC1_SCR_P1_SS 25
182 #define DA8XX_LPSC1_CR_P3_SS 26
183 #define DA8XX_LPSC1_L3_CBA_RAM 31
185 /* PSC register offsets */
186 #define EPCPR 0x070
187 #define PTCMD 0x120
188 #define PTSTAT 0x128
189 #define PDSTAT 0x200
190 #define PDCTL 0x300
191 #define MDSTAT 0x800
192 #define MDCTL 0xA00
194 /* PSC module states */
195 #define PSC_STATE_SWRSTDISABLE 0
196 #define PSC_STATE_SYNCRST 1
197 #define PSC_STATE_DISABLE 2
198 #define PSC_STATE_ENABLE 3
200 #define MDSTAT_STATE_MASK 0x3f
201 #define PDSTAT_STATE_MASK 0x1f
202 #define MDCTL_LRST BIT(8)
203 #define MDCTL_FORCE BIT(31)
204 #define PDCTL_NEXT BIT(0)
205 #define PDCTL_EPCGOOD BIT(8)