arch/arm/mach-mmp/pm-pxa910.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * PXA910 Power Management Routines
   4  *
   5  * (C) Copyright 2009 Marvell International Ltd.
   6  * All Rights Reserved
   7  */
   8
   9 #ifndef __PXA910_PM_H__
  10 #define __PXA910_PM_H__
  11
  12 #define APMU_MOH_IDLE_CFG                       APMU_REG(0x0018)
  13 #define APMU_MOH_IDLE_CFG_MOH_IDLE              (1 << 1)
  14 #define APMU_MOH_IDLE_CFG_MOH_PWRDWN            (1 << 5)
  15 #define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN       (1 << 6)
  16 #define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x)         (((x) & 0x3) << 16)
  17 #define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x)      (((x) & 0x3) << 18)
  18 #define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ     (1 << 21)
  19 #define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN        (1 << 20)
  20
  21 #define APMU_SQU_CLK_GATE_CTRL                  APMU_REG(0x001c)
  22 #define APMU_MC_HW_SLP_TYPE                     APMU_REG(0x00b0)
  23
  24 #define MPMU_FCCR                               MPMU_REG(0x0008)
  25 #define MPMU_APCR                               MPMU_REG(0x1000)
  26 #define MPMU_APCR_AXISD                         (1 << 31)
  27 #define MPMU_APCR_DSPSD                         (1 << 30)
  28 #define MPMU_APCR_SLPEN                         (1 << 29)
  29 #define MPMU_APCR_DTCMSD                        (1 << 28)
  30 #define MPMU_APCR_DDRCORSD                      (1 << 27)
  31 #define MPMU_APCR_APBSD                         (1 << 26)
  32 #define MPMU_APCR_BBSD                          (1 << 25)
  33 #define MPMU_APCR_SLPWP0                        (1 << 23)
  34 #define MPMU_APCR_SLPWP1                        (1 << 22)
  35 #define MPMU_APCR_SLPWP2                        (1 << 21)
  36 #define MPMU_APCR_SLPWP3                        (1 << 20)
  37 #define MPMU_APCR_VCTCXOSD                      (1 << 19)
  38 #define MPMU_APCR_SLPWP4                        (1 << 18)
  39 #define MPMU_APCR_SLPWP5                        (1 << 17)
  40 #define MPMU_APCR_SLPWP6                        (1 << 16)
  41 #define MPMU_APCR_SLPWP7                        (1 << 15)
  42 #define MPMU_APCR_MSASLPEN                      (1 << 14)
  43 #define MPMU_APCR_STBYEN                        (1 << 13)
  44
  45 #define MPMU_AWUCRM                             MPMU_REG(0x104c)
  46 #define MPMU_AWUCRM_AP_ASYNC_INT                (1 << 25)
  47 #define MPMU_AWUCRM_AP_FULL_IDLE                (1 << 24)
  48 #define MPMU_AWUCRM_SDH1                        (1 << 23)
  49 #define MPMU_AWUCRM_SDH2                        (1 << 22)
  50 #define MPMU_AWUCRM_KEYPRESS                    (1 << 21)
  51 #define MPMU_AWUCRM_TRACKBALL                   (1 << 20)
  52 #define MPMU_AWUCRM_NEWROTARY                   (1 << 19)
  53 #define MPMU_AWUCRM_RTC_ALARM                   (1 << 17)
  54 #define MPMU_AWUCRM_AP2_TIMER_3                 (1 << 13)
  55 #define MPMU_AWUCRM_AP2_TIMER_2                 (1 << 12)
  56 #define MPMU_AWUCRM_AP2_TIMER_1                 (1 << 11)
  57 #define MPMU_AWUCRM_AP1_TIMER_3                 (1 << 10)
  58 #define MPMU_AWUCRM_AP1_TIMER_2                 (1 << 9)
  59 #define MPMU_AWUCRM_AP1_TIMER_1                 (1 << 8)
  60 #define MPMU_AWUCRM_WAKEUP(x)                   (1 << ((x) & 0x7))
  61
  62 enum {
  63         POWER_MODE_ACTIVE = 0,
  64         POWER_MODE_CORE_INTIDLE,
  65         POWER_MODE_CORE_EXTIDLE,
  66         POWER_MODE_APPS_IDLE,
  67         POWER_MODE_APPS_SLEEP,
  68         POWER_MODE_SYS_SLEEP,
  69         POWER_MODE_HIBERNATE,
  70         POWER_MODE_UDR,
  71 };
  72
  73 extern int pxa910_set_wake(struct irq_data *data, unsigned int on);
  74
  75 #endif