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Linux 5.6.13
[linux/fpc-iii.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
blobb7c51ea8c9a65a9aee5df87406cb8c9837935c28
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Hardware modules present on the OMAP44xx chips
4 *
5 * Copyright (C) 2009-2012 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
7 *
8 * Paul Walmsley
9 * Benoit Cousson
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 * Note that this file is currently not in sync with autogeneration scripts.
17 * The above note to be removed, once it is synced up.
18 */
19
20 #include <linux/io.h>
21
22 #include "omap_hwmod.h"
23 #include "omap_hwmod_common_data.h"
24 #include "cm1_44xx.h"
25 #include "cm2_44xx.h"
26 #include "prm44xx.h"
27 #include "prm-regbits-44xx.h"
28
29 /* Base offset for all OMAP4 interrupts external to MPUSS */
30 #define OMAP44XX_IRQ_GIC_START 32
31
32 /*
33 * IP blocks
34 */
35
36 /*
37 * 'dmm' class
38 * instance(s): dmm
39 */
40 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
41 .name = "dmm",
42 };
43
44 /* dmm */
45 static struct omap_hwmod omap44xx_dmm_hwmod = {
46 .name = "dmm",
47 .class = &omap44xx_dmm_hwmod_class,
48 .clkdm_name = "l3_emif_clkdm",
49 .prcm = {
50 .omap4 = {
51 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
52 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
53 },
54 },
55 };
56
57 /*
58 * 'l3' class
59 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
60 */
61 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
62 .name = "l3",
63 };
64
65 /* l3_instr */
66 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
67 .name = "l3_instr",
68 .class = &omap44xx_l3_hwmod_class,
69 .clkdm_name = "l3_instr_clkdm",
70 .prcm = {
71 .omap4 = {
72 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
73 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
74 .modulemode = MODULEMODE_HWCTRL,
75 },
76 },
77 };
78
79 /* l3_main_1 */
80 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
81 .name = "l3_main_1",
82 .class = &omap44xx_l3_hwmod_class,
83 .clkdm_name = "l3_1_clkdm",
84 .prcm = {
85 .omap4 = {
86 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
87 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
88 },
89 },
90 };
91
92 /* l3_main_2 */
93 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
94 .name = "l3_main_2",
95 .class = &omap44xx_l3_hwmod_class,
96 .clkdm_name = "l3_2_clkdm",
97 .prcm = {
98 .omap4 = {
99 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
100 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
101 },
102 },
103 };
104
105 /* l3_main_3 */
106 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
107 .name = "l3_main_3",
108 .class = &omap44xx_l3_hwmod_class,
109 .clkdm_name = "l3_instr_clkdm",
110 .prcm = {
111 .omap4 = {
112 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
113 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
114 .modulemode = MODULEMODE_HWCTRL,
115 },
116 },
117 };
118
119 /*
120 * 'l4' class
121 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
122 */
123 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
124 .name = "l4",
125 };
126
127 /* l4_abe */
128 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
129 .name = "l4_abe",
130 .class = &omap44xx_l4_hwmod_class,
131 .clkdm_name = "abe_clkdm",
132 .prcm = {
133 .omap4 = {
134 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
135 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
136 .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
137 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
138 },
139 },
140 };
141
142 /* l4_cfg */
143 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
144 .name = "l4_cfg",
145 .class = &omap44xx_l4_hwmod_class,
146 .clkdm_name = "l4_cfg_clkdm",
147 .prcm = {
148 .omap4 = {
149 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
150 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
151 },
152 },
153 };
154
155 /* l4_per */
156 static struct omap_hwmod omap44xx_l4_per_hwmod = {
157 .name = "l4_per",
158 .class = &omap44xx_l4_hwmod_class,
159 .clkdm_name = "l4_per_clkdm",
160 .prcm = {
161 .omap4 = {
162 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
163 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
164 },
165 },
166 };
167
168 /* l4_wkup */
169 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
170 .name = "l4_wkup",
171 .class = &omap44xx_l4_hwmod_class,
172 .clkdm_name = "l4_wkup_clkdm",
173 .prcm = {
174 .omap4 = {
175 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
176 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
177 },
178 },
179 };
180
181 /*
182 * 'mpu_bus' class
183 * instance(s): mpu_private
184 */
185 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
186 .name = "mpu_bus",
187 };
188
189 /* mpu_private */
190 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
191 .name = "mpu_private",
192 .class = &omap44xx_mpu_bus_hwmod_class,
193 .clkdm_name = "mpuss_clkdm",
194 .prcm = {
195 .omap4 = {
196 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
197 },
198 },
199 };
200
201 /*
202 * 'ocp_wp_noc' class
203 * instance(s): ocp_wp_noc
204 */
205 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
206 .name = "ocp_wp_noc",
207 };
208
209 /* ocp_wp_noc */
210 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
211 .name = "ocp_wp_noc",
212 .class = &omap44xx_ocp_wp_noc_hwmod_class,
213 .clkdm_name = "l3_instr_clkdm",
214 .prcm = {
215 .omap4 = {
216 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
217 .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
218 .modulemode = MODULEMODE_HWCTRL,
219 },
220 },
221 };
222
223 /*
224 * Modules omap_hwmod structures
225 *
226 * The following IPs are excluded for the moment because:
227 * - They do not need an explicit SW control using omap_hwmod API.
228 * - They still need to be validated with the driver
229 * properly adapted to omap_hwmod / omap_device
230 *
231 * usim
232 */
233
234 /*
235 * 'counter' class
236 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
237 */
238
239 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
240 .rev_offs = 0x0000,
241 .sysc_offs = 0x0004,
242 .sysc_flags = SYSC_HAS_SIDLEMODE,
243 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
244 .sysc_fields = &omap_hwmod_sysc_type1,
245 };
246
247 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
248 .name = "counter",
249 .sysc = &omap44xx_counter_sysc,
250 };
251
252 /* counter_32k */
253 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
254 .name = "counter_32k",
255 .class = &omap44xx_counter_hwmod_class,
256 .clkdm_name = "l4_wkup_clkdm",
257 .flags = HWMOD_SWSUP_SIDLE,
258 .main_clk = "sys_32k_ck",
259 .prcm = {
260 .omap4 = {
261 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
262 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
263 },
264 },
265 };
266
267 /*
268 * 'ctrl_module' class
269 * attila core control module + core pad control module + wkup pad control
270 * module + attila wkup control module
271 */
272
273 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
274 .rev_offs = 0x0000,
275 .sysc_offs = 0x0010,
276 .sysc_flags = SYSC_HAS_SIDLEMODE,
277 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
278 SIDLE_SMART_WKUP),
279 .sysc_fields = &omap_hwmod_sysc_type2,
280 };
281
282 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
283 .name = "ctrl_module",
284 .sysc = &omap44xx_ctrl_module_sysc,
285 };
286
287 /* ctrl_module_core */
288 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
289 .name = "ctrl_module_core",
290 .class = &omap44xx_ctrl_module_hwmod_class,
291 .clkdm_name = "l4_cfg_clkdm",
292 .prcm = {
293 .omap4 = {
294 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
295 },
296 },
297 };
298
299 /* ctrl_module_pad_core */
300 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
301 .name = "ctrl_module_pad_core",
302 .class = &omap44xx_ctrl_module_hwmod_class,
303 .clkdm_name = "l4_cfg_clkdm",
304 .prcm = {
305 .omap4 = {
306 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
307 },
308 },
309 };
310
311 /* ctrl_module_wkup */
312 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
313 .name = "ctrl_module_wkup",
314 .class = &omap44xx_ctrl_module_hwmod_class,
315 .clkdm_name = "l4_wkup_clkdm",
316 .prcm = {
317 .omap4 = {
318 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
319 },
320 },
321 };
322
323 /* ctrl_module_pad_wkup */
324 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
325 .name = "ctrl_module_pad_wkup",
326 .class = &omap44xx_ctrl_module_hwmod_class,
327 .clkdm_name = "l4_wkup_clkdm",
328 .prcm = {
329 .omap4 = {
330 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
331 },
332 },
333 };
334
335 /*
336 * 'debugss' class
337 * debug and emulation sub system
338 */
339
340 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
341 .name = "debugss",
342 };
343
344 /* debugss */
345 static struct omap_hwmod omap44xx_debugss_hwmod = {
346 .name = "debugss",
347 .class = &omap44xx_debugss_hwmod_class,
348 .clkdm_name = "emu_sys_clkdm",
349 .main_clk = "trace_clk_div_ck",
350 .prcm = {
351 .omap4 = {
352 .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
353 .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
354 },
355 },
356 };
357
358 /*
359 * 'dsp' class
360 * dsp sub-system
361 */
362
363 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
364 .name = "dsp",
365 };
366
367 /* dsp */
368 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
369 { .name = "dsp", .rst_shift = 0 },
370 };
371
372 static struct omap_hwmod omap44xx_dsp_hwmod = {
373 .name = "dsp",
374 .class = &omap44xx_dsp_hwmod_class,
375 .clkdm_name = "tesla_clkdm",
376 .rst_lines = omap44xx_dsp_resets,
377 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
378 .main_clk = "dpll_iva_m4x2_ck",
379 .prcm = {
380 .omap4 = {
381 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
382 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
383 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
384 .modulemode = MODULEMODE_HWCTRL,
385 },
386 },
387 };
388
389 /*
390 * 'dss' class
391 * display sub-system
392 */
393
394 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
395 .rev_offs = 0x0000,
396 .syss_offs = 0x0014,
397 .sysc_flags = SYSS_HAS_RESET_STATUS,
398 };
399
400 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
401 .name = "dss",
402 .sysc = &omap44xx_dss_sysc,
403 .reset = omap_dss_reset,
404 };
405
406 /* dss */
407 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
408 { .role = "sys_clk", .clk = "dss_sys_clk" },
409 { .role = "tv_clk", .clk = "dss_tv_clk" },
410 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
411 };
412
413 static struct omap_hwmod omap44xx_dss_hwmod = {
414 .name = "dss_core",
415 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
416 .class = &omap44xx_dss_hwmod_class,
417 .clkdm_name = "l3_dss_clkdm",
418 .main_clk = "dss_dss_clk",
419 .prcm = {
420 .omap4 = {
421 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
422 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
423 .modulemode = MODULEMODE_SWCTRL,
424 },
425 },
426 .opt_clks = dss_opt_clks,
427 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
428 };
429
430 /*
431 * 'dispc' class
432 * display controller
433 */
434
435 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
436 .rev_offs = 0x0000,
437 .sysc_offs = 0x0010,
438 .syss_offs = 0x0014,
439 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
440 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
441 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
442 SYSS_HAS_RESET_STATUS),
443 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
444 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
445 .sysc_fields = &omap_hwmod_sysc_type1,
446 };
447
448 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
449 .name = "dispc",
450 .sysc = &omap44xx_dispc_sysc,
451 };
452
453 /* dss_dispc */
454 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
455 .manager_count = 3,
456 .has_framedonetv_irq = 1
457 };
458
459 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
460 .name = "dss_dispc",
461 .class = &omap44xx_dispc_hwmod_class,
462 .clkdm_name = "l3_dss_clkdm",
463 .main_clk = "dss_dss_clk",
464 .prcm = {
465 .omap4 = {
466 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
467 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
468 },
469 },
470 .dev_attr = &omap44xx_dss_dispc_dev_attr,
471 .parent_hwmod = &omap44xx_dss_hwmod,
472 };
473
474 /*
475 * 'dsi' class
476 * display serial interface controller
477 */
478
479 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
480 .rev_offs = 0x0000,
481 .sysc_offs = 0x0010,
482 .syss_offs = 0x0014,
483 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
484 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
485 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
486 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
487 .sysc_fields = &omap_hwmod_sysc_type1,
488 };
489
490 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
491 .name = "dsi",
492 .sysc = &omap44xx_dsi_sysc,
493 };
494
495 /* dss_dsi1 */
496 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
497 { .role = "sys_clk", .clk = "dss_sys_clk" },
498 };
499
500 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
501 .name = "dss_dsi1",
502 .class = &omap44xx_dsi_hwmod_class,
503 .clkdm_name = "l3_dss_clkdm",
504 .main_clk = "dss_dss_clk",
505 .prcm = {
506 .omap4 = {
507 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
508 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
509 },
510 },
511 .opt_clks = dss_dsi1_opt_clks,
512 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
513 .parent_hwmod = &omap44xx_dss_hwmod,
514 };
515
516 /* dss_dsi2 */
517 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
518 { .role = "sys_clk", .clk = "dss_sys_clk" },
519 };
520
521 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
522 .name = "dss_dsi2",
523 .class = &omap44xx_dsi_hwmod_class,
524 .clkdm_name = "l3_dss_clkdm",
525 .main_clk = "dss_dss_clk",
526 .prcm = {
527 .omap4 = {
528 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
529 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
530 },
531 },
532 .opt_clks = dss_dsi2_opt_clks,
533 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
534 .parent_hwmod = &omap44xx_dss_hwmod,
535 };
536
537 /*
538 * 'hdmi' class
539 * hdmi controller
540 */
541
542 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
543 .rev_offs = 0x0000,
544 .sysc_offs = 0x0010,
545 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
546 SYSC_HAS_SOFTRESET),
547 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
548 SIDLE_SMART_WKUP),
549 .sysc_fields = &omap_hwmod_sysc_type2,
550 };
551
552 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
553 .name = "hdmi",
554 .sysc = &omap44xx_hdmi_sysc,
555 };
556
557 /* dss_hdmi */
558 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
559 { .role = "sys_clk", .clk = "dss_sys_clk" },
560 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
561 };
562
563 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
564 .name = "dss_hdmi",
565 .class = &omap44xx_hdmi_hwmod_class,
566 .clkdm_name = "l3_dss_clkdm",
567 /*
568 * HDMI audio requires to use no-idle mode. Hence,
569 * set idle mode by software.
570 */
571 .flags = HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
572 .main_clk = "dss_48mhz_clk",
573 .prcm = {
574 .omap4 = {
575 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
576 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
577 },
578 },
579 .opt_clks = dss_hdmi_opt_clks,
580 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
581 .parent_hwmod = &omap44xx_dss_hwmod,
582 };
583
584 /*
585 * 'rfbi' class
586 * remote frame buffer interface
587 */
588
589 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
590 .rev_offs = 0x0000,
591 .sysc_offs = 0x0010,
592 .syss_offs = 0x0014,
593 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
594 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
595 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
596 .sysc_fields = &omap_hwmod_sysc_type1,
597 };
598
599 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
600 .name = "rfbi",
601 .sysc = &omap44xx_rfbi_sysc,
602 };
603
604 /* dss_rfbi */
605 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
606 { .role = "ick", .clk = "l3_div_ck" },
607 };
608
609 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
610 .name = "dss_rfbi",
611 .class = &omap44xx_rfbi_hwmod_class,
612 .clkdm_name = "l3_dss_clkdm",
613 .main_clk = "dss_dss_clk",
614 .prcm = {
615 .omap4 = {
616 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
617 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
618 },
619 },
620 .opt_clks = dss_rfbi_opt_clks,
621 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
622 .parent_hwmod = &omap44xx_dss_hwmod,
623 };
624
625 /*
626 * 'venc' class
627 * video encoder
628 */
629
630 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
631 .name = "venc",
632 };
633
634 /* dss_venc */
635 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
636 { .role = "tv_clk", .clk = "dss_tv_clk" },
637 };
638
639 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
640 .name = "dss_venc",
641 .class = &omap44xx_venc_hwmod_class,
642 .clkdm_name = "l3_dss_clkdm",
643 .main_clk = "dss_tv_clk",
644 .flags = HWMOD_OPT_CLKS_NEEDED,
645 .prcm = {
646 .omap4 = {
647 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
648 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
649 },
650 },
651 .parent_hwmod = &omap44xx_dss_hwmod,
652 .opt_clks = dss_venc_opt_clks,
653 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
654 };
655
656
657
658 /*
659 * 'emif' class
660 * external memory interface no1
661 */
662
663 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
664 .rev_offs = 0x0000,
665 };
666
667 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
668 .name = "emif",
669 .sysc = &omap44xx_emif_sysc,
670 };
671
672 /* emif1 */
673 static struct omap_hwmod omap44xx_emif1_hwmod = {
674 .name = "emif1",
675 .class = &omap44xx_emif_hwmod_class,
676 .clkdm_name = "l3_emif_clkdm",
677 .flags = HWMOD_INIT_NO_IDLE,
678 .main_clk = "ddrphy_ck",
679 .prcm = {
680 .omap4 = {
681 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
682 .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
683 .modulemode = MODULEMODE_HWCTRL,
684 },
685 },
686 };
687
688 /* emif2 */
689 static struct omap_hwmod omap44xx_emif2_hwmod = {
690 .name = "emif2",
691 .class = &omap44xx_emif_hwmod_class,
692 .clkdm_name = "l3_emif_clkdm",
693 .flags = HWMOD_INIT_NO_IDLE,
694 .main_clk = "ddrphy_ck",
695 .prcm = {
696 .omap4 = {
697 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
698 .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
699 .modulemode = MODULEMODE_HWCTRL,
700 },
701 },
702 };
703
704 /*
705 * 'gpmc' class
706 * general purpose memory controller
707 */
708
709 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
710 .rev_offs = 0x0000,
711 .sysc_offs = 0x0010,
712 .syss_offs = 0x0014,
713 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
714 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
715 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
716 .sysc_fields = &omap_hwmod_sysc_type1,
717 };
718
719 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
720 .name = "gpmc",
721 .sysc = &omap44xx_gpmc_sysc,
722 };
723
724 /* gpmc */
725 static struct omap_hwmod omap44xx_gpmc_hwmod = {
726 .name = "gpmc",
727 .class = &omap44xx_gpmc_hwmod_class,
728 .clkdm_name = "l3_2_clkdm",
729 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
730 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
731 .prcm = {
732 .omap4 = {
733 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
734 .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
735 .modulemode = MODULEMODE_HWCTRL,
736 },
737 },
738 };
739
740
741 /*
742 * 'ipu' class
743 * imaging processor unit
744 */
745
746 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
747 .name = "ipu",
748 };
749
750 /* ipu */
751 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
752 { .name = "cpu0", .rst_shift = 0 },
753 { .name = "cpu1", .rst_shift = 1 },
754 };
755
756 static struct omap_hwmod omap44xx_ipu_hwmod = {
757 .name = "ipu",
758 .class = &omap44xx_ipu_hwmod_class,
759 .clkdm_name = "ducati_clkdm",
760 .rst_lines = omap44xx_ipu_resets,
761 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
762 .main_clk = "ducati_clk_mux_ck",
763 .prcm = {
764 .omap4 = {
765 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
766 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
767 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
768 .modulemode = MODULEMODE_HWCTRL,
769 },
770 },
771 };
772
773 /*
774 * 'iss' class
775 * external images sensor pixel data processor
776 */
777
778 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
779 .rev_offs = 0x0000,
780 .sysc_offs = 0x0010,
781 /*
782 * ISS needs 100 OCP clk cycles delay after a softreset before
783 * accessing sysconfig again.
784 * The lowest frequency at the moment for L3 bus is 100 MHz, so
785 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
786 *
787 * TODO: Indicate errata when available.
788 */
789 .srst_udelay = 2,
790 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
791 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
792 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
793 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
794 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
795 .sysc_fields = &omap_hwmod_sysc_type2,
796 };
797
798 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
799 .name = "iss",
800 .sysc = &omap44xx_iss_sysc,
801 };
802
803 /* iss */
804 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
805 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
806 };
807
808 static struct omap_hwmod omap44xx_iss_hwmod = {
809 .name = "iss",
810 .class = &omap44xx_iss_hwmod_class,
811 .clkdm_name = "iss_clkdm",
812 .main_clk = "ducati_clk_mux_ck",
813 .prcm = {
814 .omap4 = {
815 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
816 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
817 .modulemode = MODULEMODE_SWCTRL,
818 },
819 },
820 .opt_clks = iss_opt_clks,
821 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
822 };
823
824 /*
825 * 'iva' class
826 * multi-standard video encoder/decoder hardware accelerator
827 */
828
829 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
830 .name = "iva",
831 };
832
833 /* iva */
834 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
835 { .name = "seq0", .rst_shift = 0 },
836 { .name = "seq1", .rst_shift = 1 },
837 { .name = "logic", .rst_shift = 2 },
838 };
839
840 static struct omap_hwmod omap44xx_iva_hwmod = {
841 .name = "iva",
842 .class = &omap44xx_iva_hwmod_class,
843 .clkdm_name = "ivahd_clkdm",
844 .rst_lines = omap44xx_iva_resets,
845 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
846 .main_clk = "dpll_iva_m5x2_ck",
847 .prcm = {
848 .omap4 = {
849 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
850 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
851 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
852 .modulemode = MODULEMODE_HWCTRL,
853 },
854 },
855 };
856
857 /*
858 * 'mpu' class
859 * mpu sub-system
860 */
861
862 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
863 .name = "mpu",
864 };
865
866 /* mpu */
867 static struct omap_hwmod omap44xx_mpu_hwmod = {
868 .name = "mpu",
869 .class = &omap44xx_mpu_hwmod_class,
870 .clkdm_name = "mpuss_clkdm",
871 .flags = HWMOD_INIT_NO_IDLE,
872 .main_clk = "dpll_mpu_m2_ck",
873 .prcm = {
874 .omap4 = {
875 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
876 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
877 },
878 },
879 };
880
881 /*
882 * 'ocmc_ram' class
883 * top-level core on-chip ram
884 */
885
886 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
887 .name = "ocmc_ram",
888 };
889
890 /* ocmc_ram */
891 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
892 .name = "ocmc_ram",
893 .class = &omap44xx_ocmc_ram_hwmod_class,
894 .clkdm_name = "l3_2_clkdm",
895 .prcm = {
896 .omap4 = {
897 .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
898 .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
899 },
900 },
901 };
902
903
904 /*
905 * 'prcm' class
906 * power and reset manager (part of the prcm infrastructure) + clock manager 2
907 * + clock manager 1 (in always on power domain) + local prm in mpu
908 */
909
910 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
911 .name = "prcm",
912 };
913
914 /* prcm_mpu */
915 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
916 .name = "prcm_mpu",
917 .class = &omap44xx_prcm_hwmod_class,
918 .clkdm_name = "l4_wkup_clkdm",
919 .flags = HWMOD_NO_IDLEST,
920 .prcm = {
921 .omap4 = {
922 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
923 },
924 },
925 };
926
927 /* cm_core_aon */
928 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
929 .name = "cm_core_aon",
930 .class = &omap44xx_prcm_hwmod_class,
931 .flags = HWMOD_NO_IDLEST,
932 .prcm = {
933 .omap4 = {
934 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
935 },
936 },
937 };
938
939 /* cm_core */
940 static struct omap_hwmod omap44xx_cm_core_hwmod = {
941 .name = "cm_core",
942 .class = &omap44xx_prcm_hwmod_class,
943 .flags = HWMOD_NO_IDLEST,
944 .prcm = {
945 .omap4 = {
946 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
947 },
948 },
949 };
950
951 /* prm */
952 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
953 { .name = "rst_global_warm_sw", .rst_shift = 0 },
954 { .name = "rst_global_cold_sw", .rst_shift = 1 },
955 };
956
957 static struct omap_hwmod omap44xx_prm_hwmod = {
958 .name = "prm",
959 .class = &omap44xx_prcm_hwmod_class,
960 .rst_lines = omap44xx_prm_resets,
961 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
962 };
963
964 /*
965 * 'scrm' class
966 * system clock and reset manager
967 */
968
969 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
970 .name = "scrm",
971 };
972
973 /* scrm */
974 static struct omap_hwmod omap44xx_scrm_hwmod = {
975 .name = "scrm",
976 .class = &omap44xx_scrm_hwmod_class,
977 .clkdm_name = "l4_wkup_clkdm",
978 .prcm = {
979 .omap4 = {
980 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
981 },
982 },
983 };
984
985 /*
986 * 'sl2if' class
987 * shared level 2 memory interface
988 */
989
990 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
991 .name = "sl2if",
992 };
993
994 /* sl2if */
995 static struct omap_hwmod omap44xx_sl2if_hwmod = {
996 .name = "sl2if",
997 .class = &omap44xx_sl2if_hwmod_class,
998 .clkdm_name = "ivahd_clkdm",
999 .prcm = {
1000 .omap4 = {
1001 .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
1002 .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
1003 .modulemode = MODULEMODE_HWCTRL,
1004 },
1005 },
1006 };
1007
1008 /*
1009 * 'timer' class
1010 * general purpose timer module with accurate 1ms tick
1011 * This class contains several variants: ['timer_1ms', 'timer']
1012 */
1013
1014 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
1015 .rev_offs = 0x0000,
1016 .sysc_offs = 0x0010,
1017 .syss_offs = 0x0014,
1018 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1019 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1020 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1021 SYSS_HAS_RESET_STATUS),
1022 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1023 .sysc_fields = &omap_hwmod_sysc_type1,
1024 };
1025
1026 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
1027 .name = "timer",
1028 .sysc = &omap44xx_timer_1ms_sysc,
1029 };
1030
1031 /* timer1 */
1032 static struct omap_hwmod omap44xx_timer1_hwmod = {
1033 .name = "timer1",
1034 .class = &omap44xx_timer_1ms_hwmod_class,
1035 .clkdm_name = "l4_wkup_clkdm",
1036 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1037 .main_clk = "dmt1_clk_mux",
1038 .prcm = {
1039 .omap4 = {
1040 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1041 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
1042 .modulemode = MODULEMODE_SWCTRL,
1043 },
1044 },
1045 };
1046
1047 /*
1048 * 'usb_host_fs' class
1049 * full-speed usb host controller
1050 */
1051
1052 /* The IP is not compliant to type1 / type2 scheme */
1053 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
1054 .rev_offs = 0x0000,
1055 .sysc_offs = 0x0210,
1056 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1057 SYSC_HAS_SOFTRESET),
1058 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1059 SIDLE_SMART_WKUP),
1060 .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
1061 };
1062
1063 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
1064 .name = "usb_host_fs",
1065 .sysc = &omap44xx_usb_host_fs_sysc,
1066 };
1067
1068 /* usb_host_fs */
1069 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
1070 .name = "usb_host_fs",
1071 .class = &omap44xx_usb_host_fs_hwmod_class,
1072 .clkdm_name = "l3_init_clkdm",
1073 .main_clk = "usb_host_fs_fck",
1074 .prcm = {
1075 .omap4 = {
1076 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
1077 .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
1078 .modulemode = MODULEMODE_SWCTRL,
1079 },
1080 },
1081 };
1082
1083 /*
1084 * 'usb_host_hs' class
1085 * high-speed multi-port usb host controller
1086 */
1087
1088 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
1089 .rev_offs = 0x0000,
1090 .sysc_offs = 0x0010,
1091 .syss_offs = 0x0014,
1092 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1093 SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
1094 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1095 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1096 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1097 .sysc_fields = &omap_hwmod_sysc_type2,
1098 };
1099
1100 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
1101 .name = "usb_host_hs",
1102 .sysc = &omap44xx_usb_host_hs_sysc,
1103 };
1104
1105 /* usb_host_hs */
1106 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
1107 .name = "usb_host_hs",
1108 .class = &omap44xx_usb_host_hs_hwmod_class,
1109 .clkdm_name = "l3_init_clkdm",
1110 .main_clk = "usb_host_hs_fck",
1111 .prcm = {
1112 .omap4 = {
1113 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
1114 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
1115 .modulemode = MODULEMODE_SWCTRL,
1116 },
1117 },
1118
1119 /*
1120 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1121 * id: i660
1122 *
1123 * Description:
1124 * In the following configuration :
1125 * - USBHOST module is set to smart-idle mode
1126 * - PRCM asserts idle_req to the USBHOST module ( This typically
1127 * happens when the system is going to a low power mode : all ports
1128 * have been suspended, the master part of the USBHOST module has
1129 * entered the standby state, and SW has cut the functional clocks)
1130 * - an USBHOST interrupt occurs before the module is able to answer
1131 * idle_ack, typically a remote wakeup IRQ.
1132 * Then the USB HOST module will enter a deadlock situation where it
1133 * is no more accessible nor functional.
1134 *
1135 * Workaround:
1136 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1137 */
1138
1139 /*
1140 * Errata: USB host EHCI may stall when entering smart-standby mode
1141 * Id: i571
1142 *
1143 * Description:
1144 * When the USBHOST module is set to smart-standby mode, and when it is
1145 * ready to enter the standby state (i.e. all ports are suspended and
1146 * all attached devices are in suspend mode), then it can wrongly assert
1147 * the Mstandby signal too early while there are still some residual OCP
1148 * transactions ongoing. If this condition occurs, the internal state
1149 * machine may go to an undefined state and the USB link may be stuck
1150 * upon the next resume.
1151 *
1152 * Workaround:
1153 * Don't use smart standby; use only force standby,
1154 * hence HWMOD_SWSUP_MSTANDBY
1155 */
1156
1157 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1158 };
1159
1160 /*
1161 * 'usb_tll_hs' class
1162 * usb_tll_hs module is the adapter on the usb_host_hs ports
1163 */
1164
1165 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
1166 .rev_offs = 0x0000,
1167 .sysc_offs = 0x0010,
1168 .syss_offs = 0x0014,
1169 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1170 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1171 SYSC_HAS_AUTOIDLE),
1172 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1173 .sysc_fields = &omap_hwmod_sysc_type1,
1174 };
1175
1176 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
1177 .name = "usb_tll_hs",
1178 .sysc = &omap44xx_usb_tll_hs_sysc,
1179 };
1180
1181 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
1182 .name = "usb_tll_hs",
1183 .class = &omap44xx_usb_tll_hs_hwmod_class,
1184 .clkdm_name = "l3_init_clkdm",
1185 .main_clk = "usb_tll_hs_ick",
1186 .prcm = {
1187 .omap4 = {
1188 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
1189 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
1190 .modulemode = MODULEMODE_HWCTRL,
1191 },
1192 },
1193 };
1194
1195 /*
1196 * interfaces
1197 */
1198
1199 /* l3_main_1 -> dmm */
1200 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
1201 .master = &omap44xx_l3_main_1_hwmod,
1202 .slave = &omap44xx_dmm_hwmod,
1203 .clk = "l3_div_ck",
1204 .user = OCP_USER_SDMA,
1205 };
1206
1207 /* mpu -> dmm */
1208 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
1209 .master = &omap44xx_mpu_hwmod,
1210 .slave = &omap44xx_dmm_hwmod,
1211 .clk = "l3_div_ck",
1212 .user = OCP_USER_MPU,
1213 };
1214
1215 /* iva -> l3_instr */
1216 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
1217 .master = &omap44xx_iva_hwmod,
1218 .slave = &omap44xx_l3_instr_hwmod,
1219 .clk = "l3_div_ck",
1220 .user = OCP_USER_MPU | OCP_USER_SDMA,
1221 };
1222
1223 /* l3_main_3 -> l3_instr */
1224 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
1225 .master = &omap44xx_l3_main_3_hwmod,
1226 .slave = &omap44xx_l3_instr_hwmod,
1227 .clk = "l3_div_ck",
1228 .user = OCP_USER_MPU | OCP_USER_SDMA,
1229 };
1230
1231 /* ocp_wp_noc -> l3_instr */
1232 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
1233 .master = &omap44xx_ocp_wp_noc_hwmod,
1234 .slave = &omap44xx_l3_instr_hwmod,
1235 .clk = "l3_div_ck",
1236 .user = OCP_USER_MPU | OCP_USER_SDMA,
1237 };
1238
1239 /* dsp -> l3_main_1 */
1240 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
1241 .master = &omap44xx_dsp_hwmod,
1242 .slave = &omap44xx_l3_main_1_hwmod,
1243 .clk = "l3_div_ck",
1244 .user = OCP_USER_MPU | OCP_USER_SDMA,
1245 };
1246
1247 /* dss -> l3_main_1 */
1248 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
1249 .master = &omap44xx_dss_hwmod,
1250 .slave = &omap44xx_l3_main_1_hwmod,
1251 .clk = "l3_div_ck",
1252 .user = OCP_USER_MPU | OCP_USER_SDMA,
1253 };
1254
1255 /* l3_main_2 -> l3_main_1 */
1256 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
1257 .master = &omap44xx_l3_main_2_hwmod,
1258 .slave = &omap44xx_l3_main_1_hwmod,
1259 .clk = "l3_div_ck",
1260 .user = OCP_USER_MPU | OCP_USER_SDMA,
1261 };
1262
1263 /* l4_cfg -> l3_main_1 */
1264 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
1265 .master = &omap44xx_l4_cfg_hwmod,
1266 .slave = &omap44xx_l3_main_1_hwmod,
1267 .clk = "l4_div_ck",
1268 .user = OCP_USER_MPU | OCP_USER_SDMA,
1269 };
1270
1271 /* mpu -> l3_main_1 */
1272 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
1273 .master = &omap44xx_mpu_hwmod,
1274 .slave = &omap44xx_l3_main_1_hwmod,
1275 .clk = "l3_div_ck",
1276 .user = OCP_USER_MPU,
1277 };
1278
1279 /* debugss -> l3_main_2 */
1280 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
1281 .master = &omap44xx_debugss_hwmod,
1282 .slave = &omap44xx_l3_main_2_hwmod,
1283 .clk = "dbgclk_mux_ck",
1284 .user = OCP_USER_MPU | OCP_USER_SDMA,
1285 };
1286
1287 /* ipu -> l3_main_2 */
1288 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
1289 .master = &omap44xx_ipu_hwmod,
1290 .slave = &omap44xx_l3_main_2_hwmod,
1291 .clk = "l3_div_ck",
1292 .user = OCP_USER_MPU | OCP_USER_SDMA,
1293 };
1294
1295 /* iss -> l3_main_2 */
1296 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
1297 .master = &omap44xx_iss_hwmod,
1298 .slave = &omap44xx_l3_main_2_hwmod,
1299 .clk = "l3_div_ck",
1300 .user = OCP_USER_MPU | OCP_USER_SDMA,
1301 };
1302
1303 /* iva -> l3_main_2 */
1304 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
1305 .master = &omap44xx_iva_hwmod,
1306 .slave = &omap44xx_l3_main_2_hwmod,
1307 .clk = "l3_div_ck",
1308 .user = OCP_USER_MPU | OCP_USER_SDMA,
1309 };
1310
1311 /* l3_main_1 -> l3_main_2 */
1312 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
1313 .master = &omap44xx_l3_main_1_hwmod,
1314 .slave = &omap44xx_l3_main_2_hwmod,
1315 .clk = "l3_div_ck",
1316 .user = OCP_USER_MPU,
1317 };
1318
1319 /* l4_cfg -> l3_main_2 */
1320 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
1321 .master = &omap44xx_l4_cfg_hwmod,
1322 .slave = &omap44xx_l3_main_2_hwmod,
1323 .clk = "l4_div_ck",
1324 .user = OCP_USER_MPU | OCP_USER_SDMA,
1325 };
1326
1327 /* usb_host_fs -> l3_main_2 */
1328 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
1329 .master = &omap44xx_usb_host_fs_hwmod,
1330 .slave = &omap44xx_l3_main_2_hwmod,
1331 .clk = "l3_div_ck",
1332 .user = OCP_USER_MPU | OCP_USER_SDMA,
1333 };
1334
1335 /* usb_host_hs -> l3_main_2 */
1336 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
1337 .master = &omap44xx_usb_host_hs_hwmod,
1338 .slave = &omap44xx_l3_main_2_hwmod,
1339 .clk = "l3_div_ck",
1340 .user = OCP_USER_MPU | OCP_USER_SDMA,
1341 };
1342
1343 /* l3_main_1 -> l3_main_3 */
1344 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
1345 .master = &omap44xx_l3_main_1_hwmod,
1346 .slave = &omap44xx_l3_main_3_hwmod,
1347 .clk = "l3_div_ck",
1348 .user = OCP_USER_MPU,
1349 };
1350
1351 /* l3_main_2 -> l3_main_3 */
1352 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
1353 .master = &omap44xx_l3_main_2_hwmod,
1354 .slave = &omap44xx_l3_main_3_hwmod,
1355 .clk = "l3_div_ck",
1356 .user = OCP_USER_MPU | OCP_USER_SDMA,
1357 };
1358
1359 /* l4_cfg -> l3_main_3 */
1360 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
1361 .master = &omap44xx_l4_cfg_hwmod,
1362 .slave = &omap44xx_l3_main_3_hwmod,
1363 .clk = "l4_div_ck",
1364 .user = OCP_USER_MPU | OCP_USER_SDMA,
1365 };
1366
1367 /* dsp -> l4_abe */
1368 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
1369 .master = &omap44xx_dsp_hwmod,
1370 .slave = &omap44xx_l4_abe_hwmod,
1371 .clk = "ocp_abe_iclk",
1372 .user = OCP_USER_MPU | OCP_USER_SDMA,
1373 };
1374
1375 /* l3_main_1 -> l4_abe */
1376 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
1377 .master = &omap44xx_l3_main_1_hwmod,
1378 .slave = &omap44xx_l4_abe_hwmod,
1379 .clk = "l3_div_ck",
1380 .user = OCP_USER_MPU | OCP_USER_SDMA,
1381 };
1382
1383 /* mpu -> l4_abe */
1384 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
1385 .master = &omap44xx_mpu_hwmod,
1386 .slave = &omap44xx_l4_abe_hwmod,
1387 .clk = "ocp_abe_iclk",
1388 .user = OCP_USER_MPU | OCP_USER_SDMA,
1389 };
1390
1391 /* l3_main_1 -> l4_cfg */
1392 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
1393 .master = &omap44xx_l3_main_1_hwmod,
1394 .slave = &omap44xx_l4_cfg_hwmod,
1395 .clk = "l3_div_ck",
1396 .user = OCP_USER_MPU | OCP_USER_SDMA,
1397 };
1398
1399 /* l3_main_2 -> l4_per */
1400 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
1401 .master = &omap44xx_l3_main_2_hwmod,
1402 .slave = &omap44xx_l4_per_hwmod,
1403 .clk = "l3_div_ck",
1404 .user = OCP_USER_MPU | OCP_USER_SDMA,
1405 };
1406
1407 /* l4_cfg -> l4_wkup */
1408 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
1409 .master = &omap44xx_l4_cfg_hwmod,
1410 .slave = &omap44xx_l4_wkup_hwmod,
1411 .clk = "l4_div_ck",
1412 .user = OCP_USER_MPU | OCP_USER_SDMA,
1413 };
1414
1415 /* mpu -> mpu_private */
1416 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
1417 .master = &omap44xx_mpu_hwmod,
1418 .slave = &omap44xx_mpu_private_hwmod,
1419 .clk = "l3_div_ck",
1420 .user = OCP_USER_MPU | OCP_USER_SDMA,
1421 };
1422
1423 /* l4_cfg -> ocp_wp_noc */
1424 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
1425 .master = &omap44xx_l4_cfg_hwmod,
1426 .slave = &omap44xx_ocp_wp_noc_hwmod,
1427 .clk = "l4_div_ck",
1428 .user = OCP_USER_MPU | OCP_USER_SDMA,
1429 };
1430
1431 /* l4_wkup -> counter_32k */
1432 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
1433 .master = &omap44xx_l4_wkup_hwmod,
1434 .slave = &omap44xx_counter_32k_hwmod,
1435 .clk = "l4_wkup_clk_mux_ck",
1436 .user = OCP_USER_MPU | OCP_USER_SDMA,
1437 };
1438
1439 /* l4_cfg -> ctrl_module_core */
1440 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
1441 .master = &omap44xx_l4_cfg_hwmod,
1442 .slave = &omap44xx_ctrl_module_core_hwmod,
1443 .clk = "l4_div_ck",
1444 .user = OCP_USER_MPU | OCP_USER_SDMA,
1445 };
1446
1447 /* l4_cfg -> ctrl_module_pad_core */
1448 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
1449 .master = &omap44xx_l4_cfg_hwmod,
1450 .slave = &omap44xx_ctrl_module_pad_core_hwmod,
1451 .clk = "l4_div_ck",
1452 .user = OCP_USER_MPU | OCP_USER_SDMA,
1453 };
1454
1455 /* l4_wkup -> ctrl_module_wkup */
1456 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
1457 .master = &omap44xx_l4_wkup_hwmod,
1458 .slave = &omap44xx_ctrl_module_wkup_hwmod,
1459 .clk = "l4_wkup_clk_mux_ck",
1460 .user = OCP_USER_MPU | OCP_USER_SDMA,
1461 };
1462
1463 /* l4_wkup -> ctrl_module_pad_wkup */
1464 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
1465 .master = &omap44xx_l4_wkup_hwmod,
1466 .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
1467 .clk = "l4_wkup_clk_mux_ck",
1468 .user = OCP_USER_MPU | OCP_USER_SDMA,
1469 };
1470
1471 /* l3_instr -> debugss */
1472 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
1473 .master = &omap44xx_l3_instr_hwmod,
1474 .slave = &omap44xx_debugss_hwmod,
1475 .clk = "l3_div_ck",
1476 .user = OCP_USER_MPU | OCP_USER_SDMA,
1477 };
1478
1479 /* dsp -> iva */
1480 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1481 .master = &omap44xx_dsp_hwmod,
1482 .slave = &omap44xx_iva_hwmod,
1483 .clk = "dpll_iva_m5x2_ck",
1484 .user = OCP_USER_DSP,
1485 };
1486
1487 /* dsp -> sl2if */
1488 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
1489 .master = &omap44xx_dsp_hwmod,
1490 .slave = &omap44xx_sl2if_hwmod,
1491 .clk = "dpll_iva_m5x2_ck",
1492 .user = OCP_USER_DSP,
1493 };
1494
1495 /* l4_cfg -> dsp */
1496 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1497 .master = &omap44xx_l4_cfg_hwmod,
1498 .slave = &omap44xx_dsp_hwmod,
1499 .clk = "l4_div_ck",
1500 .user = OCP_USER_MPU | OCP_USER_SDMA,
1501 };
1502
1503 /* l3_main_2 -> dss */
1504 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1505 .master = &omap44xx_l3_main_2_hwmod,
1506 .slave = &omap44xx_dss_hwmod,
1507 .clk = "l3_div_ck",
1508 .user = OCP_USER_SDMA,
1509 };
1510
1511 /* l4_per -> dss */
1512 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1513 .master = &omap44xx_l4_per_hwmod,
1514 .slave = &omap44xx_dss_hwmod,
1515 .clk = "l4_div_ck",
1516 .user = OCP_USER_MPU,
1517 };
1518
1519 /* l3_main_2 -> dss_dispc */
1520 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1521 .master = &omap44xx_l3_main_2_hwmod,
1522 .slave = &omap44xx_dss_dispc_hwmod,
1523 .clk = "l3_div_ck",
1524 .user = OCP_USER_SDMA,
1525 };
1526
1527 /* l4_per -> dss_dispc */
1528 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1529 .master = &omap44xx_l4_per_hwmod,
1530 .slave = &omap44xx_dss_dispc_hwmod,
1531 .clk = "l4_div_ck",
1532 .user = OCP_USER_MPU,
1533 };
1534
1535 /* l3_main_2 -> dss_dsi1 */
1536 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1537 .master = &omap44xx_l3_main_2_hwmod,
1538 .slave = &omap44xx_dss_dsi1_hwmod,
1539 .clk = "l3_div_ck",
1540 .user = OCP_USER_SDMA,
1541 };
1542
1543 /* l4_per -> dss_dsi1 */
1544 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1545 .master = &omap44xx_l4_per_hwmod,
1546 .slave = &omap44xx_dss_dsi1_hwmod,
1547 .clk = "l4_div_ck",
1548 .user = OCP_USER_MPU,
1549 };
1550
1551 /* l3_main_2 -> dss_dsi2 */
1552 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1553 .master = &omap44xx_l3_main_2_hwmod,
1554 .slave = &omap44xx_dss_dsi2_hwmod,
1555 .clk = "l3_div_ck",
1556 .user = OCP_USER_SDMA,
1557 };
1558
1559 /* l4_per -> dss_dsi2 */
1560 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1561 .master = &omap44xx_l4_per_hwmod,
1562 .slave = &omap44xx_dss_dsi2_hwmod,
1563 .clk = "l4_div_ck",
1564 .user = OCP_USER_MPU,
1565 };
1566
1567 /* l3_main_2 -> dss_hdmi */
1568 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1569 .master = &omap44xx_l3_main_2_hwmod,
1570 .slave = &omap44xx_dss_hdmi_hwmod,
1571 .clk = "l3_div_ck",
1572 .user = OCP_USER_SDMA,
1573 };
1574
1575 /* l4_per -> dss_hdmi */
1576 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1577 .master = &omap44xx_l4_per_hwmod,
1578 .slave = &omap44xx_dss_hdmi_hwmod,
1579 .clk = "l4_div_ck",
1580 .user = OCP_USER_MPU,
1581 };
1582
1583 /* l3_main_2 -> dss_rfbi */
1584 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1585 .master = &omap44xx_l3_main_2_hwmod,
1586 .slave = &omap44xx_dss_rfbi_hwmod,
1587 .clk = "l3_div_ck",
1588 .user = OCP_USER_SDMA,
1589 };
1590
1591 /* l4_per -> dss_rfbi */
1592 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1593 .master = &omap44xx_l4_per_hwmod,
1594 .slave = &omap44xx_dss_rfbi_hwmod,
1595 .clk = "l4_div_ck",
1596 .user = OCP_USER_MPU,
1597 };
1598
1599 /* l3_main_2 -> dss_venc */
1600 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1601 .master = &omap44xx_l3_main_2_hwmod,
1602 .slave = &omap44xx_dss_venc_hwmod,
1603 .clk = "l3_div_ck",
1604 .user = OCP_USER_SDMA,
1605 };
1606
1607 /* l4_per -> dss_venc */
1608 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1609 .master = &omap44xx_l4_per_hwmod,
1610 .slave = &omap44xx_dss_venc_hwmod,
1611 .clk = "l4_div_ck",
1612 .user = OCP_USER_MPU,
1613 };
1614
1615 /* l3_main_2 -> gpmc */
1616 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
1617 .master = &omap44xx_l3_main_2_hwmod,
1618 .slave = &omap44xx_gpmc_hwmod,
1619 .clk = "l3_div_ck",
1620 .user = OCP_USER_MPU | OCP_USER_SDMA,
1621 };
1622
1623 /* l3_main_2 -> ipu */
1624 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
1625 .master = &omap44xx_l3_main_2_hwmod,
1626 .slave = &omap44xx_ipu_hwmod,
1627 .clk = "l3_div_ck",
1628 .user = OCP_USER_MPU | OCP_USER_SDMA,
1629 };
1630
1631 /* l3_main_2 -> iss */
1632 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
1633 .master = &omap44xx_l3_main_2_hwmod,
1634 .slave = &omap44xx_iss_hwmod,
1635 .clk = "l3_div_ck",
1636 .user = OCP_USER_MPU | OCP_USER_SDMA,
1637 };
1638
1639 /* iva -> sl2if */
1640 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
1641 .master = &omap44xx_iva_hwmod,
1642 .slave = &omap44xx_sl2if_hwmod,
1643 .clk = "dpll_iva_m5x2_ck",
1644 .user = OCP_USER_IVA,
1645 };
1646
1647 /* l3_main_2 -> iva */
1648 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
1649 .master = &omap44xx_l3_main_2_hwmod,
1650 .slave = &omap44xx_iva_hwmod,
1651 .clk = "l3_div_ck",
1652 .user = OCP_USER_MPU,
1653 };
1654
1655 /* l3_main_2 -> ocmc_ram */
1656 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
1657 .master = &omap44xx_l3_main_2_hwmod,
1658 .slave = &omap44xx_ocmc_ram_hwmod,
1659 .clk = "l3_div_ck",
1660 .user = OCP_USER_MPU | OCP_USER_SDMA,
1661 };
1662
1663 /* mpu_private -> prcm_mpu */
1664 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
1665 .master = &omap44xx_mpu_private_hwmod,
1666 .slave = &omap44xx_prcm_mpu_hwmod,
1667 .clk = "l3_div_ck",
1668 .user = OCP_USER_MPU | OCP_USER_SDMA,
1669 };
1670
1671 /* l4_wkup -> cm_core_aon */
1672 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
1673 .master = &omap44xx_l4_wkup_hwmod,
1674 .slave = &omap44xx_cm_core_aon_hwmod,
1675 .clk = "l4_wkup_clk_mux_ck",
1676 .user = OCP_USER_MPU | OCP_USER_SDMA,
1677 };
1678
1679 /* l4_cfg -> cm_core */
1680 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
1681 .master = &omap44xx_l4_cfg_hwmod,
1682 .slave = &omap44xx_cm_core_hwmod,
1683 .clk = "l4_div_ck",
1684 .user = OCP_USER_MPU | OCP_USER_SDMA,
1685 };
1686
1687 /* l4_wkup -> prm */
1688 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
1689 .master = &omap44xx_l4_wkup_hwmod,
1690 .slave = &omap44xx_prm_hwmod,
1691 .clk = "l4_wkup_clk_mux_ck",
1692 .user = OCP_USER_MPU | OCP_USER_SDMA,
1693 };
1694
1695 /* l4_wkup -> scrm */
1696 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
1697 .master = &omap44xx_l4_wkup_hwmod,
1698 .slave = &omap44xx_scrm_hwmod,
1699 .clk = "l4_wkup_clk_mux_ck",
1700 .user = OCP_USER_MPU | OCP_USER_SDMA,
1701 };
1702
1703 /* l3_main_2 -> sl2if */
1704 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
1705 .master = &omap44xx_l3_main_2_hwmod,
1706 .slave = &omap44xx_sl2if_hwmod,
1707 .clk = "l3_div_ck",
1708 .user = OCP_USER_MPU | OCP_USER_SDMA,
1709 };
1710
1711 /* l4_wkup -> timer1 */
1712 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
1713 .master = &omap44xx_l4_wkup_hwmod,
1714 .slave = &omap44xx_timer1_hwmod,
1715 .clk = "l4_wkup_clk_mux_ck",
1716 .user = OCP_USER_MPU | OCP_USER_SDMA,
1717 };
1718
1719 /* l4_cfg -> usb_host_fs */
1720 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
1721 .master = &omap44xx_l4_cfg_hwmod,
1722 .slave = &omap44xx_usb_host_fs_hwmod,
1723 .clk = "l4_div_ck",
1724 .user = OCP_USER_MPU | OCP_USER_SDMA,
1725 };
1726
1727 /* l4_cfg -> usb_host_hs */
1728 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
1729 .master = &omap44xx_l4_cfg_hwmod,
1730 .slave = &omap44xx_usb_host_hs_hwmod,
1731 .clk = "l4_div_ck",
1732 .user = OCP_USER_MPU | OCP_USER_SDMA,
1733 };
1734
1735 /* l4_cfg -> usb_tll_hs */
1736 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
1737 .master = &omap44xx_l4_cfg_hwmod,
1738 .slave = &omap44xx_usb_tll_hs_hwmod,
1739 .clk = "l4_div_ck",
1740 .user = OCP_USER_MPU | OCP_USER_SDMA,
1741 };
1742
1743 /* mpu -> emif1 */
1744 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
1745 .master = &omap44xx_mpu_hwmod,
1746 .slave = &omap44xx_emif1_hwmod,
1747 .clk = "l3_div_ck",
1748 .user = OCP_USER_MPU | OCP_USER_SDMA,
1749 };
1750
1751 /* mpu -> emif2 */
1752 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
1753 .master = &omap44xx_mpu_hwmod,
1754 .slave = &omap44xx_emif2_hwmod,
1755 .clk = "l3_div_ck",
1756 .user = OCP_USER_MPU | OCP_USER_SDMA,
1757 };
1758
1759 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
1760 &omap44xx_l3_main_1__dmm,
1761 &omap44xx_mpu__dmm,
1762 &omap44xx_iva__l3_instr,
1763 &omap44xx_l3_main_3__l3_instr,
1764 &omap44xx_ocp_wp_noc__l3_instr,
1765 &omap44xx_dsp__l3_main_1,
1766 &omap44xx_dss__l3_main_1,
1767 &omap44xx_l3_main_2__l3_main_1,
1768 &omap44xx_l4_cfg__l3_main_1,
1769 &omap44xx_mpu__l3_main_1,
1770 &omap44xx_debugss__l3_main_2,
1771 &omap44xx_ipu__l3_main_2,
1772 &omap44xx_iss__l3_main_2,
1773 &omap44xx_iva__l3_main_2,
1774 &omap44xx_l3_main_1__l3_main_2,
1775 &omap44xx_l4_cfg__l3_main_2,
1776 /* &omap44xx_usb_host_fs__l3_main_2, */
1777 &omap44xx_usb_host_hs__l3_main_2,
1778 &omap44xx_l3_main_1__l3_main_3,
1779 &omap44xx_l3_main_2__l3_main_3,
1780 &omap44xx_l4_cfg__l3_main_3,
1781 &omap44xx_dsp__l4_abe,
1782 &omap44xx_l3_main_1__l4_abe,
1783 &omap44xx_mpu__l4_abe,
1784 &omap44xx_l3_main_1__l4_cfg,
1785 &omap44xx_l3_main_2__l4_per,
1786 &omap44xx_l4_cfg__l4_wkup,
1787 &omap44xx_mpu__mpu_private,
1788 &omap44xx_l4_cfg__ocp_wp_noc,
1789 &omap44xx_l4_wkup__counter_32k,
1790 &omap44xx_l4_cfg__ctrl_module_core,
1791 &omap44xx_l4_cfg__ctrl_module_pad_core,
1792 &omap44xx_l4_wkup__ctrl_module_wkup,
1793 &omap44xx_l4_wkup__ctrl_module_pad_wkup,
1794 &omap44xx_l3_instr__debugss,
1795 &omap44xx_dsp__iva,
1796 /* &omap44xx_dsp__sl2if, */
1797 &omap44xx_l4_cfg__dsp,
1798 &omap44xx_l3_main_2__dss,
1799 &omap44xx_l4_per__dss,
1800 &omap44xx_l3_main_2__dss_dispc,
1801 &omap44xx_l4_per__dss_dispc,
1802 &omap44xx_l3_main_2__dss_dsi1,
1803 &omap44xx_l4_per__dss_dsi1,
1804 &omap44xx_l3_main_2__dss_dsi2,
1805 &omap44xx_l4_per__dss_dsi2,
1806 &omap44xx_l3_main_2__dss_hdmi,
1807 &omap44xx_l4_per__dss_hdmi,
1808 &omap44xx_l3_main_2__dss_rfbi,
1809 &omap44xx_l4_per__dss_rfbi,
1810 &omap44xx_l3_main_2__dss_venc,
1811 &omap44xx_l4_per__dss_venc,
1812 &omap44xx_l3_main_2__gpmc,
1813 &omap44xx_l3_main_2__ipu,
1814 &omap44xx_l3_main_2__iss,
1815 /* &omap44xx_iva__sl2if, */
1816 &omap44xx_l3_main_2__iva,
1817 &omap44xx_l3_main_2__ocmc_ram,
1818 &omap44xx_mpu_private__prcm_mpu,
1819 &omap44xx_l4_wkup__cm_core_aon,
1820 &omap44xx_l4_cfg__cm_core,
1821 &omap44xx_l4_wkup__prm,
1822 &omap44xx_l4_wkup__scrm,
1823 /* &omap44xx_l3_main_2__sl2if, */
1824 &omap44xx_l4_wkup__timer1,
1825 /* &omap44xx_l4_cfg__usb_host_fs, */
1826 &omap44xx_l4_cfg__usb_host_hs,
1827 &omap44xx_l4_cfg__usb_tll_hs,
1828 &omap44xx_mpu__emif1,
1829 &omap44xx_mpu__emif2,
1830 NULL,
1831 };
1832
1833 int __init omap44xx_hwmod_init(void)
1834 {
1835 omap_hwmod_init();
1836 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
1837 }
1838
Linux with added FPC-III support