| blob | ecbafdb930aa9489e55de0dfdc0829ade0273130 |
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4 */
6 #ifndef _DT_BINDINGS_CLK_MSM_MMCC_8998_H
7 #define _DT_BINDINGS_CLK_MSM_MMCC_8998_H
9 #define MMPLL0 0
10 #define MMPLL0_OUT_EVEN 1
11 #define MMPLL1 2
12 #define MMPLL1_OUT_EVEN 3
13 #define MMPLL3 4
14 #define MMPLL3_OUT_EVEN 5
15 #define MMPLL4 6
16 #define MMPLL4_OUT_EVEN 7
17 #define MMPLL5 8
18 #define MMPLL5_OUT_EVEN 9
19 #define MMPLL6 10
20 #define MMPLL6_OUT_EVEN 11
21 #define MMPLL7 12
22 #define MMPLL7_OUT_EVEN 13
23 #define MMPLL10 14
24 #define MMPLL10_OUT_EVEN 15
25 #define BYTE0_CLK_SRC 16
26 #define BYTE1_CLK_SRC 17
27 #define CCI_CLK_SRC 18
28 #define CPP_CLK_SRC 19
29 #define CSI0_CLK_SRC 20
30 #define CSI1_CLK_SRC 21
31 #define CSI2_CLK_SRC 22
32 #define CSI3_CLK_SRC 23
33 #define CSIPHY_CLK_SRC 24
34 #define CSI0PHYTIMER_CLK_SRC 25
35 #define CSI1PHYTIMER_CLK_SRC 26
36 #define CSI2PHYTIMER_CLK_SRC 27
37 #define DP_AUX_CLK_SRC 28
38 #define DP_CRYPTO_CLK_SRC 29
39 #define DP_LINK_CLK_SRC 30
40 #define DP_PIXEL_CLK_SRC 31
41 #define ESC0_CLK_SRC 32
42 #define ESC1_CLK_SRC 33
43 #define EXTPCLK_CLK_SRC 34
44 #define FD_CORE_CLK_SRC 35
45 #define HDMI_CLK_SRC 36
46 #define JPEG0_CLK_SRC 37
47 #define MAXI_CLK_SRC 38
48 #define MCLK0_CLK_SRC 39
49 #define MCLK1_CLK_SRC 40
50 #define MCLK2_CLK_SRC 41
51 #define MCLK3_CLK_SRC 42
52 #define MDP_CLK_SRC 43
53 #define VSYNC_CLK_SRC 44
54 #define AHB_CLK_SRC 45
55 #define AXI_CLK_SRC 46
56 #define PCLK0_CLK_SRC 47
57 #define PCLK1_CLK_SRC 48
58 #define ROT_CLK_SRC 49
59 #define VIDEO_CORE_CLK_SRC 50
60 #define VIDEO_SUBCORE0_CLK_SRC 51
61 #define VIDEO_SUBCORE1_CLK_SRC 52
62 #define VFE0_CLK_SRC 53
63 #define VFE1_CLK_SRC 54
64 #define MISC_AHB_CLK 55
65 #define VIDEO_CORE_CLK 56
66 #define VIDEO_AHB_CLK 57
67 #define VIDEO_AXI_CLK 58
68 #define VIDEO_MAXI_CLK 59
69 #define VIDEO_SUBCORE0_CLK 60
70 #define VIDEO_SUBCORE1_CLK 61
71 #define MDSS_AHB_CLK 62
72 #define MDSS_HDMI_DP_AHB_CLK 63
73 #define MDSS_AXI_CLK 64
74 #define MDSS_PCLK0_CLK 65
75 #define MDSS_PCLK1_CLK 66
76 #define MDSS_MDP_CLK 67
77 #define MDSS_MDP_LUT_CLK 68
78 #define MDSS_EXTPCLK_CLK 69
79 #define MDSS_VSYNC_CLK 70
80 #define MDSS_HDMI_CLK 71
81 #define MDSS_BYTE0_CLK 72
82 #define MDSS_BYTE1_CLK 73
83 #define MDSS_ESC0_CLK 74
84 #define MDSS_ESC1_CLK 75
85 #define MDSS_ROT_CLK 76
86 #define MDSS_DP_LINK_CLK 77
87 #define MDSS_DP_LINK_INTF_CLK 78
88 #define MDSS_DP_CRYPTO_CLK 79
89 #define MDSS_DP_PIXEL_CLK 80
90 #define MDSS_DP_AUX_CLK 81
91 #define MDSS_BYTE0_INTF_CLK 82
92 #define MDSS_BYTE1_INTF_CLK 83
93 #define CAMSS_CSI0PHYTIMER_CLK 84
94 #define CAMSS_CSI1PHYTIMER_CLK 85
95 #define CAMSS_CSI2PHYTIMER_CLK 86
96 #define CAMSS_CSI0_CLK 87
97 #define CAMSS_CSI0_AHB_CLK 88
98 #define CAMSS_CSI0RDI_CLK 89
99 #define CAMSS_CSI0PIX_CLK 90
100 #define CAMSS_CSI1_CLK 91
101 #define CAMSS_CSI1_AHB_CLK 92
102 #define CAMSS_CSI1RDI_CLK 93
103 #define CAMSS_CSI1PIX_CLK 94
104 #define CAMSS_CSI2_CLK 95
105 #define CAMSS_CSI2_AHB_CLK 96
106 #define CAMSS_CSI2RDI_CLK 97
107 #define CAMSS_CSI2PIX_CLK 98
108 #define CAMSS_CSI3_CLK 99
109 #define CAMSS_CSI3_AHB_CLK 100
110 #define CAMSS_CSI3RDI_CLK 101
111 #define CAMSS_CSI3PIX_CLK 102
112 #define CAMSS_ISPIF_AHB_CLK 103
113 #define CAMSS_CCI_CLK 104
114 #define CAMSS_CCI_AHB_CLK 105
115 #define CAMSS_MCLK0_CLK 106
116 #define CAMSS_MCLK1_CLK 107
117 #define CAMSS_MCLK2_CLK 108
118 #define CAMSS_MCLK3_CLK 109
119 #define CAMSS_TOP_AHB_CLK 110
120 #define CAMSS_AHB_CLK 111
121 #define CAMSS_MICRO_AHB_CLK 112
122 #define CAMSS_JPEG0_CLK 113
123 #define CAMSS_JPEG_AHB_CLK 114
124 #define CAMSS_JPEG_AXI_CLK 115
125 #define CAMSS_VFE0_AHB_CLK 116
126 #define CAMSS_VFE1_AHB_CLK 117
127 #define CAMSS_VFE0_CLK 118
128 #define CAMSS_VFE1_CLK 119
129 #define CAMSS_CPP_CLK 120
130 #define CAMSS_CPP_AHB_CLK 121
131 #define CAMSS_VFE_VBIF_AHB_CLK 122
132 #define CAMSS_VFE_VBIF_AXI_CLK 123
133 #define CAMSS_CPP_AXI_CLK 124
134 #define CAMSS_CPP_VBIF_AHB_CLK 125
135 #define CAMSS_CSI_VFE0_CLK 126
136 #define CAMSS_CSI_VFE1_CLK 127
137 #define CAMSS_VFE0_STREAM_CLK 128
138 #define CAMSS_VFE1_STREAM_CLK 129
139 #define CAMSS_CPHY_CSID0_CLK 130
140 #define CAMSS_CPHY_CSID1_CLK 131
141 #define CAMSS_CPHY_CSID2_CLK 132
142 #define CAMSS_CPHY_CSID3_CLK 133
143 #define CAMSS_CSIPHY0_CLK 134
144 #define CAMSS_CSIPHY1_CLK 135
145 #define CAMSS_CSIPHY2_CLK 136
146 #define FD_CORE_CLK 137
147 #define FD_CORE_UAR_CLK 138
148 #define FD_AHB_CLK 139
149 #define MNOC_AHB_CLK 140
150 #define BIMC_SMMU_AHB_CLK 141
151 #define BIMC_SMMU_AXI_CLK 142
152 #define MNOC_MAXI_CLK 143
153 #define VMEM_MAXI_CLK 144
154 #define VMEM_AHB_CLK 145
156 #define SPDM_BCR 0
157 #define SPDM_RM_BCR 1
158 #define MISC_BCR 2
159 #define VIDEO_TOP_BCR 3
160 #define THROTTLE_VIDEO_BCR 4
161 #define MDSS_BCR 5
162 #define THROTTLE_MDSS_BCR 6
163 #define CAMSS_PHY0_BCR 7
164 #define CAMSS_PHY1_BCR 8
165 #define CAMSS_PHY2_BCR 9
166 #define CAMSS_CSI0_BCR 10
167 #define CAMSS_CSI0RDI_BCR 11
168 #define CAMSS_CSI0PIX_BCR 12
169 #define CAMSS_CSI1_BCR 13
170 #define CAMSS_CSI1RDI_BCR 14
171 #define CAMSS_CSI1PIX_BCR 15
172 #define CAMSS_CSI2_BCR 16
173 #define CAMSS_CSI2RDI_BCR 17
174 #define CAMSS_CSI2PIX_BCR 18
175 #define CAMSS_CSI3_BCR 19
176 #define CAMSS_CSI3RDI_BCR 20
177 #define CAMSS_CSI3PIX_BCR 21
178 #define CAMSS_ISPIF_BCR 22
179 #define CAMSS_CCI_BCR 23
180 #define CAMSS_TOP_BCR 24
181 #define CAMSS_AHB_BCR 25
182 #define CAMSS_MICRO_BCR 26
183 #define CAMSS_JPEG_BCR 27
184 #define CAMSS_VFE0_BCR 28
185 #define CAMSS_VFE1_BCR 29
186 #define CAMSS_VFE_VBIF_BCR 30
187 #define CAMSS_CPP_TOP_BCR 31
188 #define CAMSS_CPP_BCR 32
189 #define CAMSS_CSI_VFE0_BCR 33
190 #define CAMSS_CSI_VFE1_BCR 34
191 #define CAMSS_FD_BCR 35
192 #define THROTTLE_CAMSS_BCR 36
193 #define MNOCAHB_BCR 37
194 #define MNOCAXI_BCR 38
195 #define BMIC_SMMU_BCR 39
196 #define MNOC_MAXI_BCR 40
197 #define VMEM_BCR 41
198 #define BTO_BCR 42
200 #define VIDEO_TOP_GDSC 1
201 #define VIDEO_SUBCORE0_GDSC 2
202 #define VIDEO_SUBCORE1_GDSC 3
203 #define MDSS_GDSC 4
204 #define CAMSS_TOP_GDSC 5
205 #define CAMSS_VFE0_GDSC 6
206 #define CAMSS_VFE1_GDSC 7
207 #define CAMSS_CPP_GDSC 8
208 #define BIMC_SMMU_GDSC 9
210 #endif