include/dt-bindings/reset/mt8135-resets.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: Flora Fu, MediaTek
   5  */
   6
   7 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135
   8 #define _DT_BINDINGS_RESET_CONTROLLER_MT8135
   9
  10 /* INFRACFG resets */
  11 #define MT8135_INFRA_EMI_REG_RST        0
  12 #define MT8135_INFRA_DRAMC0_A0_RST      1
  13 #define MT8135_INFRA_CCIF0_RST          2
  14 #define MT8135_INFRA_APCIRQ_EINT_RST    3
  15 #define MT8135_INFRA_APXGPT_RST         4
  16 #define MT8135_INFRA_SCPSYS_RST         5
  17 #define MT8135_INFRA_CCIF1_RST          6
  18 #define MT8135_INFRA_PMIC_WRAP_RST      7
  19 #define MT8135_INFRA_KP_RST             8
  20 #define MT8135_INFRA_EMI_RST            32
  21 #define MT8135_INFRA_DRAMC0_RST         34
  22 #define MT8135_INFRA_SMI_RST            35
  23 #define MT8135_INFRA_M4U_RST            36
  24
  25 /*  PERICFG resets */
  26 #define MT8135_PERI_UART0_SW_RST        0
  27 #define MT8135_PERI_UART1_SW_RST        1
  28 #define MT8135_PERI_UART2_SW_RST        2
  29 #define MT8135_PERI_UART3_SW_RST        3
  30 #define MT8135_PERI_IRDA_SW_RST         4
  31 #define MT8135_PERI_PTP_SW_RST          5
  32 #define MT8135_PERI_AP_HIF_SW_RST       6
  33 #define MT8135_PERI_GPCU_SW_RST         7
  34 #define MT8135_PERI_MD_HIF_SW_RST       8
  35 #define MT8135_PERI_NLI_SW_RST          9
  36 #define MT8135_PERI_AUXADC_SW_RST       10
  37 #define MT8135_PERI_DMA_SW_RST          11
  38 #define MT8135_PERI_NFI_SW_RST          14
  39 #define MT8135_PERI_PWM_SW_RST          15
  40 #define MT8135_PERI_THERM_SW_RST        16
  41 #define MT8135_PERI_MSDC0_SW_RST        17
  42 #define MT8135_PERI_MSDC1_SW_RST        18
  43 #define MT8135_PERI_MSDC2_SW_RST        19
  44 #define MT8135_PERI_MSDC3_SW_RST        20
  45 #define MT8135_PERI_I2C0_SW_RST         22
  46 #define MT8135_PERI_I2C1_SW_RST         23
  47 #define MT8135_PERI_I2C2_SW_RST         24
  48 #define MT8135_PERI_I2C3_SW_RST         25
  49 #define MT8135_PERI_I2C4_SW_RST         26
  50 #define MT8135_PERI_I2C5_SW_RST         27
  51 #define MT8135_PERI_I2C6_SW_RST         28
  52 #define MT8135_PERI_USB_SW_RST          29
  53 #define MT8135_PERI_SPI1_SW_RST         33
  54 #define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34
  55
  56 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */