| blob | 2c0cb6afe816e39d457e423c5d6307eb574de206 |
1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
2 /*
3 * Realtek RTD1295 reset controllers
4 *
5 * Copyright (c) 2017 Andreas Färber
6 */
7 #ifndef DT_BINDINGS_RESET_RTD1295_H
8 #define DT_BINDINGS_RESET_RTD1295_H
10 /* soft reset 1 */
11 #define RTD1295_RSTN_MISC 0
12 #define RTD1295_RSTN_NAT 1
13 #define RTD1295_RSTN_USB3_PHY0_POW 2
14 #define RTD1295_RSTN_GSPI 3
15 #define RTD1295_RSTN_USB3_P0_MDIO 4
16 #define RTD1295_RSTN_SATA_0 5
17 #define RTD1295_RSTN_USB 6
18 #define RTD1295_RSTN_SATA_PHY_0 7
19 #define RTD1295_RSTN_USB_PHY0 8
20 #define RTD1295_RSTN_USB_PHY1 9
21 #define RTD1295_RSTN_SATA_PHY_POW_0 10
22 #define RTD1295_RSTN_SATA_FUNC_EXIST_0 11
23 #define RTD1295_RSTN_HDMI 12
24 #define RTD1295_RSTN_VE1 13
25 #define RTD1295_RSTN_VE2 14
26 #define RTD1295_RSTN_VE3 15
27 #define RTD1295_RSTN_ETN 16
28 #define RTD1295_RSTN_AIO 17
29 #define RTD1295_RSTN_GPU 18
30 #define RTD1295_RSTN_TVE 19
31 #define RTD1295_RSTN_VO 20
32 #define RTD1295_RSTN_LVDS 21
33 #define RTD1295_RSTN_SE 22
34 #define RTD1295_RSTN_DCU 23
35 #define RTD1295_RSTN_DC_PHY 24
36 #define RTD1295_RSTN_CP 25
37 #define RTD1295_RSTN_MD 26
38 #define RTD1295_RSTN_TP 27
39 #define RTD1295_RSTN_AE 28
40 #define RTD1295_RSTN_NF 29
41 #define RTD1295_RSTN_MIPI 30
42 #define RTD1295_RSTN_RSA 31
44 /* soft reset 2 */
45 #define RTD1295_RSTN_ACPU 0
46 #define RTD1295_RSTN_JPEG 1
47 #define RTD1295_RSTN_USB_PHY3 2
48 #define RTD1295_RSTN_USB_PHY2 3
49 #define RTD1295_RSTN_USB3_PHY1_POW 4
50 #define RTD1295_RSTN_USB3_P1_MDIO 5
51 #define RTD1295_RSTN_PCIE0_STITCH 6
52 #define RTD1295_RSTN_PCIE0_PHY 7
53 #define RTD1295_RSTN_PCIE0 8
54 #define RTD1295_RSTN_PCR_CNT 9
55 #define RTD1295_RSTN_CR 10
56 #define RTD1295_RSTN_EMMC 11
57 #define RTD1295_RSTN_SDIO 12
58 #define RTD1295_RSTN_PCIE0_CORE 13
59 #define RTD1295_RSTN_PCIE0_POWER 14
60 #define RTD1295_RSTN_PCIE0_NONSTICH 15
61 #define RTD1295_RSTN_PCIE1_PHY 16
62 #define RTD1295_RSTN_PCIE1 17
63 #define RTD1295_RSTN_I2C_5 18
64 #define RTD1295_RSTN_PCIE1_STITCH 19
65 #define RTD1295_RSTN_PCIE1_CORE 20
66 #define RTD1295_RSTN_PCIE1_POWER 21
67 #define RTD1295_RSTN_PCIE1_NONSTICH 22
68 #define RTD1295_RSTN_I2C_4 23
69 #define RTD1295_RSTN_I2C_3 24
70 #define RTD1295_RSTN_I2C_2 25
71 #define RTD1295_RSTN_I2C_1 26
72 #define RTD1295_RSTN_UR2 27
73 #define RTD1295_RSTN_UR1 28
74 #define RTD1295_RSTN_MISC_SC 29
75 #define RTD1295_RSTN_CBUS_TX 30
76 #define RTD1295_RSTN_SDS_PHY 31
78 /* soft reset 4 */
79 #define RTD1295_RSTN_DCPHY_CRT 0
80 #define RTD1295_RSTN_DCPHY_ALERT_RX 1
81 #define RTD1295_RSTN_DCPHY_PTR 2
82 #define RTD1295_RSTN_DCPHY_LDO 3
83 #define RTD1295_RSTN_DCPHY_SSC_DIG 4
84 #define RTD1295_RSTN_HDMIRX 5
85 #define RTD1295_RSTN_CBUSRX 6
86 #define RTD1295_RSTN_SATA_PHY_POW_1 7
87 #define RTD1295_RSTN_SATA_FUNC_EXIST_1 8
88 #define RTD1295_RSTN_SATA_PHY_1 9
89 #define RTD1295_RSTN_SATA_1 10
90 #define RTD1295_RSTN_FAN 11
91 #define RTD1295_RSTN_HDMIRX_WRAP 12
92 #define RTD1295_RSTN_PCIE0_PHY_MDIO 13
93 #define RTD1295_RSTN_PCIE1_PHY_MDIO 14
94 #define RTD1295_RSTN_DISP 15
96 /* iso reset */
97 #define RTD1295_ISO_RSTN_IR 1
98 #define RTD1295_ISO_RSTN_CEC0 2
99 #define RTD1295_ISO_RSTN_CEC1 3
100 #define RTD1295_ISO_RSTN_DP 4
101 #define RTD1295_ISO_RSTN_CBUSTX 5
102 #define RTD1295_ISO_RSTN_CBUSRX 6
103 #define RTD1295_ISO_RSTN_EFUSE 7
104 #define RTD1295_ISO_RSTN_UR0 8
105 #define RTD1295_ISO_RSTN_GMAC 9
106 #define RTD1295_ISO_RSTN_GPHY 10
107 #define RTD1295_ISO_RSTN_I2C_0 11
108 #define RTD1295_ISO_RSTN_I2C_1 12
109 #define RTD1295_ISO_RSTN_CBUS 13
111 #endif