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ALSA: usb-audio: mixer: volume quirk for ESS Technology Asus USB DAC
[linux/fpc-iii.git] / drivers / regulator / pfuze100-regulator.c
blob69a377ab260413db25d7d82263f63d37380dc645
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
4
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/err.h>
9 #include <linux/of.h>
10 #include <linux/of_device.h>
11 #include <linux/regulator/of_regulator.h>
12 #include <linux/platform_device.h>
13 #include <linux/regulator/driver.h>
14 #include <linux/regulator/machine.h>
15 #include <linux/regulator/pfuze100.h>
16 #include <linux/i2c.h>
17 #include <linux/slab.h>
18 #include <linux/regmap.h>
19
20 #define PFUZE_FLAG_DISABLE_SW BIT(1)
21
22 #define PFUZE_NUMREGS 128
23 #define PFUZE100_VOL_OFFSET 0
24 #define PFUZE100_STANDBY_OFFSET 1
25 #define PFUZE100_MODE_OFFSET 3
26 #define PFUZE100_CONF_OFFSET 4
27
28 #define PFUZE100_DEVICEID 0x0
29 #define PFUZE100_REVID 0x3
30 #define PFUZE100_FABID 0x4
31
32 #define PFUZE100_COINVOL 0x1a
33 #define PFUZE100_SW1ABVOL 0x20
34 #define PFUZE100_SW1CVOL 0x2e
35 #define PFUZE100_SW2VOL 0x35
36 #define PFUZE100_SW3AVOL 0x3c
37 #define PFUZE100_SW3BVOL 0x43
38 #define PFUZE100_SW4VOL 0x4a
39 #define PFUZE100_SWBSTCON1 0x66
40 #define PFUZE100_VREFDDRCON 0x6a
41 #define PFUZE100_VSNVSVOL 0x6b
42 #define PFUZE100_VGEN1VOL 0x6c
43 #define PFUZE100_VGEN2VOL 0x6d
44 #define PFUZE100_VGEN3VOL 0x6e
45 #define PFUZE100_VGEN4VOL 0x6f
46 #define PFUZE100_VGEN5VOL 0x70
47 #define PFUZE100_VGEN6VOL 0x71
48
49 enum chips { PFUZE100, PFUZE200, PFUZE3000 = 3, PFUZE3001 = 0x31, };
50
51 struct pfuze_regulator {
52 struct regulator_desc desc;
53 unsigned char stby_reg;
54 unsigned char stby_mask;
55 bool sw_reg;
56 };
57
58 struct pfuze_chip {
59 int chip_id;
60 int flags;
61 struct regmap *regmap;
62 struct device *dev;
63 struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
64 struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR];
65 struct pfuze_regulator *pfuze_regulators;
66 };
67
68 static const int pfuze100_swbst[] = {
69 5000000, 5050000, 5100000, 5150000,
70 };
71
72 static const int pfuze100_vsnvs[] = {
73 1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
74 };
75
76 static const int pfuze100_coin[] = {
77 2500000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
78 };
79
80 static const int pfuze3000_sw1a[] = {
81 700000, 725000, 750000, 775000, 800000, 825000, 850000, 875000,
82 900000, 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000,
83 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000,
84 1300000, 1325000, 1350000, 1375000, 1400000, 1425000, 1800000, 3300000,
85 };
86
87 static const int pfuze3000_sw2lo[] = {
88 1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000,
89 };
90
91 static const int pfuze3000_sw2hi[] = {
92 2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000,
93 };
94
95 static const struct i2c_device_id pfuze_device_id[] = {
96 {.name = "pfuze100", .driver_data = PFUZE100},
97 {.name = "pfuze200", .driver_data = PFUZE200},
98 {.name = "pfuze3000", .driver_data = PFUZE3000},
99 {.name = "pfuze3001", .driver_data = PFUZE3001},
100 { }
101 };
102 MODULE_DEVICE_TABLE(i2c, pfuze_device_id);
103
104 static const struct of_device_id pfuze_dt_ids[] = {
105 { .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
106 { .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
107 { .compatible = "fsl,pfuze3000", .data = (void *)PFUZE3000},
108 { .compatible = "fsl,pfuze3001", .data = (void *)PFUZE3001},
109 { }
110 };
111 MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
112
113 static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
114 {
115 struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
116 int id = rdev_get_id(rdev);
117 bool reg_has_ramp_delay;
118 unsigned int ramp_bits;
119 int ret;
120
121 switch (pfuze100->chip_id) {
122 case PFUZE3001:
123 /* no dynamic voltage scaling for PF3001 */
124 reg_has_ramp_delay = false;
125 break;
126 case PFUZE3000:
127 reg_has_ramp_delay = (id < PFUZE3000_SWBST);
128 break;
129 case PFUZE200:
130 reg_has_ramp_delay = (id < PFUZE200_SWBST);
131 break;
132 case PFUZE100:
133 default:
134 reg_has_ramp_delay = (id < PFUZE100_SWBST);
135 break;
136 }
137
138 if (reg_has_ramp_delay) {
139 ramp_delay = 12500 / ramp_delay;
140 ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
141 ret = regmap_update_bits(pfuze100->regmap,
142 rdev->desc->vsel_reg + 4,
143 0xc0, ramp_bits << 6);
144 if (ret < 0)
145 dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
146 } else {
147 ret = -EACCES;
148 }
149
150 return ret;
151 }
152
153 static const struct regulator_ops pfuze100_ldo_regulator_ops = {
154 .enable = regulator_enable_regmap,
155 .disable = regulator_disable_regmap,
156 .is_enabled = regulator_is_enabled_regmap,
157 .list_voltage = regulator_list_voltage_linear,
158 .set_voltage_sel = regulator_set_voltage_sel_regmap,
159 .get_voltage_sel = regulator_get_voltage_sel_regmap,
160 };
161
162 static const struct regulator_ops pfuze100_fixed_regulator_ops = {
163 .enable = regulator_enable_regmap,
164 .disable = regulator_disable_regmap,
165 .is_enabled = regulator_is_enabled_regmap,
166 .list_voltage = regulator_list_voltage_linear,
167 };
168
169 static const struct regulator_ops pfuze100_sw_regulator_ops = {
170 .list_voltage = regulator_list_voltage_linear,
171 .set_voltage_sel = regulator_set_voltage_sel_regmap,
172 .get_voltage_sel = regulator_get_voltage_sel_regmap,
173 .set_voltage_time_sel = regulator_set_voltage_time_sel,
174 .set_ramp_delay = pfuze100_set_ramp_delay,
175 };
176
177 static const struct regulator_ops pfuze100_sw_disable_regulator_ops = {
178 .enable = regulator_enable_regmap,
179 .disable = regulator_disable_regmap,
180 .is_enabled = regulator_is_enabled_regmap,
181 .list_voltage = regulator_list_voltage_linear,
182 .set_voltage_sel = regulator_set_voltage_sel_regmap,
183 .get_voltage_sel = regulator_get_voltage_sel_regmap,
184 .set_voltage_time_sel = regulator_set_voltage_time_sel,
185 .set_ramp_delay = pfuze100_set_ramp_delay,
186 };
187
188 static const struct regulator_ops pfuze100_swb_regulator_ops = {
189 .enable = regulator_enable_regmap,
190 .disable = regulator_disable_regmap,
191 .is_enabled = regulator_is_enabled_regmap,
192 .list_voltage = regulator_list_voltage_table,
193 .map_voltage = regulator_map_voltage_ascend,
194 .set_voltage_sel = regulator_set_voltage_sel_regmap,
195 .get_voltage_sel = regulator_get_voltage_sel_regmap,
196
197 };
198
199 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \
200 [_chip ## _ ## _name] = { \
201 .desc = { \
202 .name = #_name, \
203 .n_voltages = 1, \
204 .ops = &pfuze100_fixed_regulator_ops, \
205 .type = REGULATOR_VOLTAGE, \
206 .id = _chip ## _ ## _name, \
207 .owner = THIS_MODULE, \
208 .min_uV = (voltage), \
209 .enable_reg = (base), \
210 .enable_mask = 0x10, \
211 }, \
212 }
213
214 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \
215 [_chip ## _ ## _name] = { \
216 .desc = { \
217 .name = #_name,\
218 .n_voltages = ((max) - (min)) / (step) + 1, \
219 .ops = &pfuze100_sw_regulator_ops, \
220 .type = REGULATOR_VOLTAGE, \
221 .id = _chip ## _ ## _name, \
222 .owner = THIS_MODULE, \
223 .min_uV = (min), \
224 .uV_step = (step), \
225 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
226 .vsel_mask = 0x3f, \
227 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \
228 .enable_mask = 0xf, \
229 }, \
230 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
231 .stby_mask = 0x3f, \
232 .sw_reg = true, \
233 }
234
235 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \
236 [_chip ## _ ## _name] = { \
237 .desc = { \
238 .name = #_name, \
239 .n_voltages = ARRAY_SIZE(voltages), \
240 .ops = &pfuze100_swb_regulator_ops, \
241 .type = REGULATOR_VOLTAGE, \
242 .id = _chip ## _ ## _name, \
243 .owner = THIS_MODULE, \
244 .volt_table = voltages, \
245 .vsel_reg = (base), \
246 .vsel_mask = (mask), \
247 .enable_reg = (base), \
248 .enable_mask = 0x48, \
249 }, \
250 }
251
252 #define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \
253 [_chip ## _ ## _name] = { \
254 .desc = { \
255 .name = #_name, \
256 .n_voltages = ((max) - (min)) / (step) + 1, \
257 .ops = &pfuze100_ldo_regulator_ops, \
258 .type = REGULATOR_VOLTAGE, \
259 .id = _chip ## _ ## _name, \
260 .owner = THIS_MODULE, \
261 .min_uV = (min), \
262 .uV_step = (step), \
263 .vsel_reg = (base), \
264 .vsel_mask = 0xf, \
265 .enable_reg = (base), \
266 .enable_mask = 0x10, \
267 }, \
268 .stby_reg = (base), \
269 .stby_mask = 0x20, \
270 }
271
272 #define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages) \
273 [_chip ## _ ## _name] = { \
274 .desc = { \
275 .name = #_name, \
276 .n_voltages = ARRAY_SIZE(voltages), \
277 .ops = &pfuze100_swb_regulator_ops, \
278 .type = REGULATOR_VOLTAGE, \
279 .id = _chip ## _ ## _name, \
280 .owner = THIS_MODULE, \
281 .volt_table = voltages, \
282 .vsel_reg = (base), \
283 .vsel_mask = (mask), \
284 .enable_reg = (base), \
285 .enable_mask = 0x8, \
286 }, \
287 }
288
289 #define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step) { \
290 .desc = { \
291 .name = #_name, \
292 .n_voltages = ((max) - (min)) / (step) + 1, \
293 .ops = &pfuze100_ldo_regulator_ops, \
294 .type = REGULATOR_VOLTAGE, \
295 .id = _chip ## _ ## _name, \
296 .owner = THIS_MODULE, \
297 .min_uV = (min), \
298 .uV_step = (step), \
299 .vsel_reg = (base), \
300 .vsel_mask = 0x3, \
301 .enable_reg = (base), \
302 .enable_mask = 0x10, \
303 }, \
304 .stby_reg = (base), \
305 .stby_mask = 0x20, \
306 }
307
308
309 #define PFUZE3000_SW2_REG(_chip, _name, base, min, max, step) { \
310 .desc = { \
311 .name = #_name,\
312 .n_voltages = ((max) - (min)) / (step) + 1, \
313 .ops = &pfuze100_sw_regulator_ops, \
314 .type = REGULATOR_VOLTAGE, \
315 .id = _chip ## _ ## _name, \
316 .owner = THIS_MODULE, \
317 .min_uV = (min), \
318 .uV_step = (step), \
319 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
320 .vsel_mask = 0x7, \
321 }, \
322 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
323 .stby_mask = 0x7, \
324 }
325
326 #define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step) { \
327 .desc = { \
328 .name = #_name,\
329 .n_voltages = ((max) - (min)) / (step) + 1, \
330 .ops = &pfuze100_sw_regulator_ops, \
331 .type = REGULATOR_VOLTAGE, \
332 .id = _chip ## _ ## _name, \
333 .owner = THIS_MODULE, \
334 .min_uV = (min), \
335 .uV_step = (step), \
336 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
337 .vsel_mask = 0xf, \
338 }, \
339 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
340 .stby_mask = 0xf, \
341 }
342
343 /* PFUZE100 */
344 static struct pfuze_regulator pfuze100_regulators[] = {
345 PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
346 PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
347 PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
348 PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
349 PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
350 PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
351 PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
352 PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
353 PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000),
354 PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
355 PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
356 PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
357 PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
358 PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
359 PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
360 };
361
362 static struct pfuze_regulator pfuze200_regulators[] = {
363 PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
364 PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
365 PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
366 PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
367 PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
368 PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
369 PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000),
370 PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
371 PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
372 PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
373 PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
374 PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
375 PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
376 PFUZE100_COIN_REG(PFUZE200, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
377 };
378
379 static struct pfuze_regulator pfuze3000_regulators[] = {
380 PFUZE100_SWB_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
381 PFUZE100_SW_REG(PFUZE3000, SW1B, PFUZE100_SW1CVOL, 700000, 1475000, 25000),
382 PFUZE100_SWB_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
383 PFUZE3000_SW3_REG(PFUZE3000, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
384 PFUZE100_SWB_REG(PFUZE3000, SWBST, PFUZE100_SWBSTCON1, 0x3, pfuze100_swbst),
385 PFUZE100_SWB_REG(PFUZE3000, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
386 PFUZE100_FIXED_REG(PFUZE3000, VREFDDR, PFUZE100_VREFDDRCON, 750000),
387 PFUZE100_VGEN_REG(PFUZE3000, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
388 PFUZE100_VGEN_REG(PFUZE3000, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
389 PFUZE3000_VCC_REG(PFUZE3000, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
390 PFUZE3000_VCC_REG(PFUZE3000, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
391 PFUZE100_VGEN_REG(PFUZE3000, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
392 PFUZE100_VGEN_REG(PFUZE3000, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
393 };
394
395 static struct pfuze_regulator pfuze3001_regulators[] = {
396 PFUZE100_SWB_REG(PFUZE3001, SW1, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
397 PFUZE100_SWB_REG(PFUZE3001, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
398 PFUZE3000_SW3_REG(PFUZE3001, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
399 PFUZE100_SWB_REG(PFUZE3001, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
400 PFUZE100_VGEN_REG(PFUZE3001, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
401 PFUZE100_VGEN_REG(PFUZE3001, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
402 PFUZE3000_VCC_REG(PFUZE3001, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
403 PFUZE3000_VCC_REG(PFUZE3001, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
404 PFUZE100_VGEN_REG(PFUZE3001, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
405 PFUZE100_VGEN_REG(PFUZE3001, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
406 };
407
408 #ifdef CONFIG_OF
409 /* PFUZE100 */
410 static struct of_regulator_match pfuze100_matches[] = {
411 { .name = "sw1ab", },
412 { .name = "sw1c", },
413 { .name = "sw2", },
414 { .name = "sw3a", },
415 { .name = "sw3b", },
416 { .name = "sw4", },
417 { .name = "swbst", },
418 { .name = "vsnvs", },
419 { .name = "vrefddr", },
420 { .name = "vgen1", },
421 { .name = "vgen2", },
422 { .name = "vgen3", },
423 { .name = "vgen4", },
424 { .name = "vgen5", },
425 { .name = "vgen6", },
426 };
427
428 /* PFUZE200 */
429 static struct of_regulator_match pfuze200_matches[] = {
430
431 { .name = "sw1ab", },
432 { .name = "sw2", },
433 { .name = "sw3a", },
434 { .name = "sw3b", },
435 { .name = "swbst", },
436 { .name = "vsnvs", },
437 { .name = "vrefddr", },
438 { .name = "vgen1", },
439 { .name = "vgen2", },
440 { .name = "vgen3", },
441 { .name = "vgen4", },
442 { .name = "vgen5", },
443 { .name = "vgen6", },
444 { .name = "coin", },
445 };
446
447 /* PFUZE3000 */
448 static struct of_regulator_match pfuze3000_matches[] = {
449
450 { .name = "sw1a", },
451 { .name = "sw1b", },
452 { .name = "sw2", },
453 { .name = "sw3", },
454 { .name = "swbst", },
455 { .name = "vsnvs", },
456 { .name = "vrefddr", },
457 { .name = "vldo1", },
458 { .name = "vldo2", },
459 { .name = "vccsd", },
460 { .name = "v33", },
461 { .name = "vldo3", },
462 { .name = "vldo4", },
463 };
464
465 /* PFUZE3001 */
466 static struct of_regulator_match pfuze3001_matches[] = {
467
468 { .name = "sw1", },
469 { .name = "sw2", },
470 { .name = "sw3", },
471 { .name = "vsnvs", },
472 { .name = "vldo1", },
473 { .name = "vldo2", },
474 { .name = "vccsd", },
475 { .name = "v33", },
476 { .name = "vldo3", },
477 { .name = "vldo4", },
478 };
479
480 static struct of_regulator_match *pfuze_matches;
481
482 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
483 {
484 struct device *dev = chip->dev;
485 struct device_node *np, *parent;
486 int ret;
487
488 np = of_node_get(dev->of_node);
489 if (!np)
490 return -EINVAL;
491
492 if (of_property_read_bool(np, "fsl,pfuze-support-disable-sw"))
493 chip->flags |= PFUZE_FLAG_DISABLE_SW;
494
495 parent = of_get_child_by_name(np, "regulators");
496 if (!parent) {
497 dev_err(dev, "regulators node not found\n");
498 return -EINVAL;
499 }
500
501 switch (chip->chip_id) {
502 case PFUZE3001:
503 pfuze_matches = pfuze3001_matches;
504 ret = of_regulator_match(dev, parent, pfuze3001_matches,
505 ARRAY_SIZE(pfuze3001_matches));
506 break;
507 case PFUZE3000:
508 pfuze_matches = pfuze3000_matches;
509 ret = of_regulator_match(dev, parent, pfuze3000_matches,
510 ARRAY_SIZE(pfuze3000_matches));
511 break;
512 case PFUZE200:
513 pfuze_matches = pfuze200_matches;
514 ret = of_regulator_match(dev, parent, pfuze200_matches,
515 ARRAY_SIZE(pfuze200_matches));
516 break;
517
518 case PFUZE100:
519 default:
520 pfuze_matches = pfuze100_matches;
521 ret = of_regulator_match(dev, parent, pfuze100_matches,
522 ARRAY_SIZE(pfuze100_matches));
523 break;
524 }
525
526 of_node_put(parent);
527 if (ret < 0) {
528 dev_err(dev, "Error parsing regulator init data: %d\n",
529 ret);
530 return ret;
531 }
532
533 return 0;
534 }
535
536 static inline struct regulator_init_data *match_init_data(int index)
537 {
538 return pfuze_matches[index].init_data;
539 }
540
541 static inline struct device_node *match_of_node(int index)
542 {
543 return pfuze_matches[index].of_node;
544 }
545 #else
546 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
547 {
548 return 0;
549 }
550
551 static inline struct regulator_init_data *match_init_data(int index)
552 {
553 return NULL;
554 }
555
556 static inline struct device_node *match_of_node(int index)
557 {
558 return NULL;
559 }
560 #endif
561
562 static int pfuze_identify(struct pfuze_chip *pfuze_chip)
563 {
564 unsigned int value;
565 int ret;
566
567 ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value);
568 if (ret)
569 return ret;
570
571 if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) {
572 /*
573 * Freescale misprogrammed 1-3% of parts prior to week 8 of 2013
574 * as ID=8 in PFUZE100
575 */
576 dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
577 } else if ((value & 0x0f) != pfuze_chip->chip_id &&
578 (value & 0xf0) >> 4 != pfuze_chip->chip_id &&
579 (value != pfuze_chip->chip_id)) {
580 /* device id NOT match with your setting */
581 dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
582 return -ENODEV;
583 }
584
585 ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
586 if (ret)
587 return ret;
588 dev_info(pfuze_chip->dev,
589 "Full layer: %x, Metal layer: %x\n",
590 (value & 0xf0) >> 4, value & 0x0f);
591
592 ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value);
593 if (ret)
594 return ret;
595 dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n",
596 (value & 0xc) >> 2, value & 0x3);
597
598 return 0;
599 }
600
601 static const struct regmap_config pfuze_regmap_config = {
602 .reg_bits = 8,
603 .val_bits = 8,
604 .max_register = PFUZE_NUMREGS - 1,
605 .cache_type = REGCACHE_RBTREE,
606 };
607
608 static int pfuze100_regulator_probe(struct i2c_client *client,
609 const struct i2c_device_id *id)
610 {
611 struct pfuze_chip *pfuze_chip;
612 struct pfuze_regulator_platform_data *pdata =
613 dev_get_platdata(&client->dev);
614 struct regulator_config config = { };
615 int i, ret;
616 const struct of_device_id *match;
617 u32 regulator_num;
618 u32 sw_check_start, sw_check_end, sw_hi = 0x40;
619
620 pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
621 GFP_KERNEL);
622 if (!pfuze_chip)
623 return -ENOMEM;
624
625 if (client->dev.of_node) {
626 match = of_match_device(of_match_ptr(pfuze_dt_ids),
627 &client->dev);
628 if (!match) {
629 dev_err(&client->dev, "Error: No device match found\n");
630 return -ENODEV;
631 }
632 pfuze_chip->chip_id = (int)(long)match->data;
633 } else if (id) {
634 pfuze_chip->chip_id = id->driver_data;
635 } else {
636 dev_err(&client->dev, "No dts match or id table match found\n");
637 return -ENODEV;
638 }
639
640 i2c_set_clientdata(client, pfuze_chip);
641 pfuze_chip->dev = &client->dev;
642
643 pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
644 if (IS_ERR(pfuze_chip->regmap)) {
645 ret = PTR_ERR(pfuze_chip->regmap);
646 dev_err(&client->dev,
647 "regmap allocation failed with err %d\n", ret);
648 return ret;
649 }
650
651 ret = pfuze_identify(pfuze_chip);
652 if (ret) {
653 dev_err(&client->dev, "unrecognized pfuze chip ID!\n");
654 return ret;
655 }
656
657 /* use the right regulators after identify the right device */
658 switch (pfuze_chip->chip_id) {
659 case PFUZE3001:
660 pfuze_chip->pfuze_regulators = pfuze3001_regulators;
661 regulator_num = ARRAY_SIZE(pfuze3001_regulators);
662 sw_check_start = PFUZE3001_SW2;
663 sw_check_end = PFUZE3001_SW2;
664 sw_hi = 1 << 3;
665 break;
666 case PFUZE3000:
667 pfuze_chip->pfuze_regulators = pfuze3000_regulators;
668 regulator_num = ARRAY_SIZE(pfuze3000_regulators);
669 sw_check_start = PFUZE3000_SW2;
670 sw_check_end = PFUZE3000_SW2;
671 sw_hi = 1 << 3;
672 break;
673 case PFUZE200:
674 pfuze_chip->pfuze_regulators = pfuze200_regulators;
675 regulator_num = ARRAY_SIZE(pfuze200_regulators);
676 sw_check_start = PFUZE200_SW2;
677 sw_check_end = PFUZE200_SW3B;
678 break;
679 case PFUZE100:
680 default:
681 pfuze_chip->pfuze_regulators = pfuze100_regulators;
682 regulator_num = ARRAY_SIZE(pfuze100_regulators);
683 sw_check_start = PFUZE100_SW2;
684 sw_check_end = PFUZE100_SW4;
685 break;
686 }
687 dev_info(&client->dev, "pfuze%s found.\n",
688 (pfuze_chip->chip_id == PFUZE100) ? "100" :
689 (((pfuze_chip->chip_id == PFUZE200) ? "200" :
690 ((pfuze_chip->chip_id == PFUZE3000) ? "3000" : "3001"))));
691
692 memcpy(pfuze_chip->regulator_descs, pfuze_chip->pfuze_regulators,
693 sizeof(pfuze_chip->regulator_descs));
694
695 ret = pfuze_parse_regulators_dt(pfuze_chip);
696 if (ret)
697 return ret;
698
699 for (i = 0; i < regulator_num; i++) {
700 struct regulator_init_data *init_data;
701 struct regulator_desc *desc;
702 int val;
703
704 desc = &pfuze_chip->regulator_descs[i].desc;
705
706 if (pdata)
707 init_data = pdata->init_data[i];
708 else
709 init_data = match_init_data(i);
710
711 /* SW2~SW4 high bit check and modify the voltage value table */
712 if (i >= sw_check_start && i <= sw_check_end) {
713 ret = regmap_read(pfuze_chip->regmap,
714 desc->vsel_reg, &val);
715 if (ret) {
716 dev_err(&client->dev, "Fails to read from the register.\n");
717 return ret;
718 }
719
720 if (val & sw_hi) {
721 if (pfuze_chip->chip_id == PFUZE3000 ||
722 pfuze_chip->chip_id == PFUZE3001) {
723 desc->volt_table = pfuze3000_sw2hi;
724 desc->n_voltages = ARRAY_SIZE(pfuze3000_sw2hi);
725 } else {
726 desc->min_uV = 800000;
727 desc->uV_step = 50000;
728 desc->n_voltages = 51;
729 }
730 }
731 }
732
733 /*
734 * Allow SW regulators to turn off. Checking it trough a flag is
735 * a workaround to keep the backward compatibility with existing
736 * old dtb's which may relay on the fact that we didn't disable
737 * the switched regulator till yet.
738 */
739 if (pfuze_chip->flags & PFUZE_FLAG_DISABLE_SW) {
740 if (pfuze_chip->regulator_descs[i].sw_reg) {
741 desc->ops = &pfuze100_sw_disable_regulator_ops;
742 desc->enable_val = 0x8;
743 desc->disable_val = 0x0;
744 desc->enable_time = 500;
745 }
746 }
747
748 config.dev = &client->dev;
749 config.init_data = init_data;
750 config.driver_data = pfuze_chip;
751 config.of_node = match_of_node(i);
752
753 pfuze_chip->regulators[i] =
754 devm_regulator_register(&client->dev, desc, &config);
755 if (IS_ERR(pfuze_chip->regulators[i])) {
756 dev_err(&client->dev, "register regulator%s failed\n",
757 pfuze_chip->pfuze_regulators[i].desc.name);
758 return PTR_ERR(pfuze_chip->regulators[i]);
759 }
760 }
761
762 return 0;
763 }
764
765 static struct i2c_driver pfuze_driver = {
766 .id_table = pfuze_device_id,
767 .driver = {
768 .name = "pfuze100-regulator",
769 .of_match_table = pfuze_dt_ids,
770 },
771 .probe = pfuze100_regulator_probe,
772 };
773 module_i2c_driver(pfuze_driver);
774
775 MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
776 MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/200/3000/3001 PMIC");
777 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support