drivers/usb/host/xhci-hub.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11
  12 #include <linux/slab.h>
  13 #include <asm/unaligned.h>
  14
  15 #include "xhci.h"
  16 #include "xhci-trace.h"
  17
  18 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  19 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  20                          PORT_RC | PORT_PLC | PORT_PE)
  21
  22 /* USB 3 BOS descriptor and a capability descriptors, combined.
  23  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  24  */
  25 static u8 usb_bos_descriptor [] = {
  26         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  27         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  28         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  29         0x1,                            /*  __u8 bNumDeviceCaps */
  30         /* First device capability, SuperSpeed */
  31         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  32         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  33         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  34         0x00,                           /* bmAttributes, LTM off by default */
  35         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  36         0x03,                           /* bFunctionalitySupport,
  37                                            USB 3.0 speed only */
  38         0x00,                           /* bU1DevExitLat, set later. */
  39         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  40         /* Second device capability, SuperSpeedPlus */
  41         0x1c,                           /* bLength 28, will be adjusted later */
  42         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  43         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  44         0x00,                           /* bReserved 0 */
  45         0x23, 0x00, 0x00, 0x00,         /* bmAttributes, SSAC=3 SSIC=1 */
  46         0x01, 0x00,                     /* wFunctionalitySupport */
  47         0x00, 0x00,                     /* wReserved 0 */
  48         /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
  49         0x34, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, rx, ID = 4 */
  50         0xb4, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, tx, ID = 4 */
  51         0x35, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, rx, ID = 5 */
  52         0xb5, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, tx, ID = 5 */
  53 };
  54
  55 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  56                                      u16 wLength)
  57 {
  58         struct xhci_port_cap *port_cap = NULL;
  59         int i, ssa_count;
  60         u32 temp;
  61         u16 desc_size, ssp_cap_size, ssa_size = 0;
  62         bool usb3_1 = false;
  63
  64         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  65         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  66
  67         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  68         for (i = 0; i < xhci->num_port_caps; i++) {
  69                 if (xhci->port_caps[i].maj_rev == 0x03 &&
  70                     xhci->port_caps[i].min_rev >= 0x01) {
  71                         usb3_1 = true;
  72                         port_cap = &xhci->port_caps[i];
  73                         break;
  74                 }
  75         }
  76
  77         if (usb3_1) {
  78                 /* does xhci provide a PSI table for SSA speed attributes? */
  79                 if (port_cap->psi_count) {
  80                         /* two SSA entries for each unique PSI ID, RX and TX */
  81                         ssa_count = port_cap->psi_uid_count * 2;
  82                         ssa_size = ssa_count * sizeof(u32);
  83                         ssp_cap_size -= 16; /* skip copying the default SSA */
  84                 }
  85                 desc_size += ssp_cap_size;
  86         }
  87         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  88
  89         if (usb3_1) {
  90                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  91                 buf[4] += 1;
  92                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  93         }
  94
  95         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  96                 return wLength;
  97
  98         /* Indicate whether the host has LTM support. */
  99         temp = readl(&xhci->cap_regs->hcc_params);
 100         if (HCC_LTC(temp))
 101                 buf[8] |= USB_LTM_SUPPORT;
 102
 103         /* Set the U1 and U2 exit latencies. */
 104         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 105                 temp = readl(&xhci->cap_regs->hcs_params3);
 106                 buf[12] = HCS_U1_LATENCY(temp);
 107                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 108         }
 109
 110         /* If PSI table exists, add the custom speed attributes from it */
 111         if (usb3_1 && port_cap->psi_count) {
 112                 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
 113                 int offset;
 114
 115                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 116
 117                 if (wLength < desc_size)
 118                         return wLength;
 119                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 120
 121                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 122                 bm_attrib = (ssa_count - 1) & 0x1f;
 123                 bm_attrib |= (port_cap->psi_uid_count - 1) << 5;
 124                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 125
 126                 if (wLength < desc_size + ssa_size)
 127                         return wLength;
 128                 /*
 129                  * Create the Sublink Speed Attributes (SSA) array.
 130                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 131                  * but link type bits 7:6 differ for values 01b and 10b.
 132                  * xhci has also only one PSI entry for a symmetric link when
 133                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 134                  */
 135                 offset = desc_size;
 136                 for (i = 0; i < port_cap->psi_count; i++) {
 137                         psi = port_cap->psi[i];
 138                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 139                         psi_exp = XHCI_EXT_PORT_PSIE(psi);
 140                         psi_mant = XHCI_EXT_PORT_PSIM(psi);
 141
 142                         /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
 143                         for (; psi_exp < 3; psi_exp++)
 144                                 psi_mant /= 1000;
 145                         if (psi_mant >= 10)
 146                                 psi |= BIT(14);
 147
 148                         if ((psi & PLT_MASK) == PLT_SYM) {
 149                         /* Symmetric, create SSA RX and TX from one PSI entry */
 150                                 put_unaligned_le32(psi, &buf[offset]);
 151                                 psi |= 1 << 7;  /* turn entry to TX */
 152                                 offset += 4;
 153                                 if (offset >= desc_size + ssa_size)
 154                                         return desc_size + ssa_size;
 155                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 156                                 /* Asymetric RX, flip bits 7:6 for SSA */
 157                                 psi ^= PLT_MASK;
 158                         }
 159                         put_unaligned_le32(psi, &buf[offset]);
 160                         offset += 4;
 161                         if (offset >= desc_size + ssa_size)
 162                                 return desc_size + ssa_size;
 163                 }
 164         }
 165         /* ssa_size is 0 for other than usb 3.1 hosts */
 166         return desc_size + ssa_size;
 167 }
 168
 169 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 170                 struct usb_hub_descriptor *desc, int ports)
 171 {
 172         u16 temp;
 173
 174         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
 175         desc->bHubContrCurrent = 0;
 176
 177         desc->bNbrPorts = ports;
 178         temp = 0;
 179         /* Bits 1:0 - support per-port power switching, or power always on */
 180         if (HCC_PPC(xhci->hcc_params))
 181                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 182         else
 183                 temp |= HUB_CHAR_NO_LPSM;
 184         /* Bit  2 - root hubs are not part of a compound device */
 185         /* Bits 4:3 - individual port over current protection */
 186         temp |= HUB_CHAR_INDV_PORT_OCPM;
 187         /* Bits 6:5 - no TTs in root ports */
 188         /* Bit  7 - no port indicators */
 189         desc->wHubCharacteristics = cpu_to_le16(temp);
 190 }
 191
 192 /* Fill in the USB 2.0 roothub descriptor */
 193 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 194                 struct usb_hub_descriptor *desc)
 195 {
 196         int ports;
 197         u16 temp;
 198         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 199         u32 portsc;
 200         unsigned int i;
 201         struct xhci_hub *rhub;
 202
 203         rhub = &xhci->usb2_rhub;
 204         ports = rhub->num_ports;
 205         xhci_common_hub_descriptor(xhci, desc, ports);
 206         desc->bDescriptorType = USB_DT_HUB;
 207         temp = 1 + (ports / 8);
 208         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 209
 210         /* The Device Removable bits are reported on a byte granularity.
 211          * If the port doesn't exist within that byte, the bit is set to 0.
 212          */
 213         memset(port_removable, 0, sizeof(port_removable));
 214         for (i = 0; i < ports; i++) {
 215                 portsc = readl(rhub->ports[i]->addr);
 216                 /* If a device is removable, PORTSC reports a 0, same as in the
 217                  * hub descriptor DeviceRemovable bits.
 218                  */
 219                 if (portsc & PORT_DEV_REMOVE)
 220                         /* This math is hairy because bit 0 of DeviceRemovable
 221                          * is reserved, and bit 1 is for port 1, etc.
 222                          */
 223                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 224         }
 225
 226         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 227          * ports on it.  The USB 2.0 specification says that there are two
 228          * variable length fields at the end of the hub descriptor:
 229          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 230          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 231          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 232          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 233          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 234          * set of ports that actually exist.
 235          */
 236         memset(desc->u.hs.DeviceRemovable, 0xff,
 237                         sizeof(desc->u.hs.DeviceRemovable));
 238         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 239                         sizeof(desc->u.hs.PortPwrCtrlMask));
 240
 241         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 242                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 243                                 sizeof(__u8));
 244 }
 245
 246 /* Fill in the USB 3.0 roothub descriptor */
 247 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 248                 struct usb_hub_descriptor *desc)
 249 {
 250         int ports;
 251         u16 port_removable;
 252         u32 portsc;
 253         unsigned int i;
 254         struct xhci_hub *rhub;
 255
 256         rhub = &xhci->usb3_rhub;
 257         ports = rhub->num_ports;
 258         xhci_common_hub_descriptor(xhci, desc, ports);
 259         desc->bDescriptorType = USB_DT_SS_HUB;
 260         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 261
 262         /* header decode latency should be zero for roothubs,
 263          * see section 4.23.5.2.
 264          */
 265         desc->u.ss.bHubHdrDecLat = 0;
 266         desc->u.ss.wHubDelay = 0;
 267
 268         port_removable = 0;
 269         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 270         for (i = 0; i < ports; i++) {
 271                 portsc = readl(rhub->ports[i]->addr);
 272                 if (portsc & PORT_DEV_REMOVE)
 273                         port_removable |= 1 << (i + 1);
 274         }
 275
 276         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 277 }
 278
 279 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 280                 struct usb_hub_descriptor *desc)
 281 {
 282
 283         if (hcd->speed >= HCD_USB3)
 284                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 285         else
 286                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 287
 288 }
 289
 290 static unsigned int xhci_port_speed(unsigned int port_status)
 291 {
 292         if (DEV_LOWSPEED(port_status))
 293                 return USB_PORT_STAT_LOW_SPEED;
 294         if (DEV_HIGHSPEED(port_status))
 295                 return USB_PORT_STAT_HIGH_SPEED;
 296         /*
 297          * FIXME: Yes, we should check for full speed, but the core uses that as
 298          * a default in portspeed() in usb/core/hub.c (which is the only place
 299          * USB_PORT_STAT_*_SPEED is used).
 300          */
 301         return 0;
 302 }
 303
 304 /*
 305  * These bits are Read Only (RO) and should be saved and written to the
 306  * registers: 0, 3, 10:13, 30
 307  * connect status, over-current status, port speed, and device removable.
 308  * connect status and port speed are also sticky - meaning they're in
 309  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 310  */
 311 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 312 /*
 313  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 314  * bits 5:8, 9, 14:15, 25:27
 315  * link state, port power, port indicator state, "wake on" enable state
 316  */
 317 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 318 /*
 319  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 320  * bit 4 (port reset)
 321  */
 322 #define XHCI_PORT_RW1S  ((1<<4))
 323 /*
 324  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 325  * bits 1, 17, 18, 19, 20, 21, 22, 23
 326  * port enable/disable, and
 327  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 328  * over-current, reset, link state, and L1 change
 329  */
 330 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 331 /*
 332  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 333  * latched in
 334  */
 335 #define XHCI_PORT_RW    ((1<<16))
 336 /*
 337  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 338  * bits 2, 24, 28:31
 339  */
 340 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 341
 342 /*
 343  * Given a port state, this function returns a value that would result in the
 344  * port being in the same state, if the value was written to the port status
 345  * control register.
 346  * Save Read Only (RO) bits and save read/write bits where
 347  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 348  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 349  */
 350 u32 xhci_port_state_to_neutral(u32 state)
 351 {
 352         /* Save read-only status and port state */
 353         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 354 }
 355
 356 /*
 357  * find slot id based on port number.
 358  * @port: The one-based port number from one of the two split roothubs.
 359  */
 360 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 361                 u16 port)
 362 {
 363         int slot_id;
 364         int i;
 365         enum usb_device_speed speed;
 366
 367         slot_id = 0;
 368         for (i = 0; i < MAX_HC_SLOTS; i++) {
 369                 if (!xhci->devs[i] || !xhci->devs[i]->udev)
 370                         continue;
 371                 speed = xhci->devs[i]->udev->speed;
 372                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 373                                 && xhci->devs[i]->fake_port == port) {
 374                         slot_id = i;
 375                         break;
 376                 }
 377         }
 378
 379         return slot_id;
 380 }
 381
 382 /*
 383  * Stop device
 384  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 385  * to complete.
 386  * suspend will set to 1, if suspend bit need to set in command.
 387  */
 388 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 389 {
 390         struct xhci_virt_device *virt_dev;
 391         struct xhci_command *cmd;
 392         unsigned long flags;
 393         int ret;
 394         int i;
 395
 396         ret = 0;
 397         virt_dev = xhci->devs[slot_id];
 398         if (!virt_dev)
 399                 return -ENODEV;
 400
 401         trace_xhci_stop_device(virt_dev);
 402
 403         cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
 404         if (!cmd)
 405                 return -ENOMEM;
 406
 407         spin_lock_irqsave(&xhci->lock, flags);
 408         for (i = LAST_EP_INDEX; i > 0; i--) {
 409                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 410                         struct xhci_ep_ctx *ep_ctx;
 411                         struct xhci_command *command;
 412
 413                         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
 414
 415                         /* Check ep is running, required by AMD SNPS 3.1 xHC */
 416                         if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
 417                                 continue;
 418
 419                         command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
 420                         if (!command) {
 421                                 spin_unlock_irqrestore(&xhci->lock, flags);
 422                                 ret = -ENOMEM;
 423                                 goto cmd_cleanup;
 424                         }
 425
 426                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 427                                                        i, suspend);
 428                         if (ret) {
 429                                 spin_unlock_irqrestore(&xhci->lock, flags);
 430                                 xhci_free_command(xhci, command);
 431                                 goto cmd_cleanup;
 432                         }
 433                 }
 434         }
 435         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 436         if (ret) {
 437                 spin_unlock_irqrestore(&xhci->lock, flags);
 438                 goto cmd_cleanup;
 439         }
 440
 441         xhci_ring_cmd_db(xhci);
 442         spin_unlock_irqrestore(&xhci->lock, flags);
 443
 444         /* Wait for last stop endpoint command to finish */
 445         wait_for_completion(cmd->completion);
 446
 447         if (cmd->status == COMP_COMMAND_ABORTED ||
 448             cmd->status == COMP_COMMAND_RING_STOPPED) {
 449                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 450                 ret = -ETIME;
 451         }
 452
 453 cmd_cleanup:
 454         xhci_free_command(xhci, cmd);
 455         return ret;
 456 }
 457
 458 /*
 459  * Ring device, it rings the all doorbells unconditionally.
 460  */
 461 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 462 {
 463         int i, s;
 464         struct xhci_virt_ep *ep;
 465
 466         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 467                 ep = &xhci->devs[slot_id]->eps[i];
 468
 469                 if (ep->ep_state & EP_HAS_STREAMS) {
 470                         for (s = 1; s < ep->stream_info->num_streams; s++)
 471                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 472                 } else if (ep->ring && ep->ring->dequeue) {
 473                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 474                 }
 475         }
 476
 477         return;
 478 }
 479
 480 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 481                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 482 {
 483         /* Don't allow the USB core to disable SuperSpeed ports. */
 484         if (hcd->speed >= HCD_USB3) {
 485                 xhci_dbg(xhci, "Ignoring request to disable "
 486                                 "SuperSpeed port.\n");
 487                 return;
 488         }
 489
 490         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 491                 xhci_dbg(xhci,
 492                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 493                 return;
 494         }
 495
 496         /* Write 1 to disable the port */
 497         writel(port_status | PORT_PE, addr);
 498         port_status = readl(addr);
 499         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 500                         wIndex, port_status);
 501 }
 502
 503 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 504                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 505 {
 506         char *port_change_bit;
 507         u32 status;
 508
 509         switch (wValue) {
 510         case USB_PORT_FEAT_C_RESET:
 511                 status = PORT_RC;
 512                 port_change_bit = "reset";
 513                 break;
 514         case USB_PORT_FEAT_C_BH_PORT_RESET:
 515                 status = PORT_WRC;
 516                 port_change_bit = "warm(BH) reset";
 517                 break;
 518         case USB_PORT_FEAT_C_CONNECTION:
 519                 status = PORT_CSC;
 520                 port_change_bit = "connect";
 521                 break;
 522         case USB_PORT_FEAT_C_OVER_CURRENT:
 523                 status = PORT_OCC;
 524                 port_change_bit = "over-current";
 525                 break;
 526         case USB_PORT_FEAT_C_ENABLE:
 527                 status = PORT_PEC;
 528                 port_change_bit = "enable/disable";
 529                 break;
 530         case USB_PORT_FEAT_C_SUSPEND:
 531                 status = PORT_PLC;
 532                 port_change_bit = "suspend/resume";
 533                 break;
 534         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 535                 status = PORT_PLC;
 536                 port_change_bit = "link state";
 537                 break;
 538         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 539                 status = PORT_CEC;
 540                 port_change_bit = "config error";
 541                 break;
 542         default:
 543                 /* Should never happen */
 544                 return;
 545         }
 546         /* Change bits are all write 1 to clear */
 547         writel(port_status | status, addr);
 548         port_status = readl(addr);
 549         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 550                         port_change_bit, wIndex, port_status);
 551 }
 552
 553 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
 554 {
 555         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 556
 557         if (hcd->speed >= HCD_USB3)
 558                 return &xhci->usb3_rhub;
 559         return &xhci->usb2_rhub;
 560 }
 561
 562 /*
 563  * xhci_set_port_power() must be called with xhci->lock held.
 564  * It will release and re-aquire the lock while calling ACPI
 565  * method.
 566  */
 567 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
 568                                 u16 index, bool on, unsigned long *flags)
 569 {
 570         struct xhci_hub *rhub;
 571         struct xhci_port *port;
 572         u32 temp;
 573
 574         rhub = xhci_get_rhub(hcd);
 575         port = rhub->ports[index];
 576         temp = readl(port->addr);
 577         temp = xhci_port_state_to_neutral(temp);
 578         if (on) {
 579                 /* Power on */
 580                 writel(temp | PORT_POWER, port->addr);
 581                 temp = readl(port->addr);
 582                 xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n",
 583                                                 index, temp);
 584         } else {
 585                 /* Power off */
 586                 writel(temp & ~PORT_POWER, port->addr);
 587         }
 588
 589         spin_unlock_irqrestore(&xhci->lock, *flags);
 590         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 591                                         index);
 592         if (temp)
 593                 usb_acpi_set_power_state(hcd->self.root_hub,
 594                         index, on);
 595         spin_lock_irqsave(&xhci->lock, *flags);
 596 }
 597
 598 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
 599         u16 test_mode, u16 wIndex)
 600 {
 601         u32 temp;
 602         struct xhci_port *port;
 603
 604         /* xhci only supports test mode for usb2 ports */
 605         port = xhci->usb2_rhub.ports[wIndex];
 606         temp = readl(port->addr + PORTPMSC);
 607         temp |= test_mode << PORT_TEST_MODE_SHIFT;
 608         writel(temp, port->addr + PORTPMSC);
 609         xhci->test_mode = test_mode;
 610         if (test_mode == TEST_FORCE_EN)
 611                 xhci_start(xhci);
 612 }
 613
 614 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
 615                                 u16 test_mode, u16 wIndex, unsigned long *flags)
 616 {
 617         int i, retval;
 618
 619         /* Disable all Device Slots */
 620         xhci_dbg(xhci, "Disable all slots\n");
 621         spin_unlock_irqrestore(&xhci->lock, *flags);
 622         for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 623                 if (!xhci->devs[i])
 624                         continue;
 625
 626                 retval = xhci_disable_slot(xhci, i);
 627                 if (retval)
 628                         xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
 629                                  i, retval);
 630         }
 631         spin_lock_irqsave(&xhci->lock, *flags);
 632         /* Put all ports to the Disable state by clear PP */
 633         xhci_dbg(xhci, "Disable all port (PP = 0)\n");
 634         /* Power off USB3 ports*/
 635         for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
 636                 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
 637         /* Power off USB2 ports*/
 638         for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
 639                 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
 640         /* Stop the controller */
 641         xhci_dbg(xhci, "Stop controller\n");
 642         retval = xhci_halt(xhci);
 643         if (retval)
 644                 return retval;
 645         /* Disable runtime PM for test mode */
 646         pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
 647         /* Set PORTPMSC.PTC field to enter selected test mode */
 648         /* Port is selected by wIndex. port_id = wIndex + 1 */
 649         xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
 650                                         test_mode, wIndex + 1);
 651         xhci_port_set_test_mode(xhci, test_mode, wIndex);
 652         return retval;
 653 }
 654
 655 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
 656 {
 657         int retval;
 658
 659         if (!xhci->test_mode) {
 660                 xhci_err(xhci, "Not in test mode, do nothing.\n");
 661                 return 0;
 662         }
 663         if (xhci->test_mode == TEST_FORCE_EN &&
 664                 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
 665                 retval = xhci_halt(xhci);
 666                 if (retval)
 667                         return retval;
 668         }
 669         pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
 670         xhci->test_mode = 0;
 671         return xhci_reset(xhci);
 672 }
 673
 674 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
 675                          u32 link_state)
 676 {
 677         u32 temp;
 678
 679         temp = readl(port->addr);
 680         temp = xhci_port_state_to_neutral(temp);
 681         temp &= ~PORT_PLS_MASK;
 682         temp |= PORT_LINK_STROBE | link_state;
 683         writel(temp, port->addr);
 684 }
 685
 686 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 687                                       struct xhci_port *port, u16 wake_mask)
 688 {
 689         u32 temp;
 690
 691         temp = readl(port->addr);
 692         temp = xhci_port_state_to_neutral(temp);
 693
 694         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 695                 temp |= PORT_WKCONN_E;
 696         else
 697                 temp &= ~PORT_WKCONN_E;
 698
 699         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 700                 temp |= PORT_WKDISC_E;
 701         else
 702                 temp &= ~PORT_WKDISC_E;
 703
 704         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 705                 temp |= PORT_WKOC_E;
 706         else
 707                 temp &= ~PORT_WKOC_E;
 708
 709         writel(temp, port->addr);
 710 }
 711
 712 /* Test and clear port RWC bit */
 713 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
 714                              u32 port_bit)
 715 {
 716         u32 temp;
 717
 718         temp = readl(port->addr);
 719         if (temp & port_bit) {
 720                 temp = xhci_port_state_to_neutral(temp);
 721                 temp |= port_bit;
 722                 writel(temp, port->addr);
 723         }
 724 }
 725
 726 /* Updates Link Status for USB 2.1 port */
 727 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 728 {
 729         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 730                 *status |= USB_PORT_STAT_L1;
 731 }
 732
 733 /* Updates Link Status for super Speed port */
 734 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 735                 u32 *status, u32 status_reg)
 736 {
 737         u32 pls = status_reg & PORT_PLS_MASK;
 738
 739         /* resume state is a xHCI internal state.
 740          * Do not report it to usb core, instead, pretend to be U3,
 741          * thus usb core knows it's not ready for transfer
 742          */
 743         if (pls == XDEV_RESUME) {
 744                 *status |= USB_SS_PORT_LS_U3;
 745                 return;
 746         }
 747
 748         /* When the CAS bit is set then warm reset
 749          * should be performed on port
 750          */
 751         if (status_reg & PORT_CAS) {
 752                 /* The CAS bit can be set while the port is
 753                  * in any link state.
 754                  * Only roothubs have CAS bit, so we
 755                  * pretend to be in compliance mode
 756                  * unless we're already in compliance
 757                  * or the inactive state.
 758                  */
 759                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 760                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 761                         pls = USB_SS_PORT_LS_COMP_MOD;
 762                 }
 763                 /* Return also connection bit -
 764                  * hub state machine resets port
 765                  * when this bit is set.
 766                  */
 767                 pls |= USB_PORT_STAT_CONNECTION;
 768         } else {
 769                 /*
 770                  * If CAS bit isn't set but the Port is already at
 771                  * Compliance Mode, fake a connection so the USB core
 772                  * notices the Compliance state and resets the port.
 773                  * This resolves an issue generated by the SN65LVPE502CP
 774                  * in which sometimes the port enters compliance mode
 775                  * caused by a delay on the host-device negotiation.
 776                  */
 777                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 778                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 779                         pls |= USB_PORT_STAT_CONNECTION;
 780         }
 781
 782         /* update status field */
 783         *status |= pls;
 784 }
 785
 786 /*
 787  * Function for Compliance Mode Quirk.
 788  *
 789  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 790  * the compliance mode timer is deleted. A port won't enter
 791  * compliance mode if it has previously entered U0.
 792  */
 793 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 794                                     u16 wIndex)
 795 {
 796         u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
 797         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 798
 799         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 800                 return;
 801
 802         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 803                 xhci->port_status_u0 |= 1 << wIndex;
 804                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 805                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 806                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 807                                 "All USB3 ports have entered U0 already!");
 808                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 809                                 "Compliance Mode Recovery Timer Deleted.");
 810                 }
 811         }
 812 }
 813
 814 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 815 {
 816         u32 ext_stat = 0;
 817         int speed_id;
 818
 819         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 820         speed_id = DEV_PORT_SPEED(raw_port_status);
 821         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 822         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 823
 824         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 825         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 826
 827         return ext_stat;
 828 }
 829
 830 /*
 831  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 832  * 3.0 hubs use.
 833  *
 834  * Possible side effects:
 835  *  - Mark a port as being done with device resume,
 836  *    and ring the endpoint doorbells.
 837  *  - Stop the Synopsys redriver Compliance Mode polling.
 838  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
 839  */
 840 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 841                 struct xhci_bus_state *bus_state,
 842         u16 wIndex, u32 raw_port_status,
 843                 unsigned long *flags)
 844         __releases(&xhci->lock)
 845         __acquires(&xhci->lock)
 846 {
 847         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 848         u32 status = 0;
 849         int slot_id;
 850         struct xhci_hub *rhub;
 851         struct xhci_port *port;
 852
 853         rhub = xhci_get_rhub(hcd);
 854         port = rhub->ports[wIndex];
 855
 856         /* wPortChange bits */
 857         if (raw_port_status & PORT_CSC)
 858                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 859         if (raw_port_status & PORT_PEC)
 860                 status |= USB_PORT_STAT_C_ENABLE << 16;
 861         if ((raw_port_status & PORT_OCC))
 862                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 863         if ((raw_port_status & PORT_RC))
 864                 status |= USB_PORT_STAT_C_RESET << 16;
 865         /* USB3.0 only */
 866         if (hcd->speed >= HCD_USB3) {
 867                 /* Port link change with port in resume state should not be
 868                  * reported to usbcore, as this is an internal state to be
 869                  * handled by xhci driver. Reporting PLC to usbcore may
 870                  * cause usbcore clearing PLC first and port change event
 871                  * irq won't be generated.
 872                  */
 873                 if ((raw_port_status & PORT_PLC) &&
 874                         (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
 875                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 876                 if ((raw_port_status & PORT_WRC))
 877                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 878                 if ((raw_port_status & PORT_CEC))
 879                         status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 880
 881                 /* USB3 remote wake resume signaling completed */
 882                 if (bus_state->port_remote_wakeup & (1 << wIndex) &&
 883                     (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME &&
 884                     (raw_port_status & PORT_PLS_MASK) != XDEV_RECOVERY) {
 885                         bus_state->port_remote_wakeup &= ~(1 << wIndex);
 886                         usb_hcd_end_port_resume(&hcd->self, wIndex);
 887                 }
 888         }
 889
 890         if (hcd->speed < HCD_USB3) {
 891                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 892                                 && (raw_port_status & PORT_POWER))
 893                         status |= USB_PORT_STAT_SUSPEND;
 894         }
 895         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 896                 !DEV_SUPERSPEED_ANY(raw_port_status) && hcd->speed < HCD_USB3) {
 897                 if ((raw_port_status & PORT_RESET) ||
 898                                 !(raw_port_status & PORT_PE))
 899                         return 0xffffffff;
 900                 /* did port event handler already start resume timing? */
 901                 if (!bus_state->resume_done[wIndex]) {
 902                         /* If not, maybe we are in a host initated resume? */
 903                         if (test_bit(wIndex, &bus_state->resuming_ports)) {
 904                                 /* Host initated resume doesn't time the resume
 905                                  * signalling using resume_done[].
 906                                  * It manually sets RESUME state, sleeps 20ms
 907                                  * and sets U0 state. This should probably be
 908                                  * changed, but not right now.
 909                                  */
 910                         } else {
 911                                 /* port resume was discovered now and here,
 912                                  * start resume timing
 913                                  */
 914                                 unsigned long timeout = jiffies +
 915                                         msecs_to_jiffies(USB_RESUME_TIMEOUT);
 916
 917                                 set_bit(wIndex, &bus_state->resuming_ports);
 918                                 bus_state->resume_done[wIndex] = timeout;
 919                                 mod_timer(&hcd->rh_timer, timeout);
 920                                 usb_hcd_start_port_resume(&hcd->self, wIndex);
 921                         }
 922                 /* Has resume been signalled for USB_RESUME_TIME yet? */
 923                 } else if (time_after_eq(jiffies,
 924                                          bus_state->resume_done[wIndex])) {
 925                         int time_left;
 926
 927                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 928                                         wIndex + 1);
 929                         bus_state->resume_done[wIndex] = 0;
 930                         clear_bit(wIndex, &bus_state->resuming_ports);
 931
 932                         set_bit(wIndex, &bus_state->rexit_ports);
 933
 934                         xhci_test_and_clear_bit(xhci, port, PORT_PLC);
 935                         xhci_set_link_state(xhci, port, XDEV_U0);
 936
 937                         spin_unlock_irqrestore(&xhci->lock, *flags);
 938                         time_left = wait_for_completion_timeout(
 939                                         &bus_state->rexit_done[wIndex],
 940                                         msecs_to_jiffies(
 941                                                 XHCI_MAX_REXIT_TIMEOUT_MS));
 942                         spin_lock_irqsave(&xhci->lock, *flags);
 943
 944                         if (time_left) {
 945                                 slot_id = xhci_find_slot_id_by_port(hcd,
 946                                                 xhci, wIndex + 1);
 947                                 if (!slot_id) {
 948                                         xhci_dbg(xhci, "slot_id is zero\n");
 949                                         return 0xffffffff;
 950                                 }
 951                                 xhci_ring_device(xhci, slot_id);
 952                         } else {
 953                                 int port_status = readl(port->addr);
 954                                 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
 955                                                 XHCI_MAX_REXIT_TIMEOUT_MS,
 956                                                 port_status);
 957                                 status |= USB_PORT_STAT_SUSPEND;
 958                                 clear_bit(wIndex, &bus_state->rexit_ports);
 959                         }
 960
 961                         usb_hcd_end_port_resume(&hcd->self, wIndex);
 962                         bus_state->port_c_suspend |= 1 << wIndex;
 963                         bus_state->suspended_ports &= ~(1 << wIndex);
 964                 } else {
 965                         /*
 966                          * The resume has been signaling for less than
 967                          * USB_RESUME_TIME. Report the port status as SUSPEND,
 968                          * let the usbcore check port status again and clear
 969                          * resume signaling later.
 970                          */
 971                         status |= USB_PORT_STAT_SUSPEND;
 972                 }
 973         }
 974         /*
 975          * Clear stale usb2 resume signalling variables in case port changed
 976          * state during resume signalling. For example on error
 977          */
 978         if ((bus_state->resume_done[wIndex] ||
 979              test_bit(wIndex, &bus_state->resuming_ports)) &&
 980             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
 981             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
 982                 bus_state->resume_done[wIndex] = 0;
 983                 clear_bit(wIndex, &bus_state->resuming_ports);
 984                 usb_hcd_end_port_resume(&hcd->self, wIndex);
 985         }
 986
 987
 988         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
 989             (raw_port_status & PORT_POWER)) {
 990                 if (bus_state->suspended_ports & (1 << wIndex)) {
 991                         bus_state->suspended_ports &= ~(1 << wIndex);
 992                         if (hcd->speed < HCD_USB3)
 993                                 bus_state->port_c_suspend |= 1 << wIndex;
 994                 }
 995                 bus_state->resume_done[wIndex] = 0;
 996                 clear_bit(wIndex, &bus_state->resuming_ports);
 997         }
 998         if (raw_port_status & PORT_CONNECT) {
 999                 status |= USB_PORT_STAT_CONNECTION;
1000                 status |= xhci_port_speed(raw_port_status);
1001         }
1002         if (raw_port_status & PORT_PE)
1003                 status |= USB_PORT_STAT_ENABLE;
1004         if (raw_port_status & PORT_OC)
1005                 status |= USB_PORT_STAT_OVERCURRENT;
1006         if (raw_port_status & PORT_RESET)
1007                 status |= USB_PORT_STAT_RESET;
1008         if (raw_port_status & PORT_POWER) {
1009                 if (hcd->speed >= HCD_USB3)
1010                         status |= USB_SS_PORT_STAT_POWER;
1011                 else
1012                         status |= USB_PORT_STAT_POWER;
1013         }
1014         /* Update Port Link State */
1015         if (hcd->speed >= HCD_USB3) {
1016                 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
1017                 /*
1018                  * Verify if all USB3 Ports Have entered U0 already.
1019                  * Delete Compliance Mode Timer if so.
1020                  */
1021                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
1022         } else {
1023                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
1024         }
1025         if (bus_state->port_c_suspend & (1 << wIndex))
1026                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1027
1028         return status;
1029 }
1030
1031 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1032                 u16 wIndex, char *buf, u16 wLength)
1033 {
1034         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1035         int max_ports;
1036         unsigned long flags;
1037         u32 temp, status;
1038         int retval = 0;
1039         int slot_id;
1040         struct xhci_bus_state *bus_state;
1041         u16 link_state = 0;
1042         u16 wake_mask = 0;
1043         u16 timeout = 0;
1044         u16 test_mode = 0;
1045         struct xhci_hub *rhub;
1046         struct xhci_port **ports;
1047
1048         rhub = xhci_get_rhub(hcd);
1049         ports = rhub->ports;
1050         max_ports = rhub->num_ports;
1051         bus_state = &xhci->bus_state[hcd_index(hcd)];
1052
1053         spin_lock_irqsave(&xhci->lock, flags);
1054         switch (typeReq) {
1055         case GetHubStatus:
1056                 /* No power source, over-current reported per port */
1057                 memset(buf, 0, 4);
1058                 break;
1059         case GetHubDescriptor:
1060                 /* Check to make sure userspace is asking for the USB 3.0 hub
1061                  * descriptor for the USB 3.0 roothub.  If not, we stall the
1062                  * endpoint, like external hubs do.
1063                  */
1064                 if (hcd->speed >= HCD_USB3 &&
1065                                 (wLength < USB_DT_SS_HUB_SIZE ||
1066                                  wValue != (USB_DT_SS_HUB << 8))) {
1067                         xhci_dbg(xhci, "Wrong hub descriptor type for "
1068                                         "USB 3.0 roothub.\n");
1069                         goto error;
1070                 }
1071                 xhci_hub_descriptor(hcd, xhci,
1072                                 (struct usb_hub_descriptor *) buf);
1073                 break;
1074         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1075                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1076                         goto error;
1077
1078                 if (hcd->speed < HCD_USB3)
1079                         goto error;
1080
1081                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1082                 spin_unlock_irqrestore(&xhci->lock, flags);
1083                 return retval;
1084         case GetPortStatus:
1085                 if (!wIndex || wIndex > max_ports)
1086                         goto error;
1087                 wIndex--;
1088                 temp = readl(ports[wIndex]->addr);
1089                 if (temp == ~(u32)0) {
1090                         xhci_hc_died(xhci);
1091                         retval = -ENODEV;
1092                         break;
1093                 }
1094                 trace_xhci_get_port_status(wIndex, temp);
1095                 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1096                                               &flags);
1097                 if (status == 0xffffffff)
1098                         goto error;
1099
1100                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
1101                                 wIndex, temp);
1102                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
1103
1104                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1105                 /* if USB 3.1 extended port status return additional 4 bytes */
1106                 if (wValue == 0x02) {
1107                         u32 port_li;
1108
1109                         if (hcd->speed < HCD_USB31 || wLength != 8) {
1110                                 xhci_err(xhci, "get ext port status invalid parameter\n");
1111                                 retval = -EINVAL;
1112                                 break;
1113                         }
1114                         port_li = readl(ports[wIndex]->addr + PORTLI);
1115                         status = xhci_get_ext_port_status(temp, port_li);
1116                         put_unaligned_le32(status, &buf[4]);
1117                 }
1118                 break;
1119         case SetPortFeature:
1120                 if (wValue == USB_PORT_FEAT_LINK_STATE)
1121                         link_state = (wIndex & 0xff00) >> 3;
1122                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1123                         wake_mask = wIndex & 0xff00;
1124                 if (wValue == USB_PORT_FEAT_TEST)
1125                         test_mode = (wIndex & 0xff00) >> 8;
1126                 /* The MSB of wIndex is the U1/U2 timeout */
1127                 timeout = (wIndex & 0xff00) >> 8;
1128                 wIndex &= 0xff;
1129                 if (!wIndex || wIndex > max_ports)
1130                         goto error;
1131                 wIndex--;
1132                 temp = readl(ports[wIndex]->addr);
1133                 if (temp == ~(u32)0) {
1134                         xhci_hc_died(xhci);
1135                         retval = -ENODEV;
1136                         break;
1137                 }
1138                 temp = xhci_port_state_to_neutral(temp);
1139                 /* FIXME: What new port features do we need to support? */
1140                 switch (wValue) {
1141                 case USB_PORT_FEAT_SUSPEND:
1142                         temp = readl(ports[wIndex]->addr);
1143                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1144                                 /* Resume the port to U0 first */
1145                                 xhci_set_link_state(xhci, ports[wIndex],
1146                                                         XDEV_U0);
1147                                 spin_unlock_irqrestore(&xhci->lock, flags);
1148                                 msleep(10);
1149                                 spin_lock_irqsave(&xhci->lock, flags);
1150                         }
1151                         /* In spec software should not attempt to suspend
1152                          * a port unless the port reports that it is in the
1153                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1154                          */
1155                         temp = readl(ports[wIndex]->addr);
1156                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1157                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1158                                 xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n");
1159                                 goto error;
1160                         }
1161
1162                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1163                                         wIndex + 1);
1164                         if (!slot_id) {
1165                                 xhci_warn(xhci, "slot_id is zero\n");
1166                                 goto error;
1167                         }
1168                         /* unlock to execute stop endpoint commands */
1169                         spin_unlock_irqrestore(&xhci->lock, flags);
1170                         xhci_stop_device(xhci, slot_id, 1);
1171                         spin_lock_irqsave(&xhci->lock, flags);
1172
1173                         xhci_set_link_state(xhci, ports[wIndex], XDEV_U3);
1174
1175                         spin_unlock_irqrestore(&xhci->lock, flags);
1176                         msleep(10); /* wait device to enter */
1177                         spin_lock_irqsave(&xhci->lock, flags);
1178
1179                         temp = readl(ports[wIndex]->addr);
1180                         bus_state->suspended_ports |= 1 << wIndex;
1181                         break;
1182                 case USB_PORT_FEAT_LINK_STATE:
1183                         temp = readl(ports[wIndex]->addr);
1184                         /* Disable port */
1185                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1186                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1187                                 temp = xhci_port_state_to_neutral(temp);
1188                                 /*
1189                                  * Clear all change bits, so that we get a new
1190                                  * connection event.
1191                                  */
1192                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1193                                         PORT_OCC | PORT_RC | PORT_PLC |
1194                                         PORT_CEC;
1195                                 writel(temp | PORT_PE, ports[wIndex]->addr);
1196                                 temp = readl(ports[wIndex]->addr);
1197                                 break;
1198                         }
1199
1200                         /* Put link in RxDetect (enable port) */
1201                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1202                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1203                                 xhci_set_link_state(xhci, ports[wIndex],
1204                                                         link_state);
1205                                 temp = readl(ports[wIndex]->addr);
1206                                 break;
1207                         }
1208
1209                         /*
1210                          * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1211                          * root hub port's transition to compliance mode upon
1212                          * detecting LFPS timeout may be controlled by an
1213                          * Compliance Transition Enabled (CTE) flag (not
1214                          * software visible). This flag is set by writing 0xA
1215                          * to PORTSC PLS field which will allow transition to
1216                          * compliance mode the next time LFPS timeout is
1217                          * encountered. A warm reset will clear it.
1218                          *
1219                          * The CTE flag is only supported if the HCCPARAMS2 CTC
1220                          * flag is set, otherwise, the compliance substate is
1221                          * automatically entered as on 1.0 and prior.
1222                          */
1223                         if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1224                                 if (!HCC2_CTC(xhci->hcc_params2)) {
1225                                         xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1226                                         break;
1227                                 }
1228
1229                                 if ((temp & PORT_CONNECT)) {
1230                                         xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1231                                         goto error;
1232                                 }
1233
1234                                 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1235                                                 wIndex);
1236                                 xhci_set_link_state(xhci, ports[wIndex],
1237                                                 link_state);
1238
1239                                 temp = readl(ports[wIndex]->addr);
1240                                 break;
1241                         }
1242                         /* Port must be enabled */
1243                         if (!(temp & PORT_PE)) {
1244                                 retval = -ENODEV;
1245                                 break;
1246                         }
1247                         /* Can't set port link state above '3' (U3) */
1248                         if (link_state > USB_SS_PORT_LS_U3) {
1249                                 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1250                                          wIndex, link_state);
1251                                 goto error;
1252                         }
1253                         if (link_state == USB_SS_PORT_LS_U3) {
1254                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1255                                                 wIndex + 1);
1256                                 if (slot_id) {
1257                                         /* unlock to execute stop endpoint
1258                                          * commands */
1259                                         spin_unlock_irqrestore(&xhci->lock,
1260                                                                 flags);
1261                                         xhci_stop_device(xhci, slot_id, 1);
1262                                         spin_lock_irqsave(&xhci->lock, flags);
1263                                 }
1264                         }
1265
1266                         xhci_set_link_state(xhci, ports[wIndex], link_state);
1267
1268                         spin_unlock_irqrestore(&xhci->lock, flags);
1269                         if (link_state == USB_SS_PORT_LS_U3) {
1270                                 int retries = 16;
1271
1272                                 while (retries--) {
1273                                         usleep_range(4000, 8000);
1274                                         temp = readl(ports[wIndex]->addr);
1275                                         if ((temp & PORT_PLS_MASK) == XDEV_U3)
1276                                                 break;
1277                                 }
1278                         }
1279                         spin_lock_irqsave(&xhci->lock, flags);
1280
1281                         temp = readl(ports[wIndex]->addr);
1282                         if (link_state == USB_SS_PORT_LS_U3)
1283                                 bus_state->suspended_ports |= 1 << wIndex;
1284                         break;
1285                 case USB_PORT_FEAT_POWER:
1286                         /*
1287                          * Turn on ports, even if there isn't per-port switching.
1288                          * HC will report connect events even before this is set.
1289                          * However, hub_wq will ignore the roothub events until
1290                          * the roothub is registered.
1291                          */
1292                         xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1293                         break;
1294                 case USB_PORT_FEAT_RESET:
1295                         temp = (temp | PORT_RESET);
1296                         writel(temp, ports[wIndex]->addr);
1297
1298                         temp = readl(ports[wIndex]->addr);
1299                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1300                         break;
1301                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1302                         xhci_set_remote_wake_mask(xhci, ports[wIndex],
1303                                                   wake_mask);
1304                         temp = readl(ports[wIndex]->addr);
1305                         xhci_dbg(xhci, "set port remote wake mask, "
1306                                         "actual port %d status  = 0x%x\n",
1307                                         wIndex, temp);
1308                         break;
1309                 case USB_PORT_FEAT_BH_PORT_RESET:
1310                         temp |= PORT_WR;
1311                         writel(temp, ports[wIndex]->addr);
1312                         temp = readl(ports[wIndex]->addr);
1313                         break;
1314                 case USB_PORT_FEAT_U1_TIMEOUT:
1315                         if (hcd->speed < HCD_USB3)
1316                                 goto error;
1317                         temp = readl(ports[wIndex]->addr + PORTPMSC);
1318                         temp &= ~PORT_U1_TIMEOUT_MASK;
1319                         temp |= PORT_U1_TIMEOUT(timeout);
1320                         writel(temp, ports[wIndex]->addr + PORTPMSC);
1321                         break;
1322                 case USB_PORT_FEAT_U2_TIMEOUT:
1323                         if (hcd->speed < HCD_USB3)
1324                                 goto error;
1325                         temp = readl(ports[wIndex]->addr + PORTPMSC);
1326                         temp &= ~PORT_U2_TIMEOUT_MASK;
1327                         temp |= PORT_U2_TIMEOUT(timeout);
1328                         writel(temp, ports[wIndex]->addr + PORTPMSC);
1329                         break;
1330                 case USB_PORT_FEAT_TEST:
1331                         /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1332                         if (hcd->speed != HCD_USB2)
1333                                 goto error;
1334                         if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1335                                 goto error;
1336                         retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1337                                                       &flags);
1338                         break;
1339                 default:
1340                         goto error;
1341                 }
1342                 /* unblock any posted writes */
1343                 temp = readl(ports[wIndex]->addr);
1344                 break;
1345         case ClearPortFeature:
1346                 if (!wIndex || wIndex > max_ports)
1347                         goto error;
1348                 wIndex--;
1349                 temp = readl(ports[wIndex]->addr);
1350                 if (temp == ~(u32)0) {
1351                         xhci_hc_died(xhci);
1352                         retval = -ENODEV;
1353                         break;
1354                 }
1355                 /* FIXME: What new port features do we need to support? */
1356                 temp = xhci_port_state_to_neutral(temp);
1357                 switch (wValue) {
1358                 case USB_PORT_FEAT_SUSPEND:
1359                         temp = readl(ports[wIndex]->addr);
1360                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1361                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1362                         if (temp & PORT_RESET)
1363                                 goto error;
1364                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1365                                 if ((temp & PORT_PE) == 0)
1366                                         goto error;
1367
1368                                 set_bit(wIndex, &bus_state->resuming_ports);
1369                                 usb_hcd_start_port_resume(&hcd->self, wIndex);
1370                                 xhci_set_link_state(xhci, ports[wIndex],
1371                                                     XDEV_RESUME);
1372                                 spin_unlock_irqrestore(&xhci->lock, flags);
1373                                 msleep(USB_RESUME_TIMEOUT);
1374                                 spin_lock_irqsave(&xhci->lock, flags);
1375                                 xhci_set_link_state(xhci, ports[wIndex],
1376                                                         XDEV_U0);
1377                                 clear_bit(wIndex, &bus_state->resuming_ports);
1378                                 usb_hcd_end_port_resume(&hcd->self, wIndex);
1379                         }
1380                         bus_state->port_c_suspend |= 1 << wIndex;
1381
1382                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1383                                         wIndex + 1);
1384                         if (!slot_id) {
1385                                 xhci_dbg(xhci, "slot_id is zero\n");
1386                                 goto error;
1387                         }
1388                         xhci_ring_device(xhci, slot_id);
1389                         break;
1390                 case USB_PORT_FEAT_C_SUSPEND:
1391                         bus_state->port_c_suspend &= ~(1 << wIndex);
1392                         /* fall through */
1393                 case USB_PORT_FEAT_C_RESET:
1394                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1395                 case USB_PORT_FEAT_C_CONNECTION:
1396                 case USB_PORT_FEAT_C_OVER_CURRENT:
1397                 case USB_PORT_FEAT_C_ENABLE:
1398                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1399                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1400                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1401                                         ports[wIndex]->addr, temp);
1402                         break;
1403                 case USB_PORT_FEAT_ENABLE:
1404                         xhci_disable_port(hcd, xhci, wIndex,
1405                                         ports[wIndex]->addr, temp);
1406                         break;
1407                 case USB_PORT_FEAT_POWER:
1408                         xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1409                         break;
1410                 case USB_PORT_FEAT_TEST:
1411                         retval = xhci_exit_test_mode(xhci);
1412                         break;
1413                 default:
1414                         goto error;
1415                 }
1416                 break;
1417         default:
1418 error:
1419                 /* "stall" on error */
1420                 retval = -EPIPE;
1421         }
1422         spin_unlock_irqrestore(&xhci->lock, flags);
1423         return retval;
1424 }
1425
1426 /*
1427  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1428  * Ports are 0-indexed from the HCD point of view,
1429  * and 1-indexed from the USB core pointer of view.
1430  *
1431  * Note that the status change bits will be cleared as soon as a port status
1432  * change event is generated, so we use the saved status from that event.
1433  */
1434 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1435 {
1436         unsigned long flags;
1437         u32 temp, status;
1438         u32 mask;
1439         int i, retval;
1440         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1441         int max_ports;
1442         struct xhci_bus_state *bus_state;
1443         bool reset_change = false;
1444         struct xhci_hub *rhub;
1445         struct xhci_port **ports;
1446
1447         rhub = xhci_get_rhub(hcd);
1448         ports = rhub->ports;
1449         max_ports = rhub->num_ports;
1450         bus_state = &xhci->bus_state[hcd_index(hcd)];
1451
1452         /* Initial status is no changes */
1453         retval = (max_ports + 8) / 8;
1454         memset(buf, 0, retval);
1455
1456         /*
1457          * Inform the usbcore about resume-in-progress by returning
1458          * a non-zero value even if there are no status changes.
1459          */
1460         status = bus_state->resuming_ports;
1461
1462         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1463
1464         spin_lock_irqsave(&xhci->lock, flags);
1465         /* For each port, did anything change?  If so, set that bit in buf. */
1466         for (i = 0; i < max_ports; i++) {
1467                 temp = readl(ports[i]->addr);
1468                 if (temp == ~(u32)0) {
1469                         xhci_hc_died(xhci);
1470                         retval = -ENODEV;
1471                         break;
1472                 }
1473                 trace_xhci_hub_status_data(i, temp);
1474
1475                 if ((temp & mask) != 0 ||
1476                         (bus_state->port_c_suspend & 1 << i) ||
1477                         (bus_state->resume_done[i] && time_after_eq(
1478                             jiffies, bus_state->resume_done[i]))) {
1479                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1480                         status = 1;
1481                 }
1482                 if ((temp & PORT_RC))
1483                         reset_change = true;
1484                 if (temp & PORT_OC)
1485                         status = 1;
1486         }
1487         if (!status && !reset_change) {
1488                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1489                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1490         }
1491         spin_unlock_irqrestore(&xhci->lock, flags);
1492         return status ? retval : 0;
1493 }
1494
1495 #ifdef CONFIG_PM
1496
1497 int xhci_bus_suspend(struct usb_hcd *hcd)
1498 {
1499         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1500         int max_ports, port_index;
1501         struct xhci_bus_state *bus_state;
1502         unsigned long flags;
1503         struct xhci_hub *rhub;
1504         struct xhci_port **ports;
1505         u32 portsc_buf[USB_MAXCHILDREN];
1506         bool wake_enabled;
1507
1508         rhub = xhci_get_rhub(hcd);
1509         ports = rhub->ports;
1510         max_ports = rhub->num_ports;
1511         bus_state = &xhci->bus_state[hcd_index(hcd)];
1512         wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1513
1514         spin_lock_irqsave(&xhci->lock, flags);
1515
1516         if (wake_enabled) {
1517                 if (bus_state->resuming_ports ||        /* USB2 */
1518                     bus_state->port_remote_wakeup) {    /* USB3 */
1519                         spin_unlock_irqrestore(&xhci->lock, flags);
1520                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1521                         return -EBUSY;
1522                 }
1523         }
1524         /*
1525          * Prepare ports for suspend, but don't write anything before all ports
1526          * are checked and we know bus suspend can proceed
1527          */
1528         bus_state->bus_suspended = 0;
1529         port_index = max_ports;
1530         while (port_index--) {
1531                 u32 t1, t2;
1532                 int retries = 10;
1533 retry:
1534                 t1 = readl(ports[port_index]->addr);
1535                 t2 = xhci_port_state_to_neutral(t1);
1536                 portsc_buf[port_index] = 0;
1537
1538                 /*
1539                  * Give a USB3 port in link training time to finish, but don't
1540                  * prevent suspend as port might be stuck
1541                  */
1542                 if ((hcd->speed >= HCD_USB3) && retries-- &&
1543                     (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1544                         spin_unlock_irqrestore(&xhci->lock, flags);
1545                         msleep(XHCI_PORT_POLLING_LFPS_TIME);
1546                         spin_lock_irqsave(&xhci->lock, flags);
1547                         xhci_dbg(xhci, "port %d polling in bus suspend, waiting\n",
1548                                  port_index);
1549                         goto retry;
1550                 }
1551                 /* bail out if port detected a over-current condition */
1552                 if (t1 & PORT_OC) {
1553                         bus_state->bus_suspended = 0;
1554                         spin_unlock_irqrestore(&xhci->lock, flags);
1555                         xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n");
1556                         return -EBUSY;
1557                 }
1558                 /* suspend ports in U0, or bail out for new connect changes */
1559                 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1560                         if ((t1 & PORT_CSC) && wake_enabled) {
1561                                 bus_state->bus_suspended = 0;
1562                                 spin_unlock_irqrestore(&xhci->lock, flags);
1563                                 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1564                                 return -EBUSY;
1565                         }
1566                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1567                         t2 &= ~PORT_PLS_MASK;
1568                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1569                         set_bit(port_index, &bus_state->bus_suspended);
1570                 }
1571                 /* USB core sets remote wake mask for USB 3.0 hubs,
1572                  * including the USB 3.0 roothub, but only if CONFIG_PM
1573                  * is enabled, so also enable remote wake here.
1574                  */
1575                 if (wake_enabled) {
1576                         if (t1 & PORT_CONNECT) {
1577                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1578                                 t2 &= ~PORT_WKCONN_E;
1579                         } else {
1580                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1581                                 t2 &= ~PORT_WKDISC_E;
1582                         }
1583
1584                         if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1585                             (hcd->speed < HCD_USB3)) {
1586                                 if (usb_amd_pt_check_port(hcd->self.controller,
1587                                                           port_index))
1588                                         t2 &= ~PORT_WAKE_BITS;
1589                         }
1590                 } else
1591                         t2 &= ~PORT_WAKE_BITS;
1592
1593                 t1 = xhci_port_state_to_neutral(t1);
1594                 if (t1 != t2)
1595                         portsc_buf[port_index] = t2;
1596         }
1597
1598         /* write port settings, stopping and suspending ports if needed */
1599         port_index = max_ports;
1600         while (port_index--) {
1601                 if (!portsc_buf[port_index])
1602                         continue;
1603                 if (test_bit(port_index, &bus_state->bus_suspended)) {
1604                         int slot_id;
1605
1606                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1607                                                             port_index + 1);
1608                         if (slot_id) {
1609                                 spin_unlock_irqrestore(&xhci->lock, flags);
1610                                 xhci_stop_device(xhci, slot_id, 1);
1611                                 spin_lock_irqsave(&xhci->lock, flags);
1612                         }
1613                 }
1614                 writel(portsc_buf[port_index], ports[port_index]->addr);
1615         }
1616         hcd->state = HC_STATE_SUSPENDED;
1617         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1618         spin_unlock_irqrestore(&xhci->lock, flags);
1619         return 0;
1620 }
1621
1622 /*
1623  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1624  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1625  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1626  */
1627 static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1628 {
1629         u32 portsc;
1630
1631         portsc = readl(port->addr);
1632
1633         /* if any of these are set we are not stuck */
1634         if (portsc & (PORT_CONNECT | PORT_CAS))
1635                 return false;
1636
1637         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1638             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1639                 return false;
1640
1641         /* clear wakeup/change bits, and do a warm port reset */
1642         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1643         portsc |= PORT_WR;
1644         writel(portsc, port->addr);
1645         /* flush write */
1646         readl(port->addr);
1647         return true;
1648 }
1649
1650 int xhci_bus_resume(struct usb_hcd *hcd)
1651 {
1652         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1653         struct xhci_bus_state *bus_state;
1654         unsigned long flags;
1655         int max_ports, port_index;
1656         int slot_id;
1657         int sret;
1658         u32 next_state;
1659         u32 temp, portsc;
1660         struct xhci_hub *rhub;
1661         struct xhci_port **ports;
1662
1663         rhub = xhci_get_rhub(hcd);
1664         ports = rhub->ports;
1665         max_ports = rhub->num_ports;
1666         bus_state = &xhci->bus_state[hcd_index(hcd)];
1667
1668         if (time_before(jiffies, bus_state->next_statechange))
1669                 msleep(5);
1670
1671         spin_lock_irqsave(&xhci->lock, flags);
1672         if (!HCD_HW_ACCESSIBLE(hcd)) {
1673                 spin_unlock_irqrestore(&xhci->lock, flags);
1674                 return -ESHUTDOWN;
1675         }
1676
1677         /* delay the irqs */
1678         temp = readl(&xhci->op_regs->command);
1679         temp &= ~CMD_EIE;
1680         writel(temp, &xhci->op_regs->command);
1681
1682         /* bus specific resume for ports we suspended at bus_suspend */
1683         if (hcd->speed >= HCD_USB3)
1684                 next_state = XDEV_U0;
1685         else
1686                 next_state = XDEV_RESUME;
1687
1688         port_index = max_ports;
1689         while (port_index--) {
1690                 portsc = readl(ports[port_index]->addr);
1691
1692                 /* warm reset CAS limited ports stuck in polling/compliance */
1693                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1694                     (hcd->speed >= HCD_USB3) &&
1695                     xhci_port_missing_cas_quirk(ports[port_index])) {
1696                         xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1697                         clear_bit(port_index, &bus_state->bus_suspended);
1698                         continue;
1699                 }
1700                 /* resume if we suspended the link, and it is still suspended */
1701                 if (test_bit(port_index, &bus_state->bus_suspended))
1702                         switch (portsc & PORT_PLS_MASK) {
1703                         case XDEV_U3:
1704                                 portsc = xhci_port_state_to_neutral(portsc);
1705                                 portsc &= ~PORT_PLS_MASK;
1706                                 portsc |= PORT_LINK_STROBE | next_state;
1707                                 break;
1708                         case XDEV_RESUME:
1709                                 /* resume already initiated */
1710                                 break;
1711                         default:
1712                                 /* not in a resumeable state, ignore it */
1713                                 clear_bit(port_index,
1714                                           &bus_state->bus_suspended);
1715                                 break;
1716                         }
1717                 /* disable wake for all ports, write new link state if needed */
1718                 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1719                 writel(portsc, ports[port_index]->addr);
1720         }
1721
1722         /* USB2 specific resume signaling delay and U0 link state transition */
1723         if (hcd->speed < HCD_USB3) {
1724                 if (bus_state->bus_suspended) {
1725                         spin_unlock_irqrestore(&xhci->lock, flags);
1726                         msleep(USB_RESUME_TIMEOUT);
1727                         spin_lock_irqsave(&xhci->lock, flags);
1728                 }
1729                 for_each_set_bit(port_index, &bus_state->bus_suspended,
1730                                  BITS_PER_LONG) {
1731                         /* Clear PLC to poll it later for U0 transition */
1732                         xhci_test_and_clear_bit(xhci, ports[port_index],
1733                                                 PORT_PLC);
1734                         xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1735                 }
1736         }
1737
1738         /* poll for U0 link state complete, both USB2 and USB3 */
1739         for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1740                 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1741                                       PORT_PLC, 10 * 1000);
1742                 if (sret) {
1743                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1744                                   port_index);
1745                         continue;
1746                 }
1747                 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1748                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1749                 if (slot_id)
1750                         xhci_ring_device(xhci, slot_id);
1751         }
1752         (void) readl(&xhci->op_regs->command);
1753
1754         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1755         /* re-enable irqs */
1756         temp = readl(&xhci->op_regs->command);
1757         temp |= CMD_EIE;
1758         writel(temp, &xhci->op_regs->command);
1759         temp = readl(&xhci->op_regs->command);
1760
1761         spin_unlock_irqrestore(&xhci->lock, flags);
1762         return 0;
1763 }
1764
1765 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1766 {
1767         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1768         struct xhci_bus_state *bus_state;
1769
1770         bus_state = &xhci->bus_state[hcd_index(hcd)];
1771
1772         /* USB3 port wakeups are reported via usb_wakeup_notification() */
1773         return bus_state->resuming_ports;       /* USB2 ports only */
1774 }
1775
1776 #endif  /* CONFIG_PM */