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drm/amdkfd: Add memory exception handling
[linux/fpc-iii.git] / drivers / gpu / drm / drm_edid.c
blobe426223482fb6362198be54c54ccd8b9dbf4bb3b
1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <drm/drmP.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_displayid.h>
38
39 #define version_greater(edid, maj, min) \
40 (((edid)->version > (maj)) || \
41 ((edid)->version == (maj) && (edid)->revision > (min)))
42
43 #define EDID_EST_TIMINGS 16
44 #define EDID_STD_TIMINGS 8
45 #define EDID_DETAILED_TIMINGS 4
46
47 /*
48 * EDID blocks out in the wild have a variety of bugs, try to collect
49 * them here (note that userspace may work around broken monitors first,
50 * but fixes should make their way here so that the kernel "just works"
51 * on as many displays as possible).
52 */
53
54 /* First detailed mode wrong, use largest 60Hz mode */
55 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
56 /* Reported 135MHz pixel clock is too high, needs adjustment */
57 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
58 /* Prefer the largest mode at 75 Hz */
59 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
60 /* Detail timing is in cm not mm */
61 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
62 /* Detailed timing descriptors have bogus size values, so just take the
63 * maximum size and use that.
64 */
65 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
66 /* Monitor forgot to set the first detailed is preferred bit. */
67 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
68 /* use +hsync +vsync for detailed mode */
69 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
70 /* Force reduced-blanking timings for detailed modes */
71 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
72 /* Force 8bpc */
73 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
74 /* Force 12bpc */
75 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
76
77 struct detailed_mode_closure {
78 struct drm_connector *connector;
79 struct edid *edid;
80 bool preferred;
81 u32 quirks;
82 int modes;
83 };
84
85 #define LEVEL_DMT 0
86 #define LEVEL_GTF 1
87 #define LEVEL_GTF2 2
88 #define LEVEL_CVT 3
89
90 static struct edid_quirk {
91 char vendor[4];
92 int product_id;
93 u32 quirks;
94 } edid_quirk_list[] = {
95 /* Acer AL1706 */
96 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
97 /* Acer F51 */
98 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
99 /* Unknown Acer */
100 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
101
102 /* Belinea 10 15 55 */
103 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
104 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
105
106 /* Envision Peripherals, Inc. EN-7100e */
107 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
108 /* Envision EN2028 */
109 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
110
111 /* Funai Electronics PM36B */
112 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
113 EDID_QUIRK_DETAILED_IN_CM },
114
115 /* LG Philips LCD LP154W01-A5 */
116 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
117 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
118
119 /* Philips 107p5 CRT */
120 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
121
122 /* Proview AY765C */
123 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
124
125 /* Samsung SyncMaster 205BW. Note: irony */
126 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
127 /* Samsung SyncMaster 22[5-6]BW */
128 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
129 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
130
131 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
132 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
133
134 /* ViewSonic VA2026w */
135 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
136
137 /* Medion MD 30217 PG */
138 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
139
140 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
141 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
142 };
143
144 /*
145 * Autogenerated from the DMT spec.
146 * This table is copied from xfree86/modes/xf86EdidModes.c.
147 */
148 static const struct drm_display_mode drm_dmt_modes[] = {
149 /* 640x350@85Hz */
150 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
151 736, 832, 0, 350, 382, 385, 445, 0,
152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
153 /* 640x400@85Hz */
154 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
155 736, 832, 0, 400, 401, 404, 445, 0,
156 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
157 /* 720x400@85Hz */
158 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
159 828, 936, 0, 400, 401, 404, 446, 0,
160 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
161 /* 640x480@60Hz */
162 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
163 752, 800, 0, 480, 489, 492, 525, 0,
164 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
165 /* 640x480@72Hz */
166 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
167 704, 832, 0, 480, 489, 492, 520, 0,
168 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
169 /* 640x480@75Hz */
170 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
171 720, 840, 0, 480, 481, 484, 500, 0,
172 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
173 /* 640x480@85Hz */
174 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
175 752, 832, 0, 480, 481, 484, 509, 0,
176 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
177 /* 800x600@56Hz */
178 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
179 896, 1024, 0, 600, 601, 603, 625, 0,
180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
181 /* 800x600@60Hz */
182 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
183 968, 1056, 0, 600, 601, 605, 628, 0,
184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
185 /* 800x600@72Hz */
186 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
187 976, 1040, 0, 600, 637, 643, 666, 0,
188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
189 /* 800x600@75Hz */
190 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
191 896, 1056, 0, 600, 601, 604, 625, 0,
192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
193 /* 800x600@85Hz */
194 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
195 896, 1048, 0, 600, 601, 604, 631, 0,
196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
197 /* 800x600@120Hz RB */
198 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
199 880, 960, 0, 600, 603, 607, 636, 0,
200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
201 /* 848x480@60Hz */
202 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
203 976, 1088, 0, 480, 486, 494, 517, 0,
204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
205 /* 1024x768@43Hz, interlace */
206 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
207 1208, 1264, 0, 768, 768, 772, 817, 0,
208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
209 DRM_MODE_FLAG_INTERLACE) },
210 /* 1024x768@60Hz */
211 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
212 1184, 1344, 0, 768, 771, 777, 806, 0,
213 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
214 /* 1024x768@70Hz */
215 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
216 1184, 1328, 0, 768, 771, 777, 806, 0,
217 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
218 /* 1024x768@75Hz */
219 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
220 1136, 1312, 0, 768, 769, 772, 800, 0,
221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
222 /* 1024x768@85Hz */
223 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
224 1168, 1376, 0, 768, 769, 772, 808, 0,
225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
226 /* 1024x768@120Hz RB */
227 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
228 1104, 1184, 0, 768, 771, 775, 813, 0,
229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
230 /* 1152x864@75Hz */
231 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
232 1344, 1600, 0, 864, 865, 868, 900, 0,
233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
234 /* 1280x768@60Hz RB */
235 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
236 1360, 1440, 0, 768, 771, 778, 790, 0,
237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
238 /* 1280x768@60Hz */
239 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
240 1472, 1664, 0, 768, 771, 778, 798, 0,
241 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
242 /* 1280x768@75Hz */
243 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
244 1488, 1696, 0, 768, 771, 778, 805, 0,
245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
246 /* 1280x768@85Hz */
247 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
248 1496, 1712, 0, 768, 771, 778, 809, 0,
249 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
250 /* 1280x768@120Hz RB */
251 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
252 1360, 1440, 0, 768, 771, 778, 813, 0,
253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
254 /* 1280x800@60Hz RB */
255 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
256 1360, 1440, 0, 800, 803, 809, 823, 0,
257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
258 /* 1280x800@60Hz */
259 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
260 1480, 1680, 0, 800, 803, 809, 831, 0,
261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
262 /* 1280x800@75Hz */
263 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
264 1488, 1696, 0, 800, 803, 809, 838, 0,
265 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
266 /* 1280x800@85Hz */
267 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
268 1496, 1712, 0, 800, 803, 809, 843, 0,
269 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
270 /* 1280x800@120Hz RB */
271 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
272 1360, 1440, 0, 800, 803, 809, 847, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
274 /* 1280x960@60Hz */
275 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
276 1488, 1800, 0, 960, 961, 964, 1000, 0,
277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
278 /* 1280x960@85Hz */
279 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
280 1504, 1728, 0, 960, 961, 964, 1011, 0,
281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
282 /* 1280x960@120Hz RB */
283 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
284 1360, 1440, 0, 960, 963, 967, 1017, 0,
285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
286 /* 1280x1024@60Hz */
287 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
288 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
290 /* 1280x1024@75Hz */
291 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
292 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
294 /* 1280x1024@85Hz */
295 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
296 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
298 /* 1280x1024@120Hz RB */
299 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
300 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
302 /* 1360x768@60Hz */
303 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
304 1536, 1792, 0, 768, 771, 777, 795, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
306 /* 1360x768@120Hz RB */
307 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
308 1440, 1520, 0, 768, 771, 776, 813, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
310 /* 1400x1050@60Hz RB */
311 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
312 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
314 /* 1400x1050@60Hz */
315 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
316 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
317 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
318 /* 1400x1050@75Hz */
319 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
320 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 1400x1050@85Hz */
323 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
324 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
326 /* 1400x1050@120Hz RB */
327 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
328 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
330 /* 1440x900@60Hz RB */
331 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
332 1520, 1600, 0, 900, 903, 909, 926, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
334 /* 1440x900@60Hz */
335 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
336 1672, 1904, 0, 900, 903, 909, 934, 0,
337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
338 /* 1440x900@75Hz */
339 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
340 1688, 1936, 0, 900, 903, 909, 942, 0,
341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 1440x900@85Hz */
343 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
344 1696, 1952, 0, 900, 903, 909, 948, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 1440x900@120Hz RB */
347 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
348 1520, 1600, 0, 900, 903, 909, 953, 0,
349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
350 /* 1600x1200@60Hz */
351 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
352 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
354 /* 1600x1200@65Hz */
355 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
356 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 1600x1200@70Hz */
359 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
360 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 1600x1200@75Hz */
363 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
364 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 1600x1200@85Hz */
367 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
368 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 1600x1200@120Hz RB */
371 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
372 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
374 /* 1680x1050@60Hz RB */
375 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
376 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
378 /* 1680x1050@60Hz */
379 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
380 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
381 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 1680x1050@75Hz */
383 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
384 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
385 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 1680x1050@85Hz */
387 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
388 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
389 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
390 /* 1680x1050@120Hz RB */
391 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
392 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
394 /* 1792x1344@60Hz */
395 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
396 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
397 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
398 /* 1792x1344@75Hz */
399 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
400 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
401 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
402 /* 1792x1344@120Hz RB */
403 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
404 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
406 /* 1856x1392@60Hz */
407 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
408 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 1856x1392@75Hz */
411 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
412 2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 1856x1392@120Hz RB */
415 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
416 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
418 /* 1920x1200@60Hz RB */
419 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
420 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
422 /* 1920x1200@60Hz */
423 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
424 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 1920x1200@75Hz */
427 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
428 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 1920x1200@85Hz */
431 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
432 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
434 /* 1920x1200@120Hz RB */
435 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
436 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
438 /* 1920x1440@60Hz */
439 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
440 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 1920x1440@75Hz */
443 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
444 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 1920x1440@120Hz RB */
447 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
448 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
450 /* 2560x1600@60Hz RB */
451 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
452 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
454 /* 2560x1600@60Hz */
455 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
456 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
457 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 2560x1600@75HZ */
459 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
460 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
461 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 2560x1600@85HZ */
463 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
464 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
465 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
466 /* 2560x1600@120Hz RB */
467 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
468 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
470 };
471
472 /*
473 * These more or less come from the DMT spec. The 720x400 modes are
474 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
475 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
476 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
477 * mode.
478 *
479 * The DMT modes have been fact-checked; the rest are mild guesses.
480 */
481 static const struct drm_display_mode edid_est_modes[] = {
482 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
483 968, 1056, 0, 600, 601, 605, 628, 0,
484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
485 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
486 896, 1024, 0, 600, 601, 603, 625, 0,
487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
488 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
489 720, 840, 0, 480, 481, 484, 500, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
491 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
492 704, 832, 0, 480, 489, 491, 520, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
494 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
495 768, 864, 0, 480, 483, 486, 525, 0,
496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
497 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
498 752, 800, 0, 480, 490, 492, 525, 0,
499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
500 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
501 846, 900, 0, 400, 421, 423, 449, 0,
502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
503 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
504 846, 900, 0, 400, 412, 414, 449, 0,
505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
506 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
507 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
509 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
510 1136, 1312, 0, 768, 769, 772, 800, 0,
511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
512 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
513 1184, 1328, 0, 768, 771, 777, 806, 0,
514 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
515 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
516 1184, 1344, 0, 768, 771, 777, 806, 0,
517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
518 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
519 1208, 1264, 0, 768, 768, 776, 817, 0,
520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
521 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
522 928, 1152, 0, 624, 625, 628, 667, 0,
523 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
524 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
525 896, 1056, 0, 600, 601, 604, 625, 0,
526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
527 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
528 976, 1040, 0, 600, 637, 643, 666, 0,
529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
530 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
531 1344, 1600, 0, 864, 865, 868, 900, 0,
532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
533 };
534
535 struct minimode {
536 short w;
537 short h;
538 short r;
539 short rb;
540 };
541
542 static const struct minimode est3_modes[] = {
543 /* byte 6 */
544 { 640, 350, 85, 0 },
545 { 640, 400, 85, 0 },
546 { 720, 400, 85, 0 },
547 { 640, 480, 85, 0 },
548 { 848, 480, 60, 0 },
549 { 800, 600, 85, 0 },
550 { 1024, 768, 85, 0 },
551 { 1152, 864, 75, 0 },
552 /* byte 7 */
553 { 1280, 768, 60, 1 },
554 { 1280, 768, 60, 0 },
555 { 1280, 768, 75, 0 },
556 { 1280, 768, 85, 0 },
557 { 1280, 960, 60, 0 },
558 { 1280, 960, 85, 0 },
559 { 1280, 1024, 60, 0 },
560 { 1280, 1024, 85, 0 },
561 /* byte 8 */
562 { 1360, 768, 60, 0 },
563 { 1440, 900, 60, 1 },
564 { 1440, 900, 60, 0 },
565 { 1440, 900, 75, 0 },
566 { 1440, 900, 85, 0 },
567 { 1400, 1050, 60, 1 },
568 { 1400, 1050, 60, 0 },
569 { 1400, 1050, 75, 0 },
570 /* byte 9 */
571 { 1400, 1050, 85, 0 },
572 { 1680, 1050, 60, 1 },
573 { 1680, 1050, 60, 0 },
574 { 1680, 1050, 75, 0 },
575 { 1680, 1050, 85, 0 },
576 { 1600, 1200, 60, 0 },
577 { 1600, 1200, 65, 0 },
578 { 1600, 1200, 70, 0 },
579 /* byte 10 */
580 { 1600, 1200, 75, 0 },
581 { 1600, 1200, 85, 0 },
582 { 1792, 1344, 60, 0 },
583 { 1792, 1344, 75, 0 },
584 { 1856, 1392, 60, 0 },
585 { 1856, 1392, 75, 0 },
586 { 1920, 1200, 60, 1 },
587 { 1920, 1200, 60, 0 },
588 /* byte 11 */
589 { 1920, 1200, 75, 0 },
590 { 1920, 1200, 85, 0 },
591 { 1920, 1440, 60, 0 },
592 { 1920, 1440, 75, 0 },
593 };
594
595 static const struct minimode extra_modes[] = {
596 { 1024, 576, 60, 0 },
597 { 1366, 768, 60, 0 },
598 { 1600, 900, 60, 0 },
599 { 1680, 945, 60, 0 },
600 { 1920, 1080, 60, 0 },
601 { 2048, 1152, 60, 0 },
602 { 2048, 1536, 60, 0 },
603 };
604
605 /*
606 * Probably taken from CEA-861 spec.
607 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
608 */
609 static const struct drm_display_mode edid_cea_modes[] = {
610 /* 1 - 640x480@60Hz */
611 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
612 752, 800, 0, 480, 490, 492, 525, 0,
613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
614 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
615 /* 2 - 720x480@60Hz */
616 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
617 798, 858, 0, 480, 489, 495, 525, 0,
618 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
619 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
620 /* 3 - 720x480@60Hz */
621 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
622 798, 858, 0, 480, 489, 495, 525, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
624 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
625 /* 4 - 1280x720@60Hz */
626 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
627 1430, 1650, 0, 720, 725, 730, 750, 0,
628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
629 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
630 /* 5 - 1920x1080i@60Hz */
631 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
632 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
634 DRM_MODE_FLAG_INTERLACE),
635 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
636 /* 6 - 720(1440)x480i@60Hz */
637 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
638 801, 858, 0, 480, 488, 494, 525, 0,
639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
640 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
641 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
642 /* 7 - 720(1440)x480i@60Hz */
643 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
644 801, 858, 0, 480, 488, 494, 525, 0,
645 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
646 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
647 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
648 /* 8 - 720(1440)x240@60Hz */
649 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
650 801, 858, 0, 240, 244, 247, 262, 0,
651 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
652 DRM_MODE_FLAG_DBLCLK),
653 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
654 /* 9 - 720(1440)x240@60Hz */
655 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
656 801, 858, 0, 240, 244, 247, 262, 0,
657 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
658 DRM_MODE_FLAG_DBLCLK),
659 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
660 /* 10 - 2880x480i@60Hz */
661 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
662 3204, 3432, 0, 480, 488, 494, 525, 0,
663 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
664 DRM_MODE_FLAG_INTERLACE),
665 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
666 /* 11 - 2880x480i@60Hz */
667 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
668 3204, 3432, 0, 480, 488, 494, 525, 0,
669 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
670 DRM_MODE_FLAG_INTERLACE),
671 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
672 /* 12 - 2880x240@60Hz */
673 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
674 3204, 3432, 0, 240, 244, 247, 262, 0,
675 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
676 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
677 /* 13 - 2880x240@60Hz */
678 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
679 3204, 3432, 0, 240, 244, 247, 262, 0,
680 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
681 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
682 /* 14 - 1440x480@60Hz */
683 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
684 1596, 1716, 0, 480, 489, 495, 525, 0,
685 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
686 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
687 /* 15 - 1440x480@60Hz */
688 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
689 1596, 1716, 0, 480, 489, 495, 525, 0,
690 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
691 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
692 /* 16 - 1920x1080@60Hz */
693 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
694 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
695 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
696 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
697 /* 17 - 720x576@50Hz */
698 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
699 796, 864, 0, 576, 581, 586, 625, 0,
700 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
701 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
702 /* 18 - 720x576@50Hz */
703 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
704 796, 864, 0, 576, 581, 586, 625, 0,
705 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
706 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
707 /* 19 - 1280x720@50Hz */
708 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
709 1760, 1980, 0, 720, 725, 730, 750, 0,
710 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
711 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
712 /* 20 - 1920x1080i@50Hz */
713 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
714 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
715 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
716 DRM_MODE_FLAG_INTERLACE),
717 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
718 /* 21 - 720(1440)x576i@50Hz */
719 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
720 795, 864, 0, 576, 580, 586, 625, 0,
721 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
722 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
723 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
724 /* 22 - 720(1440)x576i@50Hz */
725 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
726 795, 864, 0, 576, 580, 586, 625, 0,
727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
728 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
729 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
730 /* 23 - 720(1440)x288@50Hz */
731 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
732 795, 864, 0, 288, 290, 293, 312, 0,
733 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
734 DRM_MODE_FLAG_DBLCLK),
735 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
736 /* 24 - 720(1440)x288@50Hz */
737 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
738 795, 864, 0, 288, 290, 293, 312, 0,
739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
740 DRM_MODE_FLAG_DBLCLK),
741 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
742 /* 25 - 2880x576i@50Hz */
743 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
744 3180, 3456, 0, 576, 580, 586, 625, 0,
745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
746 DRM_MODE_FLAG_INTERLACE),
747 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
748 /* 26 - 2880x576i@50Hz */
749 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
750 3180, 3456, 0, 576, 580, 586, 625, 0,
751 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
752 DRM_MODE_FLAG_INTERLACE),
753 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
754 /* 27 - 2880x288@50Hz */
755 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
756 3180, 3456, 0, 288, 290, 293, 312, 0,
757 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
758 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
759 /* 28 - 2880x288@50Hz */
760 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
761 3180, 3456, 0, 288, 290, 293, 312, 0,
762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
763 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
764 /* 29 - 1440x576@50Hz */
765 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
766 1592, 1728, 0, 576, 581, 586, 625, 0,
767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
768 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
769 /* 30 - 1440x576@50Hz */
770 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
771 1592, 1728, 0, 576, 581, 586, 625, 0,
772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
773 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
774 /* 31 - 1920x1080@50Hz */
775 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
776 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
777 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
778 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
779 /* 32 - 1920x1080@24Hz */
780 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
781 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
782 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
783 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
784 /* 33 - 1920x1080@25Hz */
785 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
786 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
787 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
788 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
789 /* 34 - 1920x1080@30Hz */
790 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
791 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
792 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
793 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
794 /* 35 - 2880x480@60Hz */
795 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
796 3192, 3432, 0, 480, 489, 495, 525, 0,
797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
798 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
799 /* 36 - 2880x480@60Hz */
800 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
801 3192, 3432, 0, 480, 489, 495, 525, 0,
802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
803 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
804 /* 37 - 2880x576@50Hz */
805 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
806 3184, 3456, 0, 576, 581, 586, 625, 0,
807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
808 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
809 /* 38 - 2880x576@50Hz */
810 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
811 3184, 3456, 0, 576, 581, 586, 625, 0,
812 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
813 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
814 /* 39 - 1920x1080i@50Hz */
815 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
816 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
818 DRM_MODE_FLAG_INTERLACE),
819 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
820 /* 40 - 1920x1080i@100Hz */
821 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
822 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
824 DRM_MODE_FLAG_INTERLACE),
825 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
826 /* 41 - 1280x720@100Hz */
827 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
828 1760, 1980, 0, 720, 725, 730, 750, 0,
829 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
830 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
831 /* 42 - 720x576@100Hz */
832 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
833 796, 864, 0, 576, 581, 586, 625, 0,
834 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
835 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
836 /* 43 - 720x576@100Hz */
837 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
838 796, 864, 0, 576, 581, 586, 625, 0,
839 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
840 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
841 /* 44 - 720(1440)x576i@100Hz */
842 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
843 795, 864, 0, 576, 580, 586, 625, 0,
844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
845 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
846 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
847 /* 45 - 720(1440)x576i@100Hz */
848 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
849 795, 864, 0, 576, 580, 586, 625, 0,
850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
851 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
852 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
853 /* 46 - 1920x1080i@120Hz */
854 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
855 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
856 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
857 DRM_MODE_FLAG_INTERLACE),
858 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
859 /* 47 - 1280x720@120Hz */
860 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
861 1430, 1650, 0, 720, 725, 730, 750, 0,
862 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
863 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
864 /* 48 - 720x480@120Hz */
865 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
866 798, 858, 0, 480, 489, 495, 525, 0,
867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
868 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
869 /* 49 - 720x480@120Hz */
870 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
871 798, 858, 0, 480, 489, 495, 525, 0,
872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
873 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
874 /* 50 - 720(1440)x480i@120Hz */
875 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
876 801, 858, 0, 480, 488, 494, 525, 0,
877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
878 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
879 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
880 /* 51 - 720(1440)x480i@120Hz */
881 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
882 801, 858, 0, 480, 488, 494, 525, 0,
883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
884 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
885 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
886 /* 52 - 720x576@200Hz */
887 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
888 796, 864, 0, 576, 581, 586, 625, 0,
889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
890 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
891 /* 53 - 720x576@200Hz */
892 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
893 796, 864, 0, 576, 581, 586, 625, 0,
894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
895 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
896 /* 54 - 720(1440)x576i@200Hz */
897 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
898 795, 864, 0, 576, 580, 586, 625, 0,
899 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
900 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
901 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
902 /* 55 - 720(1440)x576i@200Hz */
903 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
904 795, 864, 0, 576, 580, 586, 625, 0,
905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
906 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
907 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
908 /* 56 - 720x480@240Hz */
909 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
910 798, 858, 0, 480, 489, 495, 525, 0,
911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
912 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
913 /* 57 - 720x480@240Hz */
914 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
915 798, 858, 0, 480, 489, 495, 525, 0,
916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
917 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
918 /* 58 - 720(1440)x480i@240 */
919 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
920 801, 858, 0, 480, 488, 494, 525, 0,
921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
922 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
923 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
924 /* 59 - 720(1440)x480i@240 */
925 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
926 801, 858, 0, 480, 488, 494, 525, 0,
927 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
928 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
929 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
930 /* 60 - 1280x720@24Hz */
931 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
932 3080, 3300, 0, 720, 725, 730, 750, 0,
933 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
934 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
935 /* 61 - 1280x720@25Hz */
936 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
937 3740, 3960, 0, 720, 725, 730, 750, 0,
938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
939 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
940 /* 62 - 1280x720@30Hz */
941 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
942 3080, 3300, 0, 720, 725, 730, 750, 0,
943 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
944 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
945 /* 63 - 1920x1080@120Hz */
946 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
947 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
948 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
949 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
950 /* 64 - 1920x1080@100Hz */
951 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
952 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
953 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
954 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
955 };
956
957 /*
958 * HDMI 1.4 4k modes.
959 */
960 static const struct drm_display_mode edid_4k_modes[] = {
961 /* 1 - 3840x2160@30Hz */
962 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
963 3840, 4016, 4104, 4400, 0,
964 2160, 2168, 2178, 2250, 0,
965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
966 .vrefresh = 30, },
967 /* 2 - 3840x2160@25Hz */
968 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
969 3840, 4896, 4984, 5280, 0,
970 2160, 2168, 2178, 2250, 0,
971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
972 .vrefresh = 25, },
973 /* 3 - 3840x2160@24Hz */
974 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
975 3840, 5116, 5204, 5500, 0,
976 2160, 2168, 2178, 2250, 0,
977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
978 .vrefresh = 24, },
979 /* 4 - 4096x2160@24Hz (SMPTE) */
980 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
981 4096, 5116, 5204, 5500, 0,
982 2160, 2168, 2178, 2250, 0,
983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
984 .vrefresh = 24, },
985 };
986
987 /*** DDC fetch and block validation ***/
988
989 static const u8 edid_header[] = {
990 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
991 };
992
993 /**
994 * drm_edid_header_is_valid - sanity check the header of the base EDID block
995 * @raw_edid: pointer to raw base EDID block
996 *
997 * Sanity check the header of the base EDID block.
998 *
999 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1000 */
1001 int drm_edid_header_is_valid(const u8 *raw_edid)
1002 {
1003 int i, score = 0;
1004
1005 for (i = 0; i < sizeof(edid_header); i++)
1006 if (raw_edid[i] == edid_header[i])
1007 score++;
1008
1009 return score;
1010 }
1011 EXPORT_SYMBOL(drm_edid_header_is_valid);
1012
1013 static int edid_fixup __read_mostly = 6;
1014 module_param_named(edid_fixup, edid_fixup, int, 0400);
1015 MODULE_PARM_DESC(edid_fixup,
1016 "Minimum number of valid EDID header bytes (0-8, default 6)");
1017
1018 static void drm_get_displayid(struct drm_connector *connector,
1019 struct edid *edid);
1020
1021 static int drm_edid_block_checksum(const u8 *raw_edid)
1022 {
1023 int i;
1024 u8 csum = 0;
1025 for (i = 0; i < EDID_LENGTH; i++)
1026 csum += raw_edid[i];
1027
1028 return csum;
1029 }
1030
1031 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1032 {
1033 if (memchr_inv(in_edid, 0, length))
1034 return false;
1035
1036 return true;
1037 }
1038
1039 /**
1040 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1041 * @raw_edid: pointer to raw EDID block
1042 * @block: type of block to validate (0 for base, extension otherwise)
1043 * @print_bad_edid: if true, dump bad EDID blocks to the console
1044 * @edid_corrupt: if true, the header or checksum is invalid
1045 *
1046 * Validate a base or extension EDID block and optionally dump bad blocks to
1047 * the console.
1048 *
1049 * Return: True if the block is valid, false otherwise.
1050 */
1051 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1052 bool *edid_corrupt)
1053 {
1054 u8 csum;
1055 struct edid *edid = (struct edid *)raw_edid;
1056
1057 if (WARN_ON(!raw_edid))
1058 return false;
1059
1060 if (edid_fixup > 8 || edid_fixup < 0)
1061 edid_fixup = 6;
1062
1063 if (block == 0) {
1064 int score = drm_edid_header_is_valid(raw_edid);
1065 if (score == 8) {
1066 if (edid_corrupt)
1067 *edid_corrupt = false;
1068 } else if (score >= edid_fixup) {
1069 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1070 * The corrupt flag needs to be set here otherwise, the
1071 * fix-up code here will correct the problem, the
1072 * checksum is correct and the test fails
1073 */
1074 if (edid_corrupt)
1075 *edid_corrupt = true;
1076 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1077 memcpy(raw_edid, edid_header, sizeof(edid_header));
1078 } else {
1079 if (edid_corrupt)
1080 *edid_corrupt = true;
1081 goto bad;
1082 }
1083 }
1084
1085 csum = drm_edid_block_checksum(raw_edid);
1086 if (csum) {
1087 if (print_bad_edid) {
1088 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
1089 }
1090
1091 if (edid_corrupt)
1092 *edid_corrupt = true;
1093
1094 /* allow CEA to slide through, switches mangle this */
1095 if (raw_edid[0] != 0x02)
1096 goto bad;
1097 }
1098
1099 /* per-block-type checks */
1100 switch (raw_edid[0]) {
1101 case 0: /* base */
1102 if (edid->version != 1) {
1103 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
1104 goto bad;
1105 }
1106
1107 if (edid->revision > 4)
1108 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1109 break;
1110
1111 default:
1112 break;
1113 }
1114
1115 return true;
1116
1117 bad:
1118 if (print_bad_edid) {
1119 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1120 printk(KERN_ERR "EDID block is all zeroes\n");
1121 } else {
1122 printk(KERN_ERR "Raw EDID:\n");
1123 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
1124 raw_edid, EDID_LENGTH, false);
1125 }
1126 }
1127 return false;
1128 }
1129 EXPORT_SYMBOL(drm_edid_block_valid);
1130
1131 /**
1132 * drm_edid_is_valid - sanity check EDID data
1133 * @edid: EDID data
1134 *
1135 * Sanity-check an entire EDID record (including extensions)
1136 *
1137 * Return: True if the EDID data is valid, false otherwise.
1138 */
1139 bool drm_edid_is_valid(struct edid *edid)
1140 {
1141 int i;
1142 u8 *raw = (u8 *)edid;
1143
1144 if (!edid)
1145 return false;
1146
1147 for (i = 0; i <= edid->extensions; i++)
1148 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1149 return false;
1150
1151 return true;
1152 }
1153 EXPORT_SYMBOL(drm_edid_is_valid);
1154
1155 #define DDC_SEGMENT_ADDR 0x30
1156 /**
1157 * drm_do_probe_ddc_edid() - get EDID information via I2C
1158 * @data: I2C device adapter
1159 * @buf: EDID data buffer to be filled
1160 * @block: 128 byte EDID block to start fetching from
1161 * @len: EDID data buffer length to fetch
1162 *
1163 * Try to fetch EDID information by calling I2C driver functions.
1164 *
1165 * Return: 0 on success or -1 on failure.
1166 */
1167 static int
1168 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1169 {
1170 struct i2c_adapter *adapter = data;
1171 unsigned char start = block * EDID_LENGTH;
1172 unsigned char segment = block >> 1;
1173 unsigned char xfers = segment ? 3 : 2;
1174 int ret, retries = 5;
1175
1176 /*
1177 * The core I2C driver will automatically retry the transfer if the
1178 * adapter reports EAGAIN. However, we find that bit-banging transfers
1179 * are susceptible to errors under a heavily loaded machine and
1180 * generate spurious NAKs and timeouts. Retrying the transfer
1181 * of the individual block a few times seems to overcome this.
1182 */
1183 do {
1184 struct i2c_msg msgs[] = {
1185 {
1186 .addr = DDC_SEGMENT_ADDR,
1187 .flags = 0,
1188 .len = 1,
1189 .buf = &segment,
1190 }, {
1191 .addr = DDC_ADDR,
1192 .flags = 0,
1193 .len = 1,
1194 .buf = &start,
1195 }, {
1196 .addr = DDC_ADDR,
1197 .flags = I2C_M_RD,
1198 .len = len,
1199 .buf = buf,
1200 }
1201 };
1202
1203 /*
1204 * Avoid sending the segment addr to not upset non-compliant
1205 * DDC monitors.
1206 */
1207 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1208
1209 if (ret == -ENXIO) {
1210 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1211 adapter->name);
1212 break;
1213 }
1214 } while (ret != xfers && --retries);
1215
1216 return ret == xfers ? 0 : -1;
1217 }
1218
1219 /**
1220 * drm_do_get_edid - get EDID data using a custom EDID block read function
1221 * @connector: connector we're probing
1222 * @get_edid_block: EDID block read function
1223 * @data: private data passed to the block read function
1224 *
1225 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1226 * exposes a different interface to read EDID blocks this function can be used
1227 * to get EDID data using a custom block read function.
1228 *
1229 * As in the general case the DDC bus is accessible by the kernel at the I2C
1230 * level, drivers must make all reasonable efforts to expose it as an I2C
1231 * adapter and use drm_get_edid() instead of abusing this function.
1232 *
1233 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1234 */
1235 struct edid *drm_do_get_edid(struct drm_connector *connector,
1236 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1237 size_t len),
1238 void *data)
1239 {
1240 int i, j = 0, valid_extensions = 0;
1241 u8 *block, *new;
1242 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS);
1243
1244 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1245 return NULL;
1246
1247 /* base block fetch */
1248 for (i = 0; i < 4; i++) {
1249 if (get_edid_block(data, block, 0, EDID_LENGTH))
1250 goto out;
1251 if (drm_edid_block_valid(block, 0, print_bad_edid,
1252 &connector->edid_corrupt))
1253 break;
1254 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
1255 connector->null_edid_counter++;
1256 goto carp;
1257 }
1258 }
1259 if (i == 4)
1260 goto carp;
1261
1262 /* if there's no extensions, we're done */
1263 if (block[0x7e] == 0)
1264 return (struct edid *)block;
1265
1266 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
1267 if (!new)
1268 goto out;
1269 block = new;
1270
1271 for (j = 1; j <= block[0x7e]; j++) {
1272 for (i = 0; i < 4; i++) {
1273 if (get_edid_block(data,
1274 block + (valid_extensions + 1) * EDID_LENGTH,
1275 j, EDID_LENGTH))
1276 goto out;
1277 if (drm_edid_block_valid(block + (valid_extensions + 1)
1278 * EDID_LENGTH, j,
1279 print_bad_edid,
1280 NULL)) {
1281 valid_extensions++;
1282 break;
1283 }
1284 }
1285
1286 if (i == 4 && print_bad_edid) {
1287 dev_warn(connector->dev->dev,
1288 "%s: Ignoring invalid EDID block %d.\n",
1289 connector->name, j);
1290
1291 connector->bad_edid_counter++;
1292 }
1293 }
1294
1295 if (valid_extensions != block[0x7e]) {
1296 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1297 block[0x7e] = valid_extensions;
1298 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1299 if (!new)
1300 goto out;
1301 block = new;
1302 }
1303
1304 return (struct edid *)block;
1305
1306 carp:
1307 if (print_bad_edid) {
1308 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
1309 connector->name, j);
1310 }
1311 connector->bad_edid_counter++;
1312
1313 out:
1314 kfree(block);
1315 return NULL;
1316 }
1317 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1318
1319 /**
1320 * drm_probe_ddc() - probe DDC presence
1321 * @adapter: I2C adapter to probe
1322 *
1323 * Return: True on success, false on failure.
1324 */
1325 bool
1326 drm_probe_ddc(struct i2c_adapter *adapter)
1327 {
1328 unsigned char out;
1329
1330 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1331 }
1332 EXPORT_SYMBOL(drm_probe_ddc);
1333
1334 /**
1335 * drm_get_edid - get EDID data, if available
1336 * @connector: connector we're probing
1337 * @adapter: I2C adapter to use for DDC
1338 *
1339 * Poke the given I2C channel to grab EDID data if possible. If found,
1340 * attach it to the connector.
1341 *
1342 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1343 */
1344 struct edid *drm_get_edid(struct drm_connector *connector,
1345 struct i2c_adapter *adapter)
1346 {
1347 struct edid *edid;
1348
1349 if (!drm_probe_ddc(adapter))
1350 return NULL;
1351
1352 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1353 if (edid)
1354 drm_get_displayid(connector, edid);
1355 return edid;
1356 }
1357 EXPORT_SYMBOL(drm_get_edid);
1358
1359 /**
1360 * drm_edid_duplicate - duplicate an EDID and the extensions
1361 * @edid: EDID to duplicate
1362 *
1363 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1364 */
1365 struct edid *drm_edid_duplicate(const struct edid *edid)
1366 {
1367 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1368 }
1369 EXPORT_SYMBOL(drm_edid_duplicate);
1370
1371 /*** EDID parsing ***/
1372
1373 /**
1374 * edid_vendor - match a string against EDID's obfuscated vendor field
1375 * @edid: EDID to match
1376 * @vendor: vendor string
1377 *
1378 * Returns true if @vendor is in @edid, false otherwise
1379 */
1380 static bool edid_vendor(struct edid *edid, char *vendor)
1381 {
1382 char edid_vendor[3];
1383
1384 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1385 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1386 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1387 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1388
1389 return !strncmp(edid_vendor, vendor, 3);
1390 }
1391
1392 /**
1393 * edid_get_quirks - return quirk flags for a given EDID
1394 * @edid: EDID to process
1395 *
1396 * This tells subsequent routines what fixes they need to apply.
1397 */
1398 static u32 edid_get_quirks(struct edid *edid)
1399 {
1400 struct edid_quirk *quirk;
1401 int i;
1402
1403 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1404 quirk = &edid_quirk_list[i];
1405
1406 if (edid_vendor(edid, quirk->vendor) &&
1407 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1408 return quirk->quirks;
1409 }
1410
1411 return 0;
1412 }
1413
1414 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1415 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1416
1417 /**
1418 * edid_fixup_preferred - set preferred modes based on quirk list
1419 * @connector: has mode list to fix up
1420 * @quirks: quirks list
1421 *
1422 * Walk the mode list for @connector, clearing the preferred status
1423 * on existing modes and setting it anew for the right mode ala @quirks.
1424 */
1425 static void edid_fixup_preferred(struct drm_connector *connector,
1426 u32 quirks)
1427 {
1428 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1429 int target_refresh = 0;
1430 int cur_vrefresh, preferred_vrefresh;
1431
1432 if (list_empty(&connector->probed_modes))
1433 return;
1434
1435 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1436 target_refresh = 60;
1437 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1438 target_refresh = 75;
1439
1440 preferred_mode = list_first_entry(&connector->probed_modes,
1441 struct drm_display_mode, head);
1442
1443 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1444 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1445
1446 if (cur_mode == preferred_mode)
1447 continue;
1448
1449 /* Largest mode is preferred */
1450 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1451 preferred_mode = cur_mode;
1452
1453 cur_vrefresh = cur_mode->vrefresh ?
1454 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1455 preferred_vrefresh = preferred_mode->vrefresh ?
1456 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1457 /* At a given size, try to get closest to target refresh */
1458 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1459 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1460 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1461 preferred_mode = cur_mode;
1462 }
1463 }
1464
1465 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1466 }
1467
1468 static bool
1469 mode_is_rb(const struct drm_display_mode *mode)
1470 {
1471 return (mode->htotal - mode->hdisplay == 160) &&
1472 (mode->hsync_end - mode->hdisplay == 80) &&
1473 (mode->hsync_end - mode->hsync_start == 32) &&
1474 (mode->vsync_start - mode->vdisplay == 3);
1475 }
1476
1477 /*
1478 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1479 * @dev: Device to duplicate against
1480 * @hsize: Mode width
1481 * @vsize: Mode height
1482 * @fresh: Mode refresh rate
1483 * @rb: Mode reduced-blanking-ness
1484 *
1485 * Walk the DMT mode list looking for a match for the given parameters.
1486 *
1487 * Return: A newly allocated copy of the mode, or NULL if not found.
1488 */
1489 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1490 int hsize, int vsize, int fresh,
1491 bool rb)
1492 {
1493 int i;
1494
1495 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1496 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1497 if (hsize != ptr->hdisplay)
1498 continue;
1499 if (vsize != ptr->vdisplay)
1500 continue;
1501 if (fresh != drm_mode_vrefresh(ptr))
1502 continue;
1503 if (rb != mode_is_rb(ptr))
1504 continue;
1505
1506 return drm_mode_duplicate(dev, ptr);
1507 }
1508
1509 return NULL;
1510 }
1511 EXPORT_SYMBOL(drm_mode_find_dmt);
1512
1513 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1514
1515 static void
1516 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1517 {
1518 int i, n = 0;
1519 u8 d = ext[0x02];
1520 u8 *det_base = ext + d;
1521
1522 n = (127 - d) / 18;
1523 for (i = 0; i < n; i++)
1524 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1525 }
1526
1527 static void
1528 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1529 {
1530 unsigned int i, n = min((int)ext[0x02], 6);
1531 u8 *det_base = ext + 5;
1532
1533 if (ext[0x01] != 1)
1534 return; /* unknown version */
1535
1536 for (i = 0; i < n; i++)
1537 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1538 }
1539
1540 static void
1541 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1542 {
1543 int i;
1544 struct edid *edid = (struct edid *)raw_edid;
1545
1546 if (edid == NULL)
1547 return;
1548
1549 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1550 cb(&(edid->detailed_timings[i]), closure);
1551
1552 for (i = 1; i <= raw_edid[0x7e]; i++) {
1553 u8 *ext = raw_edid + (i * EDID_LENGTH);
1554 switch (*ext) {
1555 case CEA_EXT:
1556 cea_for_each_detailed_block(ext, cb, closure);
1557 break;
1558 case VTB_EXT:
1559 vtb_for_each_detailed_block(ext, cb, closure);
1560 break;
1561 default:
1562 break;
1563 }
1564 }
1565 }
1566
1567 static void
1568 is_rb(struct detailed_timing *t, void *data)
1569 {
1570 u8 *r = (u8 *)t;
1571 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1572 if (r[15] & 0x10)
1573 *(bool *)data = true;
1574 }
1575
1576 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1577 static bool
1578 drm_monitor_supports_rb(struct edid *edid)
1579 {
1580 if (edid->revision >= 4) {
1581 bool ret = false;
1582 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1583 return ret;
1584 }
1585
1586 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1587 }
1588
1589 static void
1590 find_gtf2(struct detailed_timing *t, void *data)
1591 {
1592 u8 *r = (u8 *)t;
1593 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1594 *(u8 **)data = r;
1595 }
1596
1597 /* Secondary GTF curve kicks in above some break frequency */
1598 static int
1599 drm_gtf2_hbreak(struct edid *edid)
1600 {
1601 u8 *r = NULL;
1602 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1603 return r ? (r[12] * 2) : 0;
1604 }
1605
1606 static int
1607 drm_gtf2_2c(struct edid *edid)
1608 {
1609 u8 *r = NULL;
1610 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1611 return r ? r[13] : 0;
1612 }
1613
1614 static int
1615 drm_gtf2_m(struct edid *edid)
1616 {
1617 u8 *r = NULL;
1618 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1619 return r ? (r[15] << 8) + r[14] : 0;
1620 }
1621
1622 static int
1623 drm_gtf2_k(struct edid *edid)
1624 {
1625 u8 *r = NULL;
1626 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1627 return r ? r[16] : 0;
1628 }
1629
1630 static int
1631 drm_gtf2_2j(struct edid *edid)
1632 {
1633 u8 *r = NULL;
1634 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1635 return r ? r[17] : 0;
1636 }
1637
1638 /**
1639 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1640 * @edid: EDID block to scan
1641 */
1642 static int standard_timing_level(struct edid *edid)
1643 {
1644 if (edid->revision >= 2) {
1645 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1646 return LEVEL_CVT;
1647 if (drm_gtf2_hbreak(edid))
1648 return LEVEL_GTF2;
1649 return LEVEL_GTF;
1650 }
1651 return LEVEL_DMT;
1652 }
1653
1654 /*
1655 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1656 * monitors fill with ascii space (0x20) instead.
1657 */
1658 static int
1659 bad_std_timing(u8 a, u8 b)
1660 {
1661 return (a == 0x00 && b == 0x00) ||
1662 (a == 0x01 && b == 0x01) ||
1663 (a == 0x20 && b == 0x20);
1664 }
1665
1666 /**
1667 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
1668 * @connector: connector of for the EDID block
1669 * @edid: EDID block to scan
1670 * @t: standard timing params
1671 *
1672 * Take the standard timing params (in this case width, aspect, and refresh)
1673 * and convert them into a real mode using CVT/GTF/DMT.
1674 */
1675 static struct drm_display_mode *
1676 drm_mode_std(struct drm_connector *connector, struct edid *edid,
1677 struct std_timing *t)
1678 {
1679 struct drm_device *dev = connector->dev;
1680 struct drm_display_mode *m, *mode = NULL;
1681 int hsize, vsize;
1682 int vrefresh_rate;
1683 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1684 >> EDID_TIMING_ASPECT_SHIFT;
1685 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1686 >> EDID_TIMING_VFREQ_SHIFT;
1687 int timing_level = standard_timing_level(edid);
1688
1689 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1690 return NULL;
1691
1692 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1693 hsize = t->hsize * 8 + 248;
1694 /* vrefresh_rate = vfreq + 60 */
1695 vrefresh_rate = vfreq + 60;
1696 /* the vdisplay is calculated based on the aspect ratio */
1697 if (aspect_ratio == 0) {
1698 if (edid->revision < 3)
1699 vsize = hsize;
1700 else
1701 vsize = (hsize * 10) / 16;
1702 } else if (aspect_ratio == 1)
1703 vsize = (hsize * 3) / 4;
1704 else if (aspect_ratio == 2)
1705 vsize = (hsize * 4) / 5;
1706 else
1707 vsize = (hsize * 9) / 16;
1708
1709 /* HDTV hack, part 1 */
1710 if (vrefresh_rate == 60 &&
1711 ((hsize == 1360 && vsize == 765) ||
1712 (hsize == 1368 && vsize == 769))) {
1713 hsize = 1366;
1714 vsize = 768;
1715 }
1716
1717 /*
1718 * If this connector already has a mode for this size and refresh
1719 * rate (because it came from detailed or CVT info), use that
1720 * instead. This way we don't have to guess at interlace or
1721 * reduced blanking.
1722 */
1723 list_for_each_entry(m, &connector->probed_modes, head)
1724 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1725 drm_mode_vrefresh(m) == vrefresh_rate)
1726 return NULL;
1727
1728 /* HDTV hack, part 2 */
1729 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1730 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
1731 false);
1732 mode->hdisplay = 1366;
1733 mode->hsync_start = mode->hsync_start - 1;
1734 mode->hsync_end = mode->hsync_end - 1;
1735 return mode;
1736 }
1737
1738 /* check whether it can be found in default mode table */
1739 if (drm_monitor_supports_rb(edid)) {
1740 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
1741 true);
1742 if (mode)
1743 return mode;
1744 }
1745 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
1746 if (mode)
1747 return mode;
1748
1749 /* okay, generate it */
1750 switch (timing_level) {
1751 case LEVEL_DMT:
1752 break;
1753 case LEVEL_GTF:
1754 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1755 break;
1756 case LEVEL_GTF2:
1757 /*
1758 * This is potentially wrong if there's ever a monitor with
1759 * more than one ranges section, each claiming a different
1760 * secondary GTF curve. Please don't do that.
1761 */
1762 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1763 if (!mode)
1764 return NULL;
1765 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
1766 drm_mode_destroy(dev, mode);
1767 mode = drm_gtf_mode_complex(dev, hsize, vsize,
1768 vrefresh_rate, 0, 0,
1769 drm_gtf2_m(edid),
1770 drm_gtf2_2c(edid),
1771 drm_gtf2_k(edid),
1772 drm_gtf2_2j(edid));
1773 }
1774 break;
1775 case LEVEL_CVT:
1776 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
1777 false);
1778 break;
1779 }
1780 return mode;
1781 }
1782
1783 /*
1784 * EDID is delightfully ambiguous about how interlaced modes are to be
1785 * encoded. Our internal representation is of frame height, but some
1786 * HDTV detailed timings are encoded as field height.
1787 *
1788 * The format list here is from CEA, in frame size. Technically we
1789 * should be checking refresh rate too. Whatever.
1790 */
1791 static void
1792 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
1793 struct detailed_pixel_timing *pt)
1794 {
1795 int i;
1796 static const struct {
1797 int w, h;
1798 } cea_interlaced[] = {
1799 { 1920, 1080 },
1800 { 720, 480 },
1801 { 1440, 480 },
1802 { 2880, 480 },
1803 { 720, 576 },
1804 { 1440, 576 },
1805 { 2880, 576 },
1806 };
1807
1808 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
1809 return;
1810
1811 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
1812 if ((mode->hdisplay == cea_interlaced[i].w) &&
1813 (mode->vdisplay == cea_interlaced[i].h / 2)) {
1814 mode->vdisplay *= 2;
1815 mode->vsync_start *= 2;
1816 mode->vsync_end *= 2;
1817 mode->vtotal *= 2;
1818 mode->vtotal |= 1;
1819 }
1820 }
1821
1822 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1823 }
1824
1825 /**
1826 * drm_mode_detailed - create a new mode from an EDID detailed timing section
1827 * @dev: DRM device (needed to create new mode)
1828 * @edid: EDID block
1829 * @timing: EDID detailed timing info
1830 * @quirks: quirks to apply
1831 *
1832 * An EDID detailed timing block contains enough info for us to create and
1833 * return a new struct drm_display_mode.
1834 */
1835 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1836 struct edid *edid,
1837 struct detailed_timing *timing,
1838 u32 quirks)
1839 {
1840 struct drm_display_mode *mode;
1841 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
1842 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
1843 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
1844 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
1845 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
1846 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
1847 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
1848 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
1849 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
1850
1851 /* ignore tiny modes */
1852 if (hactive < 64 || vactive < 64)
1853 return NULL;
1854
1855 if (pt->misc & DRM_EDID_PT_STEREO) {
1856 DRM_DEBUG_KMS("stereo mode not supported\n");
1857 return NULL;
1858 }
1859 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
1860 DRM_DEBUG_KMS("composite sync not supported\n");
1861 }
1862
1863 /* it is incorrect if hsync/vsync width is zero */
1864 if (!hsync_pulse_width || !vsync_pulse_width) {
1865 DRM_DEBUG_KMS("Incorrect Detailed timing. "
1866 "Wrong Hsync/Vsync pulse width\n");
1867 return NULL;
1868 }
1869
1870 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
1871 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
1872 if (!mode)
1873 return NULL;
1874
1875 goto set_size;
1876 }
1877
1878 mode = drm_mode_create(dev);
1879 if (!mode)
1880 return NULL;
1881
1882 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
1883 timing->pixel_clock = cpu_to_le16(1088);
1884
1885 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
1886
1887 mode->hdisplay = hactive;
1888 mode->hsync_start = mode->hdisplay + hsync_offset;
1889 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
1890 mode->htotal = mode->hdisplay + hblank;
1891
1892 mode->vdisplay = vactive;
1893 mode->vsync_start = mode->vdisplay + vsync_offset;
1894 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
1895 mode->vtotal = mode->vdisplay + vblank;
1896
1897 /* Some EDIDs have bogus h/vtotal values */
1898 if (mode->hsync_end > mode->htotal)
1899 mode->htotal = mode->hsync_end + 1;
1900 if (mode->vsync_end > mode->vtotal)
1901 mode->vtotal = mode->vsync_end + 1;
1902
1903 drm_mode_do_interlace_quirk(mode, pt);
1904
1905 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
1906 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
1907 }
1908
1909 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
1910 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
1911 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
1912 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
1913
1914 set_size:
1915 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
1916 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
1917
1918 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
1919 mode->width_mm *= 10;
1920 mode->height_mm *= 10;
1921 }
1922
1923 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
1924 mode->width_mm = edid->width_cm * 10;
1925 mode->height_mm = edid->height_cm * 10;
1926 }
1927
1928 mode->type = DRM_MODE_TYPE_DRIVER;
1929 mode->vrefresh = drm_mode_vrefresh(mode);
1930 drm_mode_set_name(mode);
1931
1932 return mode;
1933 }
1934
1935 static bool
1936 mode_in_hsync_range(const struct drm_display_mode *mode,
1937 struct edid *edid, u8 *t)
1938 {
1939 int hsync, hmin, hmax;
1940
1941 hmin = t[7];
1942 if (edid->revision >= 4)
1943 hmin += ((t[4] & 0x04) ? 255 : 0);
1944 hmax = t[8];
1945 if (edid->revision >= 4)
1946 hmax += ((t[4] & 0x08) ? 255 : 0);
1947 hsync = drm_mode_hsync(mode);
1948
1949 return (hsync <= hmax && hsync >= hmin);
1950 }
1951
1952 static bool
1953 mode_in_vsync_range(const struct drm_display_mode *mode,
1954 struct edid *edid, u8 *t)
1955 {
1956 int vsync, vmin, vmax;
1957
1958 vmin = t[5];
1959 if (edid->revision >= 4)
1960 vmin += ((t[4] & 0x01) ? 255 : 0);
1961 vmax = t[6];
1962 if (edid->revision >= 4)
1963 vmax += ((t[4] & 0x02) ? 255 : 0);
1964 vsync = drm_mode_vrefresh(mode);
1965
1966 return (vsync <= vmax && vsync >= vmin);
1967 }
1968
1969 static u32
1970 range_pixel_clock(struct edid *edid, u8 *t)
1971 {
1972 /* unspecified */
1973 if (t[9] == 0 || t[9] == 255)
1974 return 0;
1975
1976 /* 1.4 with CVT support gives us real precision, yay */
1977 if (edid->revision >= 4 && t[10] == 0x04)
1978 return (t[9] * 10000) - ((t[12] >> 2) * 250);
1979
1980 /* 1.3 is pathetic, so fuzz up a bit */
1981 return t[9] * 10000 + 5001;
1982 }
1983
1984 static bool
1985 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
1986 struct detailed_timing *timing)
1987 {
1988 u32 max_clock;
1989 u8 *t = (u8 *)timing;
1990
1991 if (!mode_in_hsync_range(mode, edid, t))
1992 return false;
1993
1994 if (!mode_in_vsync_range(mode, edid, t))
1995 return false;
1996
1997 if ((max_clock = range_pixel_clock(edid, t)))
1998 if (mode->clock > max_clock)
1999 return false;
2000
2001 /* 1.4 max horizontal check */
2002 if (edid->revision >= 4 && t[10] == 0x04)
2003 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2004 return false;
2005
2006 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2007 return false;
2008
2009 return true;
2010 }
2011
2012 static bool valid_inferred_mode(const struct drm_connector *connector,
2013 const struct drm_display_mode *mode)
2014 {
2015 struct drm_display_mode *m;
2016 bool ok = false;
2017
2018 list_for_each_entry(m, &connector->probed_modes, head) {
2019 if (mode->hdisplay == m->hdisplay &&
2020 mode->vdisplay == m->vdisplay &&
2021 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2022 return false; /* duplicated */
2023 if (mode->hdisplay <= m->hdisplay &&
2024 mode->vdisplay <= m->vdisplay)
2025 ok = true;
2026 }
2027 return ok;
2028 }
2029
2030 static int
2031 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2032 struct detailed_timing *timing)
2033 {
2034 int i, modes = 0;
2035 struct drm_display_mode *newmode;
2036 struct drm_device *dev = connector->dev;
2037
2038 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2039 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2040 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2041 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2042 if (newmode) {
2043 drm_mode_probed_add(connector, newmode);
2044 modes++;
2045 }
2046 }
2047 }
2048
2049 return modes;
2050 }
2051
2052 /* fix up 1366x768 mode from 1368x768;
2053 * GFT/CVT can't express 1366 width which isn't dividable by 8
2054 */
2055 static void fixup_mode_1366x768(struct drm_display_mode *mode)
2056 {
2057 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2058 mode->hdisplay = 1366;
2059 mode->hsync_start--;
2060 mode->hsync_end--;
2061 drm_mode_set_name(mode);
2062 }
2063 }
2064
2065 static int
2066 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2067 struct detailed_timing *timing)
2068 {
2069 int i, modes = 0;
2070 struct drm_display_mode *newmode;
2071 struct drm_device *dev = connector->dev;
2072
2073 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2074 const struct minimode *m = &extra_modes[i];
2075 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2076 if (!newmode)
2077 return modes;
2078
2079 fixup_mode_1366x768(newmode);
2080 if (!mode_in_range(newmode, edid, timing) ||
2081 !valid_inferred_mode(connector, newmode)) {
2082 drm_mode_destroy(dev, newmode);
2083 continue;
2084 }
2085
2086 drm_mode_probed_add(connector, newmode);
2087 modes++;
2088 }
2089
2090 return modes;
2091 }
2092
2093 static int
2094 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2095 struct detailed_timing *timing)
2096 {
2097 int i, modes = 0;
2098 struct drm_display_mode *newmode;
2099 struct drm_device *dev = connector->dev;
2100 bool rb = drm_monitor_supports_rb(edid);
2101
2102 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2103 const struct minimode *m = &extra_modes[i];
2104 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2105 if (!newmode)
2106 return modes;
2107
2108 fixup_mode_1366x768(newmode);
2109 if (!mode_in_range(newmode, edid, timing) ||
2110 !valid_inferred_mode(connector, newmode)) {
2111 drm_mode_destroy(dev, newmode);
2112 continue;
2113 }
2114
2115 drm_mode_probed_add(connector, newmode);
2116 modes++;
2117 }
2118
2119 return modes;
2120 }
2121
2122 static void
2123 do_inferred_modes(struct detailed_timing *timing, void *c)
2124 {
2125 struct detailed_mode_closure *closure = c;
2126 struct detailed_non_pixel *data = &timing->data.other_data;
2127 struct detailed_data_monitor_range *range = &data->data.range;
2128
2129 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2130 return;
2131
2132 closure->modes += drm_dmt_modes_for_range(closure->connector,
2133 closure->edid,
2134 timing);
2135
2136 if (!version_greater(closure->edid, 1, 1))
2137 return; /* GTF not defined yet */
2138
2139 switch (range->flags) {
2140 case 0x02: /* secondary gtf, XXX could do more */
2141 case 0x00: /* default gtf */
2142 closure->modes += drm_gtf_modes_for_range(closure->connector,
2143 closure->edid,
2144 timing);
2145 break;
2146 case 0x04: /* cvt, only in 1.4+ */
2147 if (!version_greater(closure->edid, 1, 3))
2148 break;
2149
2150 closure->modes += drm_cvt_modes_for_range(closure->connector,
2151 closure->edid,
2152 timing);
2153 break;
2154 case 0x01: /* just the ranges, no formula */
2155 default:
2156 break;
2157 }
2158 }
2159
2160 static int
2161 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2162 {
2163 struct detailed_mode_closure closure = {
2164 .connector = connector,
2165 .edid = edid,
2166 };
2167
2168 if (version_greater(edid, 1, 0))
2169 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2170 &closure);
2171
2172 return closure.modes;
2173 }
2174
2175 static int
2176 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2177 {
2178 int i, j, m, modes = 0;
2179 struct drm_display_mode *mode;
2180 u8 *est = ((u8 *)timing) + 5;
2181
2182 for (i = 0; i < 6; i++) {
2183 for (j = 7; j >= 0; j--) {
2184 m = (i * 8) + (7 - j);
2185 if (m >= ARRAY_SIZE(est3_modes))
2186 break;
2187 if (est[i] & (1 << j)) {
2188 mode = drm_mode_find_dmt(connector->dev,
2189 est3_modes[m].w,
2190 est3_modes[m].h,
2191 est3_modes[m].r,
2192 est3_modes[m].rb);
2193 if (mode) {
2194 drm_mode_probed_add(connector, mode);
2195 modes++;
2196 }
2197 }
2198 }
2199 }
2200
2201 return modes;
2202 }
2203
2204 static void
2205 do_established_modes(struct detailed_timing *timing, void *c)
2206 {
2207 struct detailed_mode_closure *closure = c;
2208 struct detailed_non_pixel *data = &timing->data.other_data;
2209
2210 if (data->type == EDID_DETAIL_EST_TIMINGS)
2211 closure->modes += drm_est3_modes(closure->connector, timing);
2212 }
2213
2214 /**
2215 * add_established_modes - get est. modes from EDID and add them
2216 * @connector: connector to add mode(s) to
2217 * @edid: EDID block to scan
2218 *
2219 * Each EDID block contains a bitmap of the supported "established modes" list
2220 * (defined above). Tease them out and add them to the global modes list.
2221 */
2222 static int
2223 add_established_modes(struct drm_connector *connector, struct edid *edid)
2224 {
2225 struct drm_device *dev = connector->dev;
2226 unsigned long est_bits = edid->established_timings.t1 |
2227 (edid->established_timings.t2 << 8) |
2228 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2229 int i, modes = 0;
2230 struct detailed_mode_closure closure = {
2231 .connector = connector,
2232 .edid = edid,
2233 };
2234
2235 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2236 if (est_bits & (1<<i)) {
2237 struct drm_display_mode *newmode;
2238 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2239 if (newmode) {
2240 drm_mode_probed_add(connector, newmode);
2241 modes++;
2242 }
2243 }
2244 }
2245
2246 if (version_greater(edid, 1, 0))
2247 drm_for_each_detailed_block((u8 *)edid,
2248 do_established_modes, &closure);
2249
2250 return modes + closure.modes;
2251 }
2252
2253 static void
2254 do_standard_modes(struct detailed_timing *timing, void *c)
2255 {
2256 struct detailed_mode_closure *closure = c;
2257 struct detailed_non_pixel *data = &timing->data.other_data;
2258 struct drm_connector *connector = closure->connector;
2259 struct edid *edid = closure->edid;
2260
2261 if (data->type == EDID_DETAIL_STD_MODES) {
2262 int i;
2263 for (i = 0; i < 6; i++) {
2264 struct std_timing *std;
2265 struct drm_display_mode *newmode;
2266
2267 std = &data->data.timings[i];
2268 newmode = drm_mode_std(connector, edid, std);
2269 if (newmode) {
2270 drm_mode_probed_add(connector, newmode);
2271 closure->modes++;
2272 }
2273 }
2274 }
2275 }
2276
2277 /**
2278 * add_standard_modes - get std. modes from EDID and add them
2279 * @connector: connector to add mode(s) to
2280 * @edid: EDID block to scan
2281 *
2282 * Standard modes can be calculated using the appropriate standard (DMT,
2283 * GTF or CVT. Grab them from @edid and add them to the list.
2284 */
2285 static int
2286 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2287 {
2288 int i, modes = 0;
2289 struct detailed_mode_closure closure = {
2290 .connector = connector,
2291 .edid = edid,
2292 };
2293
2294 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2295 struct drm_display_mode *newmode;
2296
2297 newmode = drm_mode_std(connector, edid,
2298 &edid->standard_timings[i]);
2299 if (newmode) {
2300 drm_mode_probed_add(connector, newmode);
2301 modes++;
2302 }
2303 }
2304
2305 if (version_greater(edid, 1, 0))
2306 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2307 &closure);
2308
2309 /* XXX should also look for standard codes in VTB blocks */
2310
2311 return modes + closure.modes;
2312 }
2313
2314 static int drm_cvt_modes(struct drm_connector *connector,
2315 struct detailed_timing *timing)
2316 {
2317 int i, j, modes = 0;
2318 struct drm_display_mode *newmode;
2319 struct drm_device *dev = connector->dev;
2320 struct cvt_timing *cvt;
2321 const int rates[] = { 60, 85, 75, 60, 50 };
2322 const u8 empty[3] = { 0, 0, 0 };
2323
2324 for (i = 0; i < 4; i++) {
2325 int uninitialized_var(width), height;
2326 cvt = &(timing->data.other_data.data.cvt[i]);
2327
2328 if (!memcmp(cvt->code, empty, 3))
2329 continue;
2330
2331 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2332 switch (cvt->code[1] & 0x0c) {
2333 case 0x00:
2334 width = height * 4 / 3;
2335 break;
2336 case 0x04:
2337 width = height * 16 / 9;
2338 break;
2339 case 0x08:
2340 width = height * 16 / 10;
2341 break;
2342 case 0x0c:
2343 width = height * 15 / 9;
2344 break;
2345 }
2346
2347 for (j = 1; j < 5; j++) {
2348 if (cvt->code[2] & (1 << j)) {
2349 newmode = drm_cvt_mode(dev, width, height,
2350 rates[j], j == 0,
2351 false, false);
2352 if (newmode) {
2353 drm_mode_probed_add(connector, newmode);
2354 modes++;
2355 }
2356 }
2357 }
2358 }
2359
2360 return modes;
2361 }
2362
2363 static void
2364 do_cvt_mode(struct detailed_timing *timing, void *c)
2365 {
2366 struct detailed_mode_closure *closure = c;
2367 struct detailed_non_pixel *data = &timing->data.other_data;
2368
2369 if (data->type == EDID_DETAIL_CVT_3BYTE)
2370 closure->modes += drm_cvt_modes(closure->connector, timing);
2371 }
2372
2373 static int
2374 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2375 {
2376 struct detailed_mode_closure closure = {
2377 .connector = connector,
2378 .edid = edid,
2379 };
2380
2381 if (version_greater(edid, 1, 2))
2382 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2383
2384 /* XXX should also look for CVT codes in VTB blocks */
2385
2386 return closure.modes;
2387 }
2388
2389 static void
2390 do_detailed_mode(struct detailed_timing *timing, void *c)
2391 {
2392 struct detailed_mode_closure *closure = c;
2393 struct drm_display_mode *newmode;
2394
2395 if (timing->pixel_clock) {
2396 newmode = drm_mode_detailed(closure->connector->dev,
2397 closure->edid, timing,
2398 closure->quirks);
2399 if (!newmode)
2400 return;
2401
2402 if (closure->preferred)
2403 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2404
2405 drm_mode_probed_add(closure->connector, newmode);
2406 closure->modes++;
2407 closure->preferred = 0;
2408 }
2409 }
2410
2411 /*
2412 * add_detailed_modes - Add modes from detailed timings
2413 * @connector: attached connector
2414 * @edid: EDID block to scan
2415 * @quirks: quirks to apply
2416 */
2417 static int
2418 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2419 u32 quirks)
2420 {
2421 struct detailed_mode_closure closure = {
2422 .connector = connector,
2423 .edid = edid,
2424 .preferred = 1,
2425 .quirks = quirks,
2426 };
2427
2428 if (closure.preferred && !version_greater(edid, 1, 3))
2429 closure.preferred =
2430 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2431
2432 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2433
2434 return closure.modes;
2435 }
2436
2437 #define AUDIO_BLOCK 0x01
2438 #define VIDEO_BLOCK 0x02
2439 #define VENDOR_BLOCK 0x03
2440 #define SPEAKER_BLOCK 0x04
2441 #define VIDEO_CAPABILITY_BLOCK 0x07
2442 #define EDID_BASIC_AUDIO (1 << 6)
2443 #define EDID_CEA_YCRCB444 (1 << 5)
2444 #define EDID_CEA_YCRCB422 (1 << 4)
2445 #define EDID_CEA_VCDB_QS (1 << 6)
2446
2447 /*
2448 * Search EDID for CEA extension block.
2449 */
2450 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
2451 {
2452 u8 *edid_ext = NULL;
2453 int i;
2454
2455 /* No EDID or EDID extensions */
2456 if (edid == NULL || edid->extensions == 0)
2457 return NULL;
2458
2459 /* Find CEA extension */
2460 for (i = 0; i < edid->extensions; i++) {
2461 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2462 if (edid_ext[0] == ext_id)
2463 break;
2464 }
2465
2466 if (i == edid->extensions)
2467 return NULL;
2468
2469 return edid_ext;
2470 }
2471
2472 static u8 *drm_find_cea_extension(struct edid *edid)
2473 {
2474 return drm_find_edid_extension(edid, CEA_EXT);
2475 }
2476
2477 static u8 *drm_find_displayid_extension(struct edid *edid)
2478 {
2479 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2480 }
2481
2482 /*
2483 * Calculate the alternate clock for the CEA mode
2484 * (60Hz vs. 59.94Hz etc.)
2485 */
2486 static unsigned int
2487 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2488 {
2489 unsigned int clock = cea_mode->clock;
2490
2491 if (cea_mode->vrefresh % 6 != 0)
2492 return clock;
2493
2494 /*
2495 * edid_cea_modes contains the 59.94Hz
2496 * variant for 240 and 480 line modes,
2497 * and the 60Hz variant otherwise.
2498 */
2499 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2500 clock = clock * 1001 / 1000;
2501 else
2502 clock = DIV_ROUND_UP(clock * 1000, 1001);
2503
2504 return clock;
2505 }
2506
2507 /**
2508 * drm_match_cea_mode - look for a CEA mode matching given mode
2509 * @to_match: display mode
2510 *
2511 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2512 * mode.
2513 */
2514 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2515 {
2516 u8 mode;
2517
2518 if (!to_match->clock)
2519 return 0;
2520
2521 for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) {
2522 const struct drm_display_mode *cea_mode = &edid_cea_modes[mode];
2523 unsigned int clock1, clock2;
2524
2525 /* Check both 60Hz and 59.94Hz */
2526 clock1 = cea_mode->clock;
2527 clock2 = cea_mode_alternate_clock(cea_mode);
2528
2529 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2530 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2531 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode))
2532 return mode + 1;
2533 }
2534 return 0;
2535 }
2536 EXPORT_SYMBOL(drm_match_cea_mode);
2537
2538 /**
2539 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2540 * the input VIC from the CEA mode list
2541 * @video_code: ID given to each of the CEA modes
2542 *
2543 * Returns picture aspect ratio
2544 */
2545 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2546 {
2547 /* return picture aspect ratio for video_code - 1 to access the
2548 * right array element
2549 */
2550 return edid_cea_modes[video_code-1].picture_aspect_ratio;
2551 }
2552 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2553
2554 /*
2555 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2556 * specific block).
2557 *
2558 * It's almost like cea_mode_alternate_clock(), we just need to add an
2559 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2560 * one.
2561 */
2562 static unsigned int
2563 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2564 {
2565 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2566 return hdmi_mode->clock;
2567
2568 return cea_mode_alternate_clock(hdmi_mode);
2569 }
2570
2571 /*
2572 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2573 * @to_match: display mode
2574 *
2575 * An HDMI mode is one defined in the HDMI vendor specific block.
2576 *
2577 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2578 */
2579 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2580 {
2581 u8 mode;
2582
2583 if (!to_match->clock)
2584 return 0;
2585
2586 for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) {
2587 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode];
2588 unsigned int clock1, clock2;
2589
2590 /* Make sure to also match alternate clocks */
2591 clock1 = hdmi_mode->clock;
2592 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2593
2594 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2595 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2596 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
2597 return mode + 1;
2598 }
2599 return 0;
2600 }
2601
2602 static int
2603 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2604 {
2605 struct drm_device *dev = connector->dev;
2606 struct drm_display_mode *mode, *tmp;
2607 LIST_HEAD(list);
2608 int modes = 0;
2609
2610 /* Don't add CEA modes if the CEA extension block is missing */
2611 if (!drm_find_cea_extension(edid))
2612 return 0;
2613
2614 /*
2615 * Go through all probed modes and create a new mode
2616 * with the alternate clock for certain CEA modes.
2617 */
2618 list_for_each_entry(mode, &connector->probed_modes, head) {
2619 const struct drm_display_mode *cea_mode = NULL;
2620 struct drm_display_mode *newmode;
2621 u8 mode_idx = drm_match_cea_mode(mode) - 1;
2622 unsigned int clock1, clock2;
2623
2624 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) {
2625 cea_mode = &edid_cea_modes[mode_idx];
2626 clock2 = cea_mode_alternate_clock(cea_mode);
2627 } else {
2628 mode_idx = drm_match_hdmi_mode(mode) - 1;
2629 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) {
2630 cea_mode = &edid_4k_modes[mode_idx];
2631 clock2 = hdmi_mode_alternate_clock(cea_mode);
2632 }
2633 }
2634
2635 if (!cea_mode)
2636 continue;
2637
2638 clock1 = cea_mode->clock;
2639
2640 if (clock1 == clock2)
2641 continue;
2642
2643 if (mode->clock != clock1 && mode->clock != clock2)
2644 continue;
2645
2646 newmode = drm_mode_duplicate(dev, cea_mode);
2647 if (!newmode)
2648 continue;
2649
2650 /* Carry over the stereo flags */
2651 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2652
2653 /*
2654 * The current mode could be either variant. Make
2655 * sure to pick the "other" clock for the new mode.
2656 */
2657 if (mode->clock != clock1)
2658 newmode->clock = clock1;
2659 else
2660 newmode->clock = clock2;
2661
2662 list_add_tail(&newmode->head, &list);
2663 }
2664
2665 list_for_each_entry_safe(mode, tmp, &list, head) {
2666 list_del(&mode->head);
2667 drm_mode_probed_add(connector, mode);
2668 modes++;
2669 }
2670
2671 return modes;
2672 }
2673
2674 static struct drm_display_mode *
2675 drm_display_mode_from_vic_index(struct drm_connector *connector,
2676 const u8 *video_db, u8 video_len,
2677 u8 video_index)
2678 {
2679 struct drm_device *dev = connector->dev;
2680 struct drm_display_mode *newmode;
2681 u8 cea_mode;
2682
2683 if (video_db == NULL || video_index >= video_len)
2684 return NULL;
2685
2686 /* CEA modes are numbered 1..127 */
2687 cea_mode = (video_db[video_index] & 127) - 1;
2688 if (cea_mode >= ARRAY_SIZE(edid_cea_modes))
2689 return NULL;
2690
2691 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]);
2692 if (!newmode)
2693 return NULL;
2694
2695 newmode->vrefresh = 0;
2696
2697 return newmode;
2698 }
2699
2700 static int
2701 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
2702 {
2703 int i, modes = 0;
2704
2705 for (i = 0; i < len; i++) {
2706 struct drm_display_mode *mode;
2707 mode = drm_display_mode_from_vic_index(connector, db, len, i);
2708 if (mode) {
2709 drm_mode_probed_add(connector, mode);
2710 modes++;
2711 }
2712 }
2713
2714 return modes;
2715 }
2716
2717 struct stereo_mandatory_mode {
2718 int width, height, vrefresh;
2719 unsigned int flags;
2720 };
2721
2722 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
2723 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2724 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
2725 { 1920, 1080, 50,
2726 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2727 { 1920, 1080, 60,
2728 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2729 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2730 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
2731 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2732 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
2733 };
2734
2735 static bool
2736 stereo_match_mandatory(const struct drm_display_mode *mode,
2737 const struct stereo_mandatory_mode *stereo_mode)
2738 {
2739 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
2740
2741 return mode->hdisplay == stereo_mode->width &&
2742 mode->vdisplay == stereo_mode->height &&
2743 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
2744 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
2745 }
2746
2747 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
2748 {
2749 struct drm_device *dev = connector->dev;
2750 const struct drm_display_mode *mode;
2751 struct list_head stereo_modes;
2752 int modes = 0, i;
2753
2754 INIT_LIST_HEAD(&stereo_modes);
2755
2756 list_for_each_entry(mode, &connector->probed_modes, head) {
2757 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
2758 const struct stereo_mandatory_mode *mandatory;
2759 struct drm_display_mode *new_mode;
2760
2761 if (!stereo_match_mandatory(mode,
2762 &stereo_mandatory_modes[i]))
2763 continue;
2764
2765 mandatory = &stereo_mandatory_modes[i];
2766 new_mode = drm_mode_duplicate(dev, mode);
2767 if (!new_mode)
2768 continue;
2769
2770 new_mode->flags |= mandatory->flags;
2771 list_add_tail(&new_mode->head, &stereo_modes);
2772 modes++;
2773 }
2774 }
2775
2776 list_splice_tail(&stereo_modes, &connector->probed_modes);
2777
2778 return modes;
2779 }
2780
2781 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
2782 {
2783 struct drm_device *dev = connector->dev;
2784 struct drm_display_mode *newmode;
2785
2786 vic--; /* VICs start at 1 */
2787 if (vic >= ARRAY_SIZE(edid_4k_modes)) {
2788 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
2789 return 0;
2790 }
2791
2792 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
2793 if (!newmode)
2794 return 0;
2795
2796 drm_mode_probed_add(connector, newmode);
2797
2798 return 1;
2799 }
2800
2801 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
2802 const u8 *video_db, u8 video_len, u8 video_index)
2803 {
2804 struct drm_display_mode *newmode;
2805 int modes = 0;
2806
2807 if (structure & (1 << 0)) {
2808 newmode = drm_display_mode_from_vic_index(connector, video_db,
2809 video_len,
2810 video_index);
2811 if (newmode) {
2812 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
2813 drm_mode_probed_add(connector, newmode);
2814 modes++;
2815 }
2816 }
2817 if (structure & (1 << 6)) {
2818 newmode = drm_display_mode_from_vic_index(connector, video_db,
2819 video_len,
2820 video_index);
2821 if (newmode) {
2822 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
2823 drm_mode_probed_add(connector, newmode);
2824 modes++;
2825 }
2826 }
2827 if (structure & (1 << 8)) {
2828 newmode = drm_display_mode_from_vic_index(connector, video_db,
2829 video_len,
2830 video_index);
2831 if (newmode) {
2832 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
2833 drm_mode_probed_add(connector, newmode);
2834 modes++;
2835 }
2836 }
2837
2838 return modes;
2839 }
2840
2841 /*
2842 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
2843 * @connector: connector corresponding to the HDMI sink
2844 * @db: start of the CEA vendor specific block
2845 * @len: length of the CEA block payload, ie. one can access up to db[len]
2846 *
2847 * Parses the HDMI VSDB looking for modes to add to @connector. This function
2848 * also adds the stereo 3d modes when applicable.
2849 */
2850 static int
2851 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
2852 const u8 *video_db, u8 video_len)
2853 {
2854 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
2855 u8 vic_len, hdmi_3d_len = 0;
2856 u16 mask;
2857 u16 structure_all;
2858
2859 if (len < 8)
2860 goto out;
2861
2862 /* no HDMI_Video_Present */
2863 if (!(db[8] & (1 << 5)))
2864 goto out;
2865
2866 /* Latency_Fields_Present */
2867 if (db[8] & (1 << 7))
2868 offset += 2;
2869
2870 /* I_Latency_Fields_Present */
2871 if (db[8] & (1 << 6))
2872 offset += 2;
2873
2874 /* the declared length is not long enough for the 2 first bytes
2875 * of additional video format capabilities */
2876 if (len < (8 + offset + 2))
2877 goto out;
2878
2879 /* 3D_Present */
2880 offset++;
2881 if (db[8 + offset] & (1 << 7)) {
2882 modes += add_hdmi_mandatory_stereo_modes(connector);
2883
2884 /* 3D_Multi_present */
2885 multi_present = (db[8 + offset] & 0x60) >> 5;
2886 }
2887
2888 offset++;
2889 vic_len = db[8 + offset] >> 5;
2890 hdmi_3d_len = db[8 + offset] & 0x1f;
2891
2892 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
2893 u8 vic;
2894
2895 vic = db[9 + offset + i];
2896 modes += add_hdmi_mode(connector, vic);
2897 }
2898 offset += 1 + vic_len;
2899
2900 if (multi_present == 1)
2901 multi_len = 2;
2902 else if (multi_present == 2)
2903 multi_len = 4;
2904 else
2905 multi_len = 0;
2906
2907 if (len < (8 + offset + hdmi_3d_len - 1))
2908 goto out;
2909
2910 if (hdmi_3d_len < multi_len)
2911 goto out;
2912
2913 if (multi_present == 1 || multi_present == 2) {
2914 /* 3D_Structure_ALL */
2915 structure_all = (db[8 + offset] << 8) | db[9 + offset];
2916
2917 /* check if 3D_MASK is present */
2918 if (multi_present == 2)
2919 mask = (db[10 + offset] << 8) | db[11 + offset];
2920 else
2921 mask = 0xffff;
2922
2923 for (i = 0; i < 16; i++) {
2924 if (mask & (1 << i))
2925 modes += add_3d_struct_modes(connector,
2926 structure_all,
2927 video_db,
2928 video_len, i);
2929 }
2930 }
2931
2932 offset += multi_len;
2933
2934 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
2935 int vic_index;
2936 struct drm_display_mode *newmode = NULL;
2937 unsigned int newflag = 0;
2938 bool detail_present;
2939
2940 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
2941
2942 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
2943 break;
2944
2945 /* 2D_VIC_order_X */
2946 vic_index = db[8 + offset + i] >> 4;
2947
2948 /* 3D_Structure_X */
2949 switch (db[8 + offset + i] & 0x0f) {
2950 case 0:
2951 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
2952 break;
2953 case 6:
2954 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
2955 break;
2956 case 8:
2957 /* 3D_Detail_X */
2958 if ((db[9 + offset + i] >> 4) == 1)
2959 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
2960 break;
2961 }
2962
2963 if (newflag != 0) {
2964 newmode = drm_display_mode_from_vic_index(connector,
2965 video_db,
2966 video_len,
2967 vic_index);
2968
2969 if (newmode) {
2970 newmode->flags |= newflag;
2971 drm_mode_probed_add(connector, newmode);
2972 modes++;
2973 }
2974 }
2975
2976 if (detail_present)
2977 i++;
2978 }
2979
2980 out:
2981 return modes;
2982 }
2983
2984 static int
2985 cea_db_payload_len(const u8 *db)
2986 {
2987 return db[0] & 0x1f;
2988 }
2989
2990 static int
2991 cea_db_tag(const u8 *db)
2992 {
2993 return db[0] >> 5;
2994 }
2995
2996 static int
2997 cea_revision(const u8 *cea)
2998 {
2999 return cea[1];
3000 }
3001
3002 static int
3003 cea_db_offsets(const u8 *cea, int *start, int *end)
3004 {
3005 /* Data block offset in CEA extension block */
3006 *start = 4;
3007 *end = cea[2];
3008 if (*end == 0)
3009 *end = 127;
3010 if (*end < 4 || *end > 127)
3011 return -ERANGE;
3012 return 0;
3013 }
3014
3015 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3016 {
3017 int hdmi_id;
3018
3019 if (cea_db_tag(db) != VENDOR_BLOCK)
3020 return false;
3021
3022 if (cea_db_payload_len(db) < 5)
3023 return false;
3024
3025 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3026
3027 return hdmi_id == HDMI_IEEE_OUI;
3028 }
3029
3030 #define for_each_cea_db(cea, i, start, end) \
3031 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3032
3033 static int
3034 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3035 {
3036 const u8 *cea = drm_find_cea_extension(edid);
3037 const u8 *db, *hdmi = NULL, *video = NULL;
3038 u8 dbl, hdmi_len, video_len = 0;
3039 int modes = 0;
3040
3041 if (cea && cea_revision(cea) >= 3) {
3042 int i, start, end;
3043
3044 if (cea_db_offsets(cea, &start, &end))
3045 return 0;
3046
3047 for_each_cea_db(cea, i, start, end) {
3048 db = &cea[i];
3049 dbl = cea_db_payload_len(db);
3050
3051 if (cea_db_tag(db) == VIDEO_BLOCK) {
3052 video = db + 1;
3053 video_len = dbl;
3054 modes += do_cea_modes(connector, video, dbl);
3055 }
3056 else if (cea_db_is_hdmi_vsdb(db)) {
3057 hdmi = db;
3058 hdmi_len = dbl;
3059 }
3060 }
3061 }
3062
3063 /*
3064 * We parse the HDMI VSDB after having added the cea modes as we will
3065 * be patching their flags when the sink supports stereo 3D.
3066 */
3067 if (hdmi)
3068 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3069 video_len);
3070
3071 return modes;
3072 }
3073
3074 static void
3075 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db)
3076 {
3077 u8 len = cea_db_payload_len(db);
3078
3079 if (len >= 6) {
3080 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3081 connector->dvi_dual = db[6] & 1;
3082 }
3083 if (len >= 7)
3084 connector->max_tmds_clock = db[7] * 5;
3085 if (len >= 8) {
3086 connector->latency_present[0] = db[8] >> 7;
3087 connector->latency_present[1] = (db[8] >> 6) & 1;
3088 }
3089 if (len >= 9)
3090 connector->video_latency[0] = db[9];
3091 if (len >= 10)
3092 connector->audio_latency[0] = db[10];
3093 if (len >= 11)
3094 connector->video_latency[1] = db[11];
3095 if (len >= 12)
3096 connector->audio_latency[1] = db[12];
3097
3098 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
3099 "max TMDS clock %d, "
3100 "latency present %d %d, "
3101 "video latency %d %d, "
3102 "audio latency %d %d\n",
3103 connector->dvi_dual,
3104 connector->max_tmds_clock,
3105 (int) connector->latency_present[0],
3106 (int) connector->latency_present[1],
3107 connector->video_latency[0],
3108 connector->video_latency[1],
3109 connector->audio_latency[0],
3110 connector->audio_latency[1]);
3111 }
3112
3113 static void
3114 monitor_name(struct detailed_timing *t, void *data)
3115 {
3116 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3117 *(u8 **)data = t->data.other_data.data.str.str;
3118 }
3119
3120 /**
3121 * drm_edid_to_eld - build ELD from EDID
3122 * @connector: connector corresponding to the HDMI/DP sink
3123 * @edid: EDID to parse
3124 *
3125 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3126 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3127 * fill in.
3128 */
3129 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3130 {
3131 uint8_t *eld = connector->eld;
3132 u8 *cea;
3133 u8 *name;
3134 u8 *db;
3135 int sad_count = 0;
3136 int mnl;
3137 int dbl;
3138
3139 memset(eld, 0, sizeof(connector->eld));
3140
3141 cea = drm_find_cea_extension(edid);
3142 if (!cea) {
3143 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3144 return;
3145 }
3146
3147 name = NULL;
3148 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name);
3149 for (mnl = 0; name && mnl < 13; mnl++) {
3150 if (name[mnl] == 0x0a)
3151 break;
3152 eld[20 + mnl] = name[mnl];
3153 }
3154 eld[4] = (cea[1] << 5) | mnl;
3155 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3156
3157 eld[0] = 2 << 3; /* ELD version: 2 */
3158
3159 eld[16] = edid->mfg_id[0];
3160 eld[17] = edid->mfg_id[1];
3161 eld[18] = edid->prod_code[0];
3162 eld[19] = edid->prod_code[1];
3163
3164 if (cea_revision(cea) >= 3) {
3165 int i, start, end;
3166
3167 if (cea_db_offsets(cea, &start, &end)) {
3168 start = 0;
3169 end = 0;
3170 }
3171
3172 for_each_cea_db(cea, i, start, end) {
3173 db = &cea[i];
3174 dbl = cea_db_payload_len(db);
3175
3176 switch (cea_db_tag(db)) {
3177 case AUDIO_BLOCK:
3178 /* Audio Data Block, contains SADs */
3179 sad_count = dbl / 3;
3180 if (dbl >= 1)
3181 memcpy(eld + 20 + mnl, &db[1], dbl);
3182 break;
3183 case SPEAKER_BLOCK:
3184 /* Speaker Allocation Data Block */
3185 if (dbl >= 1)
3186 eld[7] = db[1];
3187 break;
3188 case VENDOR_BLOCK:
3189 /* HDMI Vendor-Specific Data Block */
3190 if (cea_db_is_hdmi_vsdb(db))
3191 parse_hdmi_vsdb(connector, db);
3192 break;
3193 default:
3194 break;
3195 }
3196 }
3197 }
3198 eld[5] |= sad_count << 4;
3199
3200 eld[DRM_ELD_BASELINE_ELD_LEN] =
3201 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3202
3203 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3204 drm_eld_size(eld), sad_count);
3205 }
3206 EXPORT_SYMBOL(drm_edid_to_eld);
3207
3208 /**
3209 * drm_edid_to_sad - extracts SADs from EDID
3210 * @edid: EDID to parse
3211 * @sads: pointer that will be set to the extracted SADs
3212 *
3213 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3214 *
3215 * Note: The returned pointer needs to be freed using kfree().
3216 *
3217 * Return: The number of found SADs or negative number on error.
3218 */
3219 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3220 {
3221 int count = 0;
3222 int i, start, end, dbl;
3223 u8 *cea;
3224
3225 cea = drm_find_cea_extension(edid);
3226 if (!cea) {
3227 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3228 return -ENOENT;
3229 }
3230
3231 if (cea_revision(cea) < 3) {
3232 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3233 return -ENOTSUPP;
3234 }
3235
3236 if (cea_db_offsets(cea, &start, &end)) {
3237 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3238 return -EPROTO;
3239 }
3240
3241 for_each_cea_db(cea, i, start, end) {
3242 u8 *db = &cea[i];
3243
3244 if (cea_db_tag(db) == AUDIO_BLOCK) {
3245 int j;
3246 dbl = cea_db_payload_len(db);
3247
3248 count = dbl / 3; /* SAD is 3B */
3249 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3250 if (!*sads)
3251 return -ENOMEM;
3252 for (j = 0; j < count; j++) {
3253 u8 *sad = &db[1 + j * 3];
3254
3255 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3256 (*sads)[j].channels = sad[0] & 0x7;
3257 (*sads)[j].freq = sad[1] & 0x7F;
3258 (*sads)[j].byte2 = sad[2];
3259 }
3260 break;
3261 }
3262 }
3263
3264 return count;
3265 }
3266 EXPORT_SYMBOL(drm_edid_to_sad);
3267
3268 /**
3269 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3270 * @edid: EDID to parse
3271 * @sadb: pointer to the speaker block
3272 *
3273 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3274 *
3275 * Note: The returned pointer needs to be freed using kfree().
3276 *
3277 * Return: The number of found Speaker Allocation Blocks or negative number on
3278 * error.
3279 */
3280 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3281 {
3282 int count = 0;
3283 int i, start, end, dbl;
3284 const u8 *cea;
3285
3286 cea = drm_find_cea_extension(edid);
3287 if (!cea) {
3288 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3289 return -ENOENT;
3290 }
3291
3292 if (cea_revision(cea) < 3) {
3293 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3294 return -ENOTSUPP;
3295 }
3296
3297 if (cea_db_offsets(cea, &start, &end)) {
3298 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3299 return -EPROTO;
3300 }
3301
3302 for_each_cea_db(cea, i, start, end) {
3303 const u8 *db = &cea[i];
3304
3305 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3306 dbl = cea_db_payload_len(db);
3307
3308 /* Speaker Allocation Data Block */
3309 if (dbl == 3) {
3310 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
3311 if (!*sadb)
3312 return -ENOMEM;
3313 count = dbl;
3314 break;
3315 }
3316 }
3317 }
3318
3319 return count;
3320 }
3321 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3322
3323 /**
3324 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
3325 * @connector: connector associated with the HDMI/DP sink
3326 * @mode: the display mode
3327 *
3328 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3329 * the sink doesn't support audio or video.
3330 */
3331 int drm_av_sync_delay(struct drm_connector *connector,
3332 struct drm_display_mode *mode)
3333 {
3334 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3335 int a, v;
3336
3337 if (!connector->latency_present[0])
3338 return 0;
3339 if (!connector->latency_present[1])
3340 i = 0;
3341
3342 a = connector->audio_latency[i];
3343 v = connector->video_latency[i];
3344
3345 /*
3346 * HDMI/DP sink doesn't support audio or video?
3347 */
3348 if (a == 255 || v == 255)
3349 return 0;
3350
3351 /*
3352 * Convert raw EDID values to millisecond.
3353 * Treat unknown latency as 0ms.
3354 */
3355 if (a)
3356 a = min(2 * (a - 1), 500);
3357 if (v)
3358 v = min(2 * (v - 1), 500);
3359
3360 return max(v - a, 0);
3361 }
3362 EXPORT_SYMBOL(drm_av_sync_delay);
3363
3364 /**
3365 * drm_select_eld - select one ELD from multiple HDMI/DP sinks
3366 * @encoder: the encoder just changed display mode
3367 * @mode: the adjusted display mode
3368 *
3369 * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
3370 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
3371 *
3372 * Return: The connector associated with the first HDMI/DP sink that has ELD
3373 * attached to it.
3374 */
3375 struct drm_connector *drm_select_eld(struct drm_encoder *encoder,
3376 struct drm_display_mode *mode)
3377 {
3378 struct drm_connector *connector;
3379 struct drm_device *dev = encoder->dev;
3380
3381 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
3382 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3383
3384 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
3385 if (connector->encoder == encoder && connector->eld[0])
3386 return connector;
3387
3388 return NULL;
3389 }
3390 EXPORT_SYMBOL(drm_select_eld);
3391
3392 /**
3393 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
3394 * @edid: monitor EDID information
3395 *
3396 * Parse the CEA extension according to CEA-861-B.
3397 *
3398 * Return: True if the monitor is HDMI, false if not or unknown.
3399 */
3400 bool drm_detect_hdmi_monitor(struct edid *edid)
3401 {
3402 u8 *edid_ext;
3403 int i;
3404 int start_offset, end_offset;
3405
3406 edid_ext = drm_find_cea_extension(edid);
3407 if (!edid_ext)
3408 return false;
3409
3410 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3411 return false;
3412
3413 /*
3414 * Because HDMI identifier is in Vendor Specific Block,
3415 * search it from all data blocks of CEA extension.
3416 */
3417 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3418 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3419 return true;
3420 }
3421
3422 return false;
3423 }
3424 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3425
3426 /**
3427 * drm_detect_monitor_audio - check monitor audio capability
3428 * @edid: EDID block to scan
3429 *
3430 * Monitor should have CEA extension block.
3431 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3432 * audio' only. If there is any audio extension block and supported
3433 * audio format, assume at least 'basic audio' support, even if 'basic
3434 * audio' is not defined in EDID.
3435 *
3436 * Return: True if the monitor supports audio, false otherwise.
3437 */
3438 bool drm_detect_monitor_audio(struct edid *edid)
3439 {
3440 u8 *edid_ext;
3441 int i, j;
3442 bool has_audio = false;
3443 int start_offset, end_offset;
3444
3445 edid_ext = drm_find_cea_extension(edid);
3446 if (!edid_ext)
3447 goto end;
3448
3449 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3450
3451 if (has_audio) {
3452 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3453 goto end;
3454 }
3455
3456 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3457 goto end;
3458
3459 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3460 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
3461 has_audio = true;
3462 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
3463 DRM_DEBUG_KMS("CEA audio format %d\n",
3464 (edid_ext[i + j] >> 3) & 0xf);
3465 goto end;
3466 }
3467 }
3468 end:
3469 return has_audio;
3470 }
3471 EXPORT_SYMBOL(drm_detect_monitor_audio);
3472
3473 /**
3474 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
3475 * @edid: EDID block to scan
3476 *
3477 * Check whether the monitor reports the RGB quantization range selection
3478 * as supported. The AVI infoframe can then be used to inform the monitor
3479 * which quantization range (full or limited) is used.
3480 *
3481 * Return: True if the RGB quantization range is selectable, false otherwise.
3482 */
3483 bool drm_rgb_quant_range_selectable(struct edid *edid)
3484 {
3485 u8 *edid_ext;
3486 int i, start, end;
3487
3488 edid_ext = drm_find_cea_extension(edid);
3489 if (!edid_ext)
3490 return false;
3491
3492 if (cea_db_offsets(edid_ext, &start, &end))
3493 return false;
3494
3495 for_each_cea_db(edid_ext, i, start, end) {
3496 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
3497 cea_db_payload_len(&edid_ext[i]) == 2) {
3498 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
3499 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
3500 }
3501 }
3502
3503 return false;
3504 }
3505 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
3506
3507 /**
3508 * drm_assign_hdmi_deep_color_info - detect whether monitor supports
3509 * hdmi deep color modes and update drm_display_info if so.
3510 * @edid: monitor EDID information
3511 * @info: Updated with maximum supported deep color bpc and color format
3512 * if deep color supported.
3513 * @connector: DRM connector, used only for debug output
3514 *
3515 * Parse the CEA extension according to CEA-861-B.
3516 * Return true if HDMI deep color supported, false if not or unknown.
3517 */
3518 static bool drm_assign_hdmi_deep_color_info(struct edid *edid,
3519 struct drm_display_info *info,
3520 struct drm_connector *connector)
3521 {
3522 u8 *edid_ext, *hdmi;
3523 int i;
3524 int start_offset, end_offset;
3525 unsigned int dc_bpc = 0;
3526
3527 edid_ext = drm_find_cea_extension(edid);
3528 if (!edid_ext)
3529 return false;
3530
3531 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3532 return false;
3533
3534 /*
3535 * Because HDMI identifier is in Vendor Specific Block,
3536 * search it from all data blocks of CEA extension.
3537 */
3538 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3539 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) {
3540 /* HDMI supports at least 8 bpc */
3541 info->bpc = 8;
3542
3543 hdmi = &edid_ext[i];
3544 if (cea_db_payload_len(hdmi) < 6)
3545 return false;
3546
3547 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
3548 dc_bpc = 10;
3549 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
3550 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
3551 connector->name);
3552 }
3553
3554 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
3555 dc_bpc = 12;
3556 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
3557 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
3558 connector->name);
3559 }
3560
3561 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
3562 dc_bpc = 16;
3563 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
3564 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
3565 connector->name);
3566 }
3567
3568 if (dc_bpc > 0) {
3569 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
3570 connector->name, dc_bpc);
3571 info->bpc = dc_bpc;
3572
3573 /*
3574 * Deep color support mandates RGB444 support for all video
3575 * modes and forbids YCRCB422 support for all video modes per
3576 * HDMI 1.3 spec.
3577 */
3578 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3579
3580 /* YCRCB444 is optional according to spec. */
3581 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
3582 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3583 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
3584 connector->name);
3585 }
3586
3587 /*
3588 * Spec says that if any deep color mode is supported at all,
3589 * then deep color 36 bit must be supported.
3590 */
3591 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
3592 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
3593 connector->name);
3594 }
3595
3596 return true;
3597 }
3598 else {
3599 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
3600 connector->name);
3601 }
3602 }
3603 }
3604
3605 return false;
3606 }
3607
3608 /**
3609 * drm_add_display_info - pull display info out if present
3610 * @edid: EDID data
3611 * @info: display info (attached to connector)
3612 * @connector: connector whose edid is used to build display info
3613 *
3614 * Grab any available display info and stuff it into the drm_display_info
3615 * structure that's part of the connector. Useful for tracking bpp and
3616 * color spaces.
3617 */
3618 static void drm_add_display_info(struct edid *edid,
3619 struct drm_display_info *info,
3620 struct drm_connector *connector)
3621 {
3622 u8 *edid_ext;
3623
3624 info->width_mm = edid->width_cm * 10;
3625 info->height_mm = edid->height_cm * 10;
3626
3627 /* driver figures it out in this case */
3628 info->bpc = 0;
3629 info->color_formats = 0;
3630
3631 if (edid->revision < 3)
3632 return;
3633
3634 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
3635 return;
3636
3637 /* Get data from CEA blocks if present */
3638 edid_ext = drm_find_cea_extension(edid);
3639 if (edid_ext) {
3640 info->cea_rev = edid_ext[1];
3641
3642 /* The existence of a CEA block should imply RGB support */
3643 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3644 if (edid_ext[3] & EDID_CEA_YCRCB444)
3645 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3646 if (edid_ext[3] & EDID_CEA_YCRCB422)
3647 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3648 }
3649
3650 /* HDMI deep color modes supported? Assign to info, if so */
3651 drm_assign_hdmi_deep_color_info(edid, info, connector);
3652
3653 /* Only defined for 1.4 with digital displays */
3654 if (edid->revision < 4)
3655 return;
3656
3657 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
3658 case DRM_EDID_DIGITAL_DEPTH_6:
3659 info->bpc = 6;
3660 break;
3661 case DRM_EDID_DIGITAL_DEPTH_8:
3662 info->bpc = 8;
3663 break;
3664 case DRM_EDID_DIGITAL_DEPTH_10:
3665 info->bpc = 10;
3666 break;
3667 case DRM_EDID_DIGITAL_DEPTH_12:
3668 info->bpc = 12;
3669 break;
3670 case DRM_EDID_DIGITAL_DEPTH_14:
3671 info->bpc = 14;
3672 break;
3673 case DRM_EDID_DIGITAL_DEPTH_16:
3674 info->bpc = 16;
3675 break;
3676 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
3677 default:
3678 info->bpc = 0;
3679 break;
3680 }
3681
3682 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
3683 connector->name, info->bpc);
3684
3685 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
3686 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
3687 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3688 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
3689 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3690 }
3691
3692 /**
3693 * drm_add_edid_modes - add modes from EDID data, if available
3694 * @connector: connector we're probing
3695 * @edid: EDID data
3696 *
3697 * Add the specified modes to the connector's mode list.
3698 *
3699 * Return: The number of modes added or 0 if we couldn't find any.
3700 */
3701 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
3702 {
3703 int num_modes = 0;
3704 u32 quirks;
3705
3706 if (edid == NULL) {
3707 return 0;
3708 }
3709 if (!drm_edid_is_valid(edid)) {
3710 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
3711 connector->name);
3712 return 0;
3713 }
3714
3715 quirks = edid_get_quirks(edid);
3716
3717 /*
3718 * EDID spec says modes should be preferred in this order:
3719 * - preferred detailed mode
3720 * - other detailed modes from base block
3721 * - detailed modes from extension blocks
3722 * - CVT 3-byte code modes
3723 * - standard timing codes
3724 * - established timing codes
3725 * - modes inferred from GTF or CVT range information
3726 *
3727 * We get this pretty much right.
3728 *
3729 * XXX order for additional mode types in extension blocks?
3730 */
3731 num_modes += add_detailed_modes(connector, edid, quirks);
3732 num_modes += add_cvt_modes(connector, edid);
3733 num_modes += add_standard_modes(connector, edid);
3734 num_modes += add_established_modes(connector, edid);
3735 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
3736 num_modes += add_inferred_modes(connector, edid);
3737 num_modes += add_cea_modes(connector, edid);
3738 num_modes += add_alternate_cea_modes(connector, edid);
3739
3740 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
3741 edid_fixup_preferred(connector, quirks);
3742
3743 drm_add_display_info(edid, &connector->display_info, connector);
3744
3745 if (quirks & EDID_QUIRK_FORCE_8BPC)
3746 connector->display_info.bpc = 8;
3747
3748 if (quirks & EDID_QUIRK_FORCE_12BPC)
3749 connector->display_info.bpc = 12;
3750
3751 return num_modes;
3752 }
3753 EXPORT_SYMBOL(drm_add_edid_modes);
3754
3755 /**
3756 * drm_add_modes_noedid - add modes for the connectors without EDID
3757 * @connector: connector we're probing
3758 * @hdisplay: the horizontal display limit
3759 * @vdisplay: the vertical display limit
3760 *
3761 * Add the specified modes to the connector's mode list. Only when the
3762 * hdisplay/vdisplay is not beyond the given limit, it will be added.
3763 *
3764 * Return: The number of modes added or 0 if we couldn't find any.
3765 */
3766 int drm_add_modes_noedid(struct drm_connector *connector,
3767 int hdisplay, int vdisplay)
3768 {
3769 int i, count, num_modes = 0;
3770 struct drm_display_mode *mode;
3771 struct drm_device *dev = connector->dev;
3772
3773 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
3774 if (hdisplay < 0)
3775 hdisplay = 0;
3776 if (vdisplay < 0)
3777 vdisplay = 0;
3778
3779 for (i = 0; i < count; i++) {
3780 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
3781 if (hdisplay && vdisplay) {
3782 /*
3783 * Only when two are valid, they will be used to check
3784 * whether the mode should be added to the mode list of
3785 * the connector.
3786 */
3787 if (ptr->hdisplay > hdisplay ||
3788 ptr->vdisplay > vdisplay)
3789 continue;
3790 }
3791 if (drm_mode_vrefresh(ptr) > 61)
3792 continue;
3793 mode = drm_mode_duplicate(dev, ptr);
3794 if (mode) {
3795 drm_mode_probed_add(connector, mode);
3796 num_modes++;
3797 }
3798 }
3799 return num_modes;
3800 }
3801 EXPORT_SYMBOL(drm_add_modes_noedid);
3802
3803 /**
3804 * drm_set_preferred_mode - Sets the preferred mode of a connector
3805 * @connector: connector whose mode list should be processed
3806 * @hpref: horizontal resolution of preferred mode
3807 * @vpref: vertical resolution of preferred mode
3808 *
3809 * Marks a mode as preferred if it matches the resolution specified by @hpref
3810 * and @vpref.
3811 */
3812 void drm_set_preferred_mode(struct drm_connector *connector,
3813 int hpref, int vpref)
3814 {
3815 struct drm_display_mode *mode;
3816
3817 list_for_each_entry(mode, &connector->probed_modes, head) {
3818 if (mode->hdisplay == hpref &&
3819 mode->vdisplay == vpref)
3820 mode->type |= DRM_MODE_TYPE_PREFERRED;
3821 }
3822 }
3823 EXPORT_SYMBOL(drm_set_preferred_mode);
3824
3825 /**
3826 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
3827 * data from a DRM display mode
3828 * @frame: HDMI AVI infoframe
3829 * @mode: DRM display mode
3830 *
3831 * Return: 0 on success or a negative error code on failure.
3832 */
3833 int
3834 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
3835 const struct drm_display_mode *mode)
3836 {
3837 int err;
3838
3839 if (!frame || !mode)
3840 return -EINVAL;
3841
3842 err = hdmi_avi_infoframe_init(frame);
3843 if (err < 0)
3844 return err;
3845
3846 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
3847 frame->pixel_repeat = 1;
3848
3849 frame->video_code = drm_match_cea_mode(mode);
3850
3851 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
3852
3853 /*
3854 * Populate picture aspect ratio from either
3855 * user input (if specified) or from the CEA mode list.
3856 */
3857 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
3858 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
3859 frame->picture_aspect = mode->picture_aspect_ratio;
3860 else if (frame->video_code > 0)
3861 frame->picture_aspect = drm_get_cea_aspect_ratio(
3862 frame->video_code);
3863
3864 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
3865 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
3866
3867 return 0;
3868 }
3869 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
3870
3871 static enum hdmi_3d_structure
3872 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
3873 {
3874 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
3875
3876 switch (layout) {
3877 case DRM_MODE_FLAG_3D_FRAME_PACKING:
3878 return HDMI_3D_STRUCTURE_FRAME_PACKING;
3879 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
3880 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
3881 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
3882 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
3883 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
3884 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
3885 case DRM_MODE_FLAG_3D_L_DEPTH:
3886 return HDMI_3D_STRUCTURE_L_DEPTH;
3887 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
3888 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
3889 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
3890 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
3891 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
3892 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
3893 default:
3894 return HDMI_3D_STRUCTURE_INVALID;
3895 }
3896 }
3897
3898 /**
3899 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
3900 * data from a DRM display mode
3901 * @frame: HDMI vendor infoframe
3902 * @mode: DRM display mode
3903 *
3904 * Note that there's is a need to send HDMI vendor infoframes only when using a
3905 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
3906 * function will return -EINVAL, error that can be safely ignored.
3907 *
3908 * Return: 0 on success or a negative error code on failure.
3909 */
3910 int
3911 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
3912 const struct drm_display_mode *mode)
3913 {
3914 int err;
3915 u32 s3d_flags;
3916 u8 vic;
3917
3918 if (!frame || !mode)
3919 return -EINVAL;
3920
3921 vic = drm_match_hdmi_mode(mode);
3922 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
3923
3924 if (!vic && !s3d_flags)
3925 return -EINVAL;
3926
3927 if (vic && s3d_flags)
3928 return -EINVAL;
3929
3930 err = hdmi_vendor_infoframe_init(frame);
3931 if (err < 0)
3932 return err;
3933
3934 if (vic)
3935 frame->vic = vic;
3936 else
3937 frame->s3d_struct = s3d_structure_from_display_mode(mode);
3938
3939 return 0;
3940 }
3941 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
3942
3943 static int drm_parse_display_id(struct drm_connector *connector,
3944 u8 *displayid, int length,
3945 bool is_edid_extension)
3946 {
3947 /* if this is an EDID extension the first byte will be 0x70 */
3948 int idx = 0;
3949 struct displayid_hdr *base;
3950 struct displayid_block *block;
3951 u8 csum = 0;
3952 int i;
3953
3954 if (is_edid_extension)
3955 idx = 1;
3956
3957 base = (struct displayid_hdr *)&displayid[idx];
3958
3959 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
3960 base->rev, base->bytes, base->prod_id, base->ext_count);
3961
3962 if (base->bytes + 5 > length - idx)
3963 return -EINVAL;
3964
3965 for (i = idx; i <= base->bytes + 5; i++) {
3966 csum += displayid[i];
3967 }
3968 if (csum) {
3969 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum);
3970 return -EINVAL;
3971 }
3972
3973 block = (struct displayid_block *)&displayid[idx + 4];
3974 DRM_DEBUG_KMS("block id %d, rev %d, len %d\n",
3975 block->tag, block->rev, block->num_bytes);
3976
3977 switch (block->tag) {
3978 case DATA_BLOCK_TILED_DISPLAY: {
3979 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
3980
3981 u16 w, h;
3982 u8 tile_v_loc, tile_h_loc;
3983 u8 num_v_tile, num_h_tile;
3984 struct drm_tile_group *tg;
3985
3986 w = tile->tile_size[0] | tile->tile_size[1] << 8;
3987 h = tile->tile_size[2] | tile->tile_size[3] << 8;
3988
3989 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
3990 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
3991 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
3992 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
3993
3994 connector->has_tile = true;
3995 if (tile->tile_cap & 0x80)
3996 connector->tile_is_single_monitor = true;
3997
3998 connector->num_h_tile = num_h_tile + 1;
3999 connector->num_v_tile = num_v_tile + 1;
4000 connector->tile_h_loc = tile_h_loc;
4001 connector->tile_v_loc = tile_v_loc;
4002 connector->tile_h_size = w + 1;
4003 connector->tile_v_size = h + 1;
4004
4005 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
4006 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
4007 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4008 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
4009 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
4010
4011 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
4012 if (!tg) {
4013 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
4014 }
4015 if (!tg)
4016 return -ENOMEM;
4017
4018 if (connector->tile_group != tg) {
4019 /* if we haven't got a pointer,
4020 take the reference, drop ref to old tile group */
4021 if (connector->tile_group) {
4022 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4023 }
4024 connector->tile_group = tg;
4025 } else
4026 /* if same tile group, then release the ref we just took. */
4027 drm_mode_put_tile_group(connector->dev, tg);
4028 }
4029 break;
4030 default:
4031 printk("unknown displayid tag %d\n", block->tag);
4032 break;
4033 }
4034 return 0;
4035 }
4036
4037 static void drm_get_displayid(struct drm_connector *connector,
4038 struct edid *edid)
4039 {
4040 void *displayid = NULL;
4041 int ret;
4042 connector->has_tile = false;
4043 displayid = drm_find_displayid_extension(edid);
4044 if (!displayid) {
4045 /* drop reference to any tile group we had */
4046 goto out_drop_ref;
4047 }
4048
4049 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
4050 if (ret < 0)
4051 goto out_drop_ref;
4052 if (!connector->has_tile)
4053 goto out_drop_ref;
4054 return;
4055 out_drop_ref:
4056 if (connector->tile_group) {
4057 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4058 connector->tile_group = NULL;
4059 }
4060 return;
4061 }
Linux with added FPC-III support