drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c

   1 /*
   2  * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include "mdp5_kms.h"
  15 #include "mdp5_cfg.h"
  16
  17 struct mdp5_cfg_handler {
  18         int revision;
  19         struct mdp5_cfg config;
  20 };
  21
  22 /* mdp5_cfg must be exposed (used in mdp5.xml.h) */
  23 const struct mdp5_cfg_hw *mdp5_cfg = NULL;
  24
  25 const struct mdp5_cfg_hw msm8x74_config = {
  26         .name = "msm8x74",
  27         .mdp = {
  28                 .count = 1,
  29                 .base = { 0x00100 },
  30         },
  31         .smp = {
  32                 .mmb_count = 22,
  33                 .mmb_size = 4096,
  34                 .clients = {
  35                         [SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
  36                         [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
  37                         [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
  38                 },
  39         },
  40         .ctl = {
  41                 .count = 5,
  42                 .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
  43                 .flush_hw_mask = 0x0003ffff,
  44         },
  45         .pipe_vig = {
  46                 .count = 3,
  47                 .base = { 0x01200, 0x01600, 0x01a00 },
  48         },
  49         .pipe_rgb = {
  50                 .count = 3,
  51                 .base = { 0x01e00, 0x02200, 0x02600 },
  52         },
  53         .pipe_dma = {
  54                 .count = 2,
  55                 .base = { 0x02a00, 0x02e00 },
  56         },
  57         .lm = {
  58                 .count = 5,
  59                 .base = { 0x03200, 0x03600, 0x03a00, 0x03e00, 0x04200 },
  60                 .nb_stages = 5,
  61         },
  62         .dspp = {
  63                 .count = 3,
  64                 .base = { 0x04600, 0x04a00, 0x04e00 },
  65         },
  66         .ad = {
  67                 .count = 2,
  68                 .base = { 0x13100, 0x13300 }, /* NOTE: no ad in v1.0 */
  69         },
  70         .pp = {
  71                 .count = 3,
  72                 .base = { 0x12d00, 0x12e00, 0x12f00 },
  73         },
  74         .intf = {
  75                 .count = 4,
  76                 .base = { 0x12500, 0x12700, 0x12900, 0x12b00 },
  77         },
  78         .intfs = {
  79                 [0] = INTF_eDP,
  80                 [1] = INTF_DSI,
  81                 [2] = INTF_DSI,
  82                 [3] = INTF_HDMI,
  83         },
  84         .max_clk = 200000000,
  85 };
  86
  87 const struct mdp5_cfg_hw apq8084_config = {
  88         .name = "apq8084",
  89         .mdp = {
  90                 .count = 1,
  91                 .base = { 0x00100 },
  92         },
  93         .smp = {
  94                 .mmb_count = 44,
  95                 .mmb_size = 8192,
  96                 .clients = {
  97                         [SSPP_VIG0] =  1, [SSPP_VIG1] =  4,
  98                         [SSPP_VIG2] =  7, [SSPP_VIG3] = 19,
  99                         [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
 100                         [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
 101                         [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
 102                 },
 103                 .reserved_state[0] = GENMASK(7, 0),     /* first 8 MMBs */
 104                 .reserved = {
 105                         /* Two SMP blocks are statically tied to RGB pipes: */
 106                         [16] = 2, [17] = 2, [18] = 2, [22] = 2,
 107                 },
 108         },
 109         .ctl = {
 110                 .count = 5,
 111                 .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
 112                 .flush_hw_mask = 0x003fffff,
 113         },
 114         .pipe_vig = {
 115                 .count = 4,
 116                 .base = { 0x01200, 0x01600, 0x01a00, 0x01e00 },
 117         },
 118         .pipe_rgb = {
 119                 .count = 4,
 120                 .base = { 0x02200, 0x02600, 0x02a00, 0x02e00 },
 121         },
 122         .pipe_dma = {
 123                 .count = 2,
 124                 .base = { 0x03200, 0x03600 },
 125         },
 126         .lm = {
 127                 .count = 6,
 128                 .base = { 0x03a00, 0x03e00, 0x04200, 0x04600, 0x04a00, 0x04e00 },
 129                 .nb_stages = 5,
 130         },
 131         .dspp = {
 132                 .count = 4,
 133                 .base = { 0x05200, 0x05600, 0x05a00, 0x05e00 },
 134
 135         },
 136         .ad = {
 137                 .count = 3,
 138                 .base = { 0x13500, 0x13700, 0x13900 },
 139         },
 140         .pp = {
 141                 .count = 4,
 142                 .base = { 0x12f00, 0x13000, 0x13100, 0x13200 },
 143         },
 144         .intf = {
 145                 .count = 5,
 146                 .base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 },
 147         },
 148         .intfs = {
 149                 [0] = INTF_eDP,
 150                 [1] = INTF_DSI,
 151                 [2] = INTF_DSI,
 152                 [3] = INTF_HDMI,
 153         },
 154         .max_clk = 320000000,
 155 };
 156
 157 const struct mdp5_cfg_hw msm8x16_config = {
 158         .name = "msm8x16",
 159         .mdp = {
 160                 .count = 1,
 161                 .base = { 0x01000 },
 162         },
 163         .smp = {
 164                 .mmb_count = 8,
 165                 .mmb_size = 8192,
 166                 .clients = {
 167                         [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
 168                         [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
 169                 },
 170         },
 171         .ctl = {
 172                 .count = 5,
 173                 .base = { 0x02000, 0x02200, 0x02400, 0x02600, 0x02800 },
 174                 .flush_hw_mask = 0x4003ffff,
 175         },
 176         .pipe_vig = {
 177                 .count = 1,
 178                 .base = { 0x05000 },
 179         },
 180         .pipe_rgb = {
 181                 .count = 2,
 182                 .base = { 0x15000, 0x17000 },
 183         },
 184         .pipe_dma = {
 185                 .count = 1,
 186                 .base = { 0x25000 },
 187         },
 188         .lm = {
 189                 .count = 2, /* LM0 and LM3 */
 190                 .base = { 0x45000, 0x48000 },
 191                 .nb_stages = 5,
 192         },
 193         .dspp = {
 194                 .count = 1,
 195                 .base = { 0x55000 },
 196
 197         },
 198         .intf = {
 199                 .count = 1, /* INTF_1 */
 200                 .base = { 0x6B800 },
 201         },
 202         /* TODO enable .intfs[] with [1] = INTF_DSI, once DSI is implemented */
 203         .max_clk = 320000000,
 204 };
 205
 206 static const struct mdp5_cfg_handler cfg_handlers[] = {
 207         { .revision = 0, .config = { .hw = &msm8x74_config } },
 208         { .revision = 2, .config = { .hw = &msm8x74_config } },
 209         { .revision = 3, .config = { .hw = &apq8084_config } },
 210         { .revision = 6, .config = { .hw = &msm8x16_config } },
 211 };
 212
 213
 214 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev);
 215
 216 const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
 217 {
 218         return cfg_handler->config.hw;
 219 }
 220
 221 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler)
 222 {
 223         return &cfg_handler->config;
 224 }
 225
 226 int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)
 227 {
 228         return cfg_handler->revision;
 229 }
 230
 231 void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler)
 232 {
 233         kfree(cfg_handler);
 234 }
 235
 236 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
 237                 uint32_t major, uint32_t minor)
 238 {
 239         struct drm_device *dev = mdp5_kms->dev;
 240         struct platform_device *pdev = dev->platformdev;
 241         struct mdp5_cfg_handler *cfg_handler;
 242         struct mdp5_cfg_platform *pconfig;
 243         int i, ret = 0;
 244
 245         cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
 246         if (unlikely(!cfg_handler)) {
 247                 ret = -ENOMEM;
 248                 goto fail;
 249         }
 250
 251         if (major != 1) {
 252                 dev_err(dev->dev, "unexpected MDP major version: v%d.%d\n",
 253                                 major, minor);
 254                 ret = -ENXIO;
 255                 goto fail;
 256         }
 257
 258         /* only after mdp5_cfg global pointer's init can we access the hw */
 259         for (i = 0; i < ARRAY_SIZE(cfg_handlers); i++) {
 260                 if (cfg_handlers[i].revision != minor)
 261                         continue;
 262                 mdp5_cfg = cfg_handlers[i].config.hw;
 263
 264                 break;
 265         }
 266         if (unlikely(!mdp5_cfg)) {
 267                 dev_err(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
 268                                 major, minor);
 269                 ret = -ENXIO;
 270                 goto fail;
 271         }
 272
 273         cfg_handler->revision = minor;
 274         cfg_handler->config.hw = mdp5_cfg;
 275
 276         pconfig = mdp5_get_config(pdev);
 277         memcpy(&cfg_handler->config.platform, pconfig, sizeof(*pconfig));
 278
 279         DBG("MDP5: %s hw config selected", mdp5_cfg->name);
 280
 281         return cfg_handler;
 282
 283 fail:
 284         if (cfg_handler)
 285                 mdp5_cfg_destroy(cfg_handler);
 286
 287         return NULL;
 288 }
 289
 290 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev)
 291 {
 292         static struct mdp5_cfg_platform config = {};
 293 #ifdef CONFIG_OF
 294         /* TODO */
 295 #endif
 296         config.iommu = iommu_domain_alloc(&platform_bus_type);
 297
 298         return &config;
 299 }