drm/amdkfd: Add memory exception handling
[linux/fpc-iii.git] / drivers / gpu / drm / msm / mdp / mdp5 / mdp5_ctl.h
blob7a62000994a16fc906ee919d4e2ad65860f6b944
1 /*
2 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #ifndef __MDP5_CTL_H__
15 #define __MDP5_CTL_H__
17 #include "msm_drv.h"
20 * CTL Manager prototypes:
21 * mdp5_ctlm_init() returns a ctlm (CTL Manager) handler,
22 * which is then used to call the other mdp5_ctlm_*(ctlm, ...) functions.
24 struct mdp5_ctl_manager;
25 struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,
26 void __iomem *mmio_base, const struct mdp5_cfg_hw *hw_cfg);
27 void mdp5_ctlm_hw_reset(struct mdp5_ctl_manager *ctlm);
28 void mdp5_ctlm_destroy(struct mdp5_ctl_manager *ctlm);
31 * CTL prototypes:
32 * mdp5_ctl_request(ctlm, ...) returns a ctl (CTL resource) handler,
33 * which is then used to call the other mdp5_ctl_*(ctl, ...) functions.
35 struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctlm, struct drm_crtc *crtc);
36 int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl);
38 struct mdp5_interface;
39 int mdp5_ctl_set_intf(struct mdp5_ctl *ctl, struct mdp5_interface *intf);
40 int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, bool enabled);
42 int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, int cursor_id, bool enable);
45 * blend_cfg (LM blender config):
47 * The function below allows the caller of mdp5_ctl_blend() to specify how pipes
48 * are being blended according to their stage (z-order), through @blend_cfg arg.
50 static inline u32 mdp_ctl_blend_mask(enum mdp5_pipe pipe,
51 enum mdp_mixer_stage_id stage)
53 switch (pipe) {
54 case SSPP_VIG0: return MDP5_CTL_LAYER_REG_VIG0(stage);
55 case SSPP_VIG1: return MDP5_CTL_LAYER_REG_VIG1(stage);
56 case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage);
57 case SSPP_RGB0: return MDP5_CTL_LAYER_REG_RGB0(stage);
58 case SSPP_RGB1: return MDP5_CTL_LAYER_REG_RGB1(stage);
59 case SSPP_RGB2: return MDP5_CTL_LAYER_REG_RGB2(stage);
60 case SSPP_DMA0: return MDP5_CTL_LAYER_REG_DMA0(stage);
61 case SSPP_DMA1: return MDP5_CTL_LAYER_REG_DMA1(stage);
62 case SSPP_VIG3: return MDP5_CTL_LAYER_REG_VIG3(stage);
63 case SSPP_RGB3: return MDP5_CTL_LAYER_REG_RGB3(stage);
64 default: return 0;
69 * mdp5_ctl_blend() - Blend multiple layers on a Layer Mixer (LM)
71 * @blend_cfg: see LM blender config definition below
73 * Note:
74 * CTL registers need to be flushed after calling this function
75 * (call mdp5_ctl_commit() with mdp_ctl_flush_mask_ctl() mask)
77 int mdp5_ctl_blend(struct mdp5_ctl *ctl, u32 lm, u32 blend_cfg);
79 /**
80 * mdp_ctl_flush_mask...() - Register FLUSH masks
82 * These masks are used to specify which block(s) need to be flushed
83 * through @flush_mask parameter in mdp5_ctl_commit(.., flush_mask).
85 u32 mdp_ctl_flush_mask_lm(int lm);
86 u32 mdp_ctl_flush_mask_pipe(enum mdp5_pipe pipe);
87 u32 mdp_ctl_flush_mask_cursor(int cursor_id);
88 u32 mdp_ctl_flush_mask_encoder(struct mdp5_interface *intf);
90 /* @flush_mask: see CTL flush masks definitions below */
91 int mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask);
93 void mdp5_ctl_release(struct mdp5_ctl *ctl);
97 #endif /* __MDP5_CTL_H__ */