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arm: Add devicetree fixup machine function
[linux/fpc-iii.git] / drivers / mtd / nand / fsl_ifc_nand.c
blob2338124dd05f54fb002966666041a15eb72f0dd0
1 /*
2 * Freescale Integrated Flash Controller NAND driver
3 *
4 * Copyright 2011-2012 Freescale Semiconductor, Inc
5 *
6 * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/of_address.h>
27 #include <linux/slab.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/nand.h>
30 #include <linux/mtd/partitions.h>
31 #include <linux/mtd/nand_ecc.h>
32 #include <linux/fsl_ifc.h>
33
34 #define FSL_IFC_V1_1_0 0x01010000
35 #define ERR_BYTE 0xFF /* Value returned for read
36 bytes when read failed */
37 #define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait
38 for IFC NAND Machine */
39
40 struct fsl_ifc_ctrl;
41
42 /* mtd information per set */
43 struct fsl_ifc_mtd {
44 struct mtd_info mtd;
45 struct nand_chip chip;
46 struct fsl_ifc_ctrl *ctrl;
47
48 struct device *dev;
49 int bank; /* Chip select bank number */
50 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
51 u8 __iomem *vbase; /* Chip select base virtual address */
52 };
53
54 /* overview of the fsl ifc controller */
55 struct fsl_ifc_nand_ctrl {
56 struct nand_hw_control controller;
57 struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
58
59 void __iomem *addr; /* Address of assigned IFC buffer */
60 unsigned int page; /* Last page written to / read from */
61 unsigned int read_bytes;/* Number of bytes read during command */
62 unsigned int column; /* Saved column from SEQIN */
63 unsigned int index; /* Pointer to next byte to 'read' */
64 unsigned int oob; /* Non zero if operating on OOB data */
65 unsigned int eccread; /* Non zero for a full-page ECC read */
66 unsigned int counter; /* counter for the initializations */
67 unsigned int max_bitflips; /* Saved during READ0 cmd */
68 };
69
70 static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
71
72 /* 512-byte page with 4-bit ECC, 8-bit */
73 static struct nand_ecclayout oob_512_8bit_ecc4 = {
74 .eccbytes = 8,
75 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
76 .oobfree = { {0, 5}, {6, 2} },
77 };
78
79 /* 512-byte page with 4-bit ECC, 16-bit */
80 static struct nand_ecclayout oob_512_16bit_ecc4 = {
81 .eccbytes = 8,
82 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
83 .oobfree = { {2, 6}, },
84 };
85
86 /* 2048-byte page size with 4-bit ECC */
87 static struct nand_ecclayout oob_2048_ecc4 = {
88 .eccbytes = 32,
89 .eccpos = {
90 8, 9, 10, 11, 12, 13, 14, 15,
91 16, 17, 18, 19, 20, 21, 22, 23,
92 24, 25, 26, 27, 28, 29, 30, 31,
93 32, 33, 34, 35, 36, 37, 38, 39,
94 },
95 .oobfree = { {2, 6}, {40, 24} },
96 };
97
98 /* 4096-byte page size with 4-bit ECC */
99 static struct nand_ecclayout oob_4096_ecc4 = {
100 .eccbytes = 64,
101 .eccpos = {
102 8, 9, 10, 11, 12, 13, 14, 15,
103 16, 17, 18, 19, 20, 21, 22, 23,
104 24, 25, 26, 27, 28, 29, 30, 31,
105 32, 33, 34, 35, 36, 37, 38, 39,
106 40, 41, 42, 43, 44, 45, 46, 47,
107 48, 49, 50, 51, 52, 53, 54, 55,
108 56, 57, 58, 59, 60, 61, 62, 63,
109 64, 65, 66, 67, 68, 69, 70, 71,
110 },
111 .oobfree = { {2, 6}, {72, 56} },
112 };
113
114 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
115 static struct nand_ecclayout oob_4096_ecc8 = {
116 .eccbytes = 128,
117 .eccpos = {
118 8, 9, 10, 11, 12, 13, 14, 15,
119 16, 17, 18, 19, 20, 21, 22, 23,
120 24, 25, 26, 27, 28, 29, 30, 31,
121 32, 33, 34, 35, 36, 37, 38, 39,
122 40, 41, 42, 43, 44, 45, 46, 47,
123 48, 49, 50, 51, 52, 53, 54, 55,
124 56, 57, 58, 59, 60, 61, 62, 63,
125 64, 65, 66, 67, 68, 69, 70, 71,
126 72, 73, 74, 75, 76, 77, 78, 79,
127 80, 81, 82, 83, 84, 85, 86, 87,
128 88, 89, 90, 91, 92, 93, 94, 95,
129 96, 97, 98, 99, 100, 101, 102, 103,
130 104, 105, 106, 107, 108, 109, 110, 111,
131 112, 113, 114, 115, 116, 117, 118, 119,
132 120, 121, 122, 123, 124, 125, 126, 127,
133 128, 129, 130, 131, 132, 133, 134, 135,
134 },
135 .oobfree = { {2, 6}, {136, 82} },
136 };
137
138 /* 8192-byte page size with 4-bit ECC */
139 static struct nand_ecclayout oob_8192_ecc4 = {
140 .eccbytes = 128,
141 .eccpos = {
142 8, 9, 10, 11, 12, 13, 14, 15,
143 16, 17, 18, 19, 20, 21, 22, 23,
144 24, 25, 26, 27, 28, 29, 30, 31,
145 32, 33, 34, 35, 36, 37, 38, 39,
146 40, 41, 42, 43, 44, 45, 46, 47,
147 48, 49, 50, 51, 52, 53, 54, 55,
148 56, 57, 58, 59, 60, 61, 62, 63,
149 64, 65, 66, 67, 68, 69, 70, 71,
150 72, 73, 74, 75, 76, 77, 78, 79,
151 80, 81, 82, 83, 84, 85, 86, 87,
152 88, 89, 90, 91, 92, 93, 94, 95,
153 96, 97, 98, 99, 100, 101, 102, 103,
154 104, 105, 106, 107, 108, 109, 110, 111,
155 112, 113, 114, 115, 116, 117, 118, 119,
156 120, 121, 122, 123, 124, 125, 126, 127,
157 128, 129, 130, 131, 132, 133, 134, 135,
158 },
159 .oobfree = { {2, 6}, {136, 208} },
160 };
161
162 /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
163 static struct nand_ecclayout oob_8192_ecc8 = {
164 .eccbytes = 256,
165 .eccpos = {
166 8, 9, 10, 11, 12, 13, 14, 15,
167 16, 17, 18, 19, 20, 21, 22, 23,
168 24, 25, 26, 27, 28, 29, 30, 31,
169 32, 33, 34, 35, 36, 37, 38, 39,
170 40, 41, 42, 43, 44, 45, 46, 47,
171 48, 49, 50, 51, 52, 53, 54, 55,
172 56, 57, 58, 59, 60, 61, 62, 63,
173 64, 65, 66, 67, 68, 69, 70, 71,
174 72, 73, 74, 75, 76, 77, 78, 79,
175 80, 81, 82, 83, 84, 85, 86, 87,
176 88, 89, 90, 91, 92, 93, 94, 95,
177 96, 97, 98, 99, 100, 101, 102, 103,
178 104, 105, 106, 107, 108, 109, 110, 111,
179 112, 113, 114, 115, 116, 117, 118, 119,
180 120, 121, 122, 123, 124, 125, 126, 127,
181 128, 129, 130, 131, 132, 133, 134, 135,
182 136, 137, 138, 139, 140, 141, 142, 143,
183 144, 145, 146, 147, 148, 149, 150, 151,
184 152, 153, 154, 155, 156, 157, 158, 159,
185 160, 161, 162, 163, 164, 165, 166, 167,
186 168, 169, 170, 171, 172, 173, 174, 175,
187 176, 177, 178, 179, 180, 181, 182, 183,
188 184, 185, 186, 187, 188, 189, 190, 191,
189 192, 193, 194, 195, 196, 197, 198, 199,
190 200, 201, 202, 203, 204, 205, 206, 207,
191 208, 209, 210, 211, 212, 213, 214, 215,
192 216, 217, 218, 219, 220, 221, 222, 223,
193 224, 225, 226, 227, 228, 229, 230, 231,
194 232, 233, 234, 235, 236, 237, 238, 239,
195 240, 241, 242, 243, 244, 245, 246, 247,
196 248, 249, 250, 251, 252, 253, 254, 255,
197 256, 257, 258, 259, 260, 261, 262, 263,
198 },
199 .oobfree = { {2, 6}, {264, 80} },
200 };
201
202 /*
203 * Generic flash bbt descriptors
204 */
205 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
206 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
207
208 static struct nand_bbt_descr bbt_main_descr = {
209 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
210 NAND_BBT_2BIT | NAND_BBT_VERSION,
211 .offs = 2, /* 0 on 8-bit small page */
212 .len = 4,
213 .veroffs = 6,
214 .maxblocks = 4,
215 .pattern = bbt_pattern,
216 };
217
218 static struct nand_bbt_descr bbt_mirror_descr = {
219 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
220 NAND_BBT_2BIT | NAND_BBT_VERSION,
221 .offs = 2, /* 0 on 8-bit small page */
222 .len = 4,
223 .veroffs = 6,
224 .maxblocks = 4,
225 .pattern = mirror_pattern,
226 };
227
228 /*
229 * Set up the IFC hardware block and page address fields, and the ifc nand
230 * structure addr field to point to the correct IFC buffer in memory
231 */
232 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
233 {
234 struct nand_chip *chip = mtd->priv;
235 struct fsl_ifc_mtd *priv = chip->priv;
236 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
237 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
238 int buf_num;
239
240 ifc_nand_ctrl->page = page_addr;
241 /* Program ROW0/COL0 */
242 iowrite32be(page_addr, &ifc->ifc_nand.row0);
243 iowrite32be((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
244
245 buf_num = page_addr & priv->bufnum_mask;
246
247 ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
248 ifc_nand_ctrl->index = column;
249
250 /* for OOB data point to the second half of the buffer */
251 if (oob)
252 ifc_nand_ctrl->index += mtd->writesize;
253 }
254
255 static int is_blank(struct mtd_info *mtd, unsigned int bufnum)
256 {
257 struct nand_chip *chip = mtd->priv;
258 struct fsl_ifc_mtd *priv = chip->priv;
259 u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
260 u32 __iomem *mainarea = (u32 __iomem *)addr;
261 u8 __iomem *oob = addr + mtd->writesize;
262 int i;
263
264 for (i = 0; i < mtd->writesize / 4; i++) {
265 if (__raw_readl(&mainarea[i]) != 0xffffffff)
266 return 0;
267 }
268
269 for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
270 int pos = chip->ecc.layout->eccpos[i];
271
272 if (__raw_readb(&oob[pos]) != 0xff)
273 return 0;
274 }
275
276 return 1;
277 }
278
279 /* returns nonzero if entire page is blank */
280 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
281 u32 *eccstat, unsigned int bufnum)
282 {
283 u32 reg = eccstat[bufnum / 4];
284 int errors;
285
286 errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
287
288 return errors;
289 }
290
291 /*
292 * execute IFC NAND command and wait for it to complete
293 */
294 static void fsl_ifc_run_command(struct mtd_info *mtd)
295 {
296 struct nand_chip *chip = mtd->priv;
297 struct fsl_ifc_mtd *priv = chip->priv;
298 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
299 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
300 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
301 u32 eccstat[4];
302 int i;
303
304 /* set the chip select for NAND Transaction */
305 iowrite32be(priv->bank << IFC_NAND_CSEL_SHIFT,
306 &ifc->ifc_nand.nand_csel);
307
308 dev_vdbg(priv->dev,
309 "%s: fir0=%08x fcr0=%08x\n",
310 __func__,
311 ioread32be(&ifc->ifc_nand.nand_fir0),
312 ioread32be(&ifc->ifc_nand.nand_fcr0));
313
314 ctrl->nand_stat = 0;
315
316 /* start read/write seq */
317 iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
318
319 /* wait for command complete flag or timeout */
320 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
321 IFC_TIMEOUT_MSECS * HZ/1000);
322
323 /* ctrl->nand_stat will be updated from IRQ context */
324 if (!ctrl->nand_stat)
325 dev_err(priv->dev, "Controller is not responding\n");
326 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
327 dev_err(priv->dev, "NAND Flash Timeout Error\n");
328 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
329 dev_err(priv->dev, "NAND Flash Write Protect Error\n");
330
331 nctrl->max_bitflips = 0;
332
333 if (nctrl->eccread) {
334 int errors;
335 int bufnum = nctrl->page & priv->bufnum_mask;
336 int sector = bufnum * chip->ecc.steps;
337 int sector_end = sector + chip->ecc.steps - 1;
338
339 for (i = sector / 4; i <= sector_end / 4; i++)
340 eccstat[i] = ioread32be(&ifc->ifc_nand.nand_eccstat[i]);
341
342 for (i = sector; i <= sector_end; i++) {
343 errors = check_read_ecc(mtd, ctrl, eccstat, i);
344
345 if (errors == 15) {
346 /*
347 * Uncorrectable error.
348 * OK only if the whole page is blank.
349 *
350 * We disable ECCER reporting due to...
351 * erratum IFC-A002770 -- so report it now if we
352 * see an uncorrectable error in ECCSTAT.
353 */
354 if (!is_blank(mtd, bufnum))
355 ctrl->nand_stat |=
356 IFC_NAND_EVTER_STAT_ECCER;
357 break;
358 }
359
360 mtd->ecc_stats.corrected += errors;
361 nctrl->max_bitflips = max_t(unsigned int,
362 nctrl->max_bitflips,
363 errors);
364 }
365
366 nctrl->eccread = 0;
367 }
368 }
369
370 static void fsl_ifc_do_read(struct nand_chip *chip,
371 int oob,
372 struct mtd_info *mtd)
373 {
374 struct fsl_ifc_mtd *priv = chip->priv;
375 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
376 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
377
378 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
379 if (mtd->writesize > 512) {
380 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
381 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
382 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
383 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
384 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
385 &ifc->ifc_nand.nand_fir0);
386 iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
387
388 iowrite32be((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
389 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
390 &ifc->ifc_nand.nand_fcr0);
391 } else {
392 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
393 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
394 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
395 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
396 &ifc->ifc_nand.nand_fir0);
397 iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
398
399 if (oob)
400 iowrite32be(NAND_CMD_READOOB <<
401 IFC_NAND_FCR0_CMD0_SHIFT,
402 &ifc->ifc_nand.nand_fcr0);
403 else
404 iowrite32be(NAND_CMD_READ0 <<
405 IFC_NAND_FCR0_CMD0_SHIFT,
406 &ifc->ifc_nand.nand_fcr0);
407 }
408 }
409
410 /* cmdfunc send commands to the IFC NAND Machine */
411 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
412 int column, int page_addr) {
413 struct nand_chip *chip = mtd->priv;
414 struct fsl_ifc_mtd *priv = chip->priv;
415 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
416 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
417
418 /* clear the read buffer */
419 ifc_nand_ctrl->read_bytes = 0;
420 if (command != NAND_CMD_PAGEPROG)
421 ifc_nand_ctrl->index = 0;
422
423 switch (command) {
424 /* READ0 read the entire buffer to use hardware ECC. */
425 case NAND_CMD_READ0:
426 iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
427 set_addr(mtd, 0, page_addr, 0);
428
429 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
430 ifc_nand_ctrl->index += column;
431
432 if (chip->ecc.mode == NAND_ECC_HW)
433 ifc_nand_ctrl->eccread = 1;
434
435 fsl_ifc_do_read(chip, 0, mtd);
436 fsl_ifc_run_command(mtd);
437 return;
438
439 /* READOOB reads only the OOB because no ECC is performed. */
440 case NAND_CMD_READOOB:
441 iowrite32be(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
442 set_addr(mtd, column, page_addr, 1);
443
444 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
445
446 fsl_ifc_do_read(chip, 1, mtd);
447 fsl_ifc_run_command(mtd);
448
449 return;
450
451 case NAND_CMD_READID:
452 case NAND_CMD_PARAM: {
453 int timing = IFC_FIR_OP_RB;
454 if (command == NAND_CMD_PARAM)
455 timing = IFC_FIR_OP_RBCD;
456
457 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
458 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
459 (timing << IFC_NAND_FIR0_OP2_SHIFT),
460 &ifc->ifc_nand.nand_fir0);
461 iowrite32be(command << IFC_NAND_FCR0_CMD0_SHIFT,
462 &ifc->ifc_nand.nand_fcr0);
463 iowrite32be(column, &ifc->ifc_nand.row3);
464
465 /*
466 * although currently it's 8 bytes for READID, we always read
467 * the maximum 256 bytes(for PARAM)
468 */
469 iowrite32be(256, &ifc->ifc_nand.nand_fbcr);
470 ifc_nand_ctrl->read_bytes = 256;
471
472 set_addr(mtd, 0, 0, 0);
473 fsl_ifc_run_command(mtd);
474 return;
475 }
476
477 /* ERASE1 stores the block and page address */
478 case NAND_CMD_ERASE1:
479 set_addr(mtd, 0, page_addr, 0);
480 return;
481
482 /* ERASE2 uses the block and page address from ERASE1 */
483 case NAND_CMD_ERASE2:
484 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
485 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
486 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
487 &ifc->ifc_nand.nand_fir0);
488
489 iowrite32be((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
490 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
491 &ifc->ifc_nand.nand_fcr0);
492
493 iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
494 ifc_nand_ctrl->read_bytes = 0;
495 fsl_ifc_run_command(mtd);
496 return;
497
498 /* SEQIN sets up the addr buffer and all registers except the length */
499 case NAND_CMD_SEQIN: {
500 u32 nand_fcr0;
501 ifc_nand_ctrl->column = column;
502 ifc_nand_ctrl->oob = 0;
503
504 if (mtd->writesize > 512) {
505 nand_fcr0 =
506 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
507 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
508 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
509
510 iowrite32be(
511 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
512 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
513 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
514 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
515 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
516 &ifc->ifc_nand.nand_fir0);
517 iowrite32be(
518 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
519 (IFC_FIR_OP_RDSTAT <<
520 IFC_NAND_FIR1_OP6_SHIFT) |
521 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
522 &ifc->ifc_nand.nand_fir1);
523 } else {
524 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
525 IFC_NAND_FCR0_CMD1_SHIFT) |
526 (NAND_CMD_SEQIN <<
527 IFC_NAND_FCR0_CMD2_SHIFT) |
528 (NAND_CMD_STATUS <<
529 IFC_NAND_FCR0_CMD3_SHIFT));
530
531 iowrite32be(
532 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
533 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
534 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
535 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
536 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
537 &ifc->ifc_nand.nand_fir0);
538 iowrite32be(
539 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
540 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
541 (IFC_FIR_OP_RDSTAT <<
542 IFC_NAND_FIR1_OP7_SHIFT) |
543 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
544 &ifc->ifc_nand.nand_fir1);
545
546 if (column >= mtd->writesize)
547 nand_fcr0 |=
548 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
549 else
550 nand_fcr0 |=
551 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
552 }
553
554 if (column >= mtd->writesize) {
555 /* OOB area --> READOOB */
556 column -= mtd->writesize;
557 ifc_nand_ctrl->oob = 1;
558 }
559 iowrite32be(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
560 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
561 return;
562 }
563
564 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
565 case NAND_CMD_PAGEPROG: {
566 if (ifc_nand_ctrl->oob) {
567 iowrite32be(ifc_nand_ctrl->index -
568 ifc_nand_ctrl->column,
569 &ifc->ifc_nand.nand_fbcr);
570 } else {
571 iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
572 }
573
574 fsl_ifc_run_command(mtd);
575 return;
576 }
577
578 case NAND_CMD_STATUS:
579 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
580 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
581 &ifc->ifc_nand.nand_fir0);
582 iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
583 &ifc->ifc_nand.nand_fcr0);
584 iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
585 set_addr(mtd, 0, 0, 0);
586 ifc_nand_ctrl->read_bytes = 1;
587
588 fsl_ifc_run_command(mtd);
589
590 /*
591 * The chip always seems to report that it is
592 * write-protected, even when it is not.
593 */
594 if (chip->options & NAND_BUSWIDTH_16)
595 setbits16(ifc_nand_ctrl->addr, NAND_STATUS_WP);
596 else
597 setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP);
598 return;
599
600 case NAND_CMD_RESET:
601 iowrite32be(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
602 &ifc->ifc_nand.nand_fir0);
603 iowrite32be(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
604 &ifc->ifc_nand.nand_fcr0);
605 fsl_ifc_run_command(mtd);
606 return;
607
608 default:
609 dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
610 __func__, command);
611 }
612 }
613
614 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
615 {
616 /* The hardware does not seem to support multiple
617 * chips per bank.
618 */
619 }
620
621 /*
622 * Write buf to the IFC NAND Controller Data Buffer
623 */
624 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
625 {
626 struct nand_chip *chip = mtd->priv;
627 struct fsl_ifc_mtd *priv = chip->priv;
628 unsigned int bufsize = mtd->writesize + mtd->oobsize;
629
630 if (len <= 0) {
631 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
632 return;
633 }
634
635 if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
636 dev_err(priv->dev,
637 "%s: beyond end of buffer (%d requested, %u available)\n",
638 __func__, len, bufsize - ifc_nand_ctrl->index);
639 len = bufsize - ifc_nand_ctrl->index;
640 }
641
642 memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len);
643 ifc_nand_ctrl->index += len;
644 }
645
646 /*
647 * Read a byte from either the IFC hardware buffer
648 * read function for 8-bit buswidth
649 */
650 static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
651 {
652 struct nand_chip *chip = mtd->priv;
653 struct fsl_ifc_mtd *priv = chip->priv;
654 unsigned int offset;
655
656 /*
657 * If there are still bytes in the IFC buffer, then use the
658 * next byte.
659 */
660 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
661 offset = ifc_nand_ctrl->index++;
662 return in_8(ifc_nand_ctrl->addr + offset);
663 }
664
665 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
666 return ERR_BYTE;
667 }
668
669 /*
670 * Read two bytes from the IFC hardware buffer
671 * read function for 16-bit buswith
672 */
673 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
674 {
675 struct nand_chip *chip = mtd->priv;
676 struct fsl_ifc_mtd *priv = chip->priv;
677 uint16_t data;
678
679 /*
680 * If there are still bytes in the IFC buffer, then use the
681 * next byte.
682 */
683 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
684 data = in_be16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
685 ifc_nand_ctrl->index += 2;
686 return (uint8_t) data;
687 }
688
689 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
690 return ERR_BYTE;
691 }
692
693 /*
694 * Read from the IFC Controller Data Buffer
695 */
696 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
697 {
698 struct nand_chip *chip = mtd->priv;
699 struct fsl_ifc_mtd *priv = chip->priv;
700 int avail;
701
702 if (len < 0) {
703 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
704 return;
705 }
706
707 avail = min((unsigned int)len,
708 ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
709 memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail);
710 ifc_nand_ctrl->index += avail;
711
712 if (len > avail)
713 dev_err(priv->dev,
714 "%s: beyond end of buffer (%d requested, %d available)\n",
715 __func__, len, avail);
716 }
717
718 /*
719 * This function is called after Program and Erase Operations to
720 * check for success or failure.
721 */
722 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
723 {
724 struct fsl_ifc_mtd *priv = chip->priv;
725 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
726 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
727 u32 nand_fsr;
728
729 /* Use READ_STATUS command, but wait for the device to be ready */
730 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
731 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
732 &ifc->ifc_nand.nand_fir0);
733 iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
734 &ifc->ifc_nand.nand_fcr0);
735 iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
736 set_addr(mtd, 0, 0, 0);
737 ifc_nand_ctrl->read_bytes = 1;
738
739 fsl_ifc_run_command(mtd);
740
741 nand_fsr = ioread32be(&ifc->ifc_nand.nand_fsr);
742
743 /*
744 * The chip always seems to report that it is
745 * write-protected, even when it is not.
746 */
747 return nand_fsr | NAND_STATUS_WP;
748 }
749
750 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
751 uint8_t *buf, int oob_required, int page)
752 {
753 struct fsl_ifc_mtd *priv = chip->priv;
754 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
755 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
756
757 fsl_ifc_read_buf(mtd, buf, mtd->writesize);
758 if (oob_required)
759 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
760
761 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER)
762 dev_err(priv->dev, "NAND Flash ECC Uncorrectable Error\n");
763
764 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
765 mtd->ecc_stats.failed++;
766
767 return nctrl->max_bitflips;
768 }
769
770 /* ECC will be calculated automatically, and errors will be detected in
771 * waitfunc.
772 */
773 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
774 const uint8_t *buf, int oob_required)
775 {
776 fsl_ifc_write_buf(mtd, buf, mtd->writesize);
777 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
778
779 return 0;
780 }
781
782 static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
783 {
784 struct nand_chip *chip = mtd->priv;
785 struct fsl_ifc_mtd *priv = chip->priv;
786
787 dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
788 chip->numchips);
789 dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
790 chip->chipsize);
791 dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
792 chip->pagemask);
793 dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
794 chip->chip_delay);
795 dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
796 chip->badblockpos);
797 dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
798 chip->chip_shift);
799 dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
800 chip->page_shift);
801 dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
802 chip->phys_erase_shift);
803 dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
804 chip->ecc.mode);
805 dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
806 chip->ecc.steps);
807 dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
808 chip->ecc.bytes);
809 dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
810 chip->ecc.total);
811 dev_dbg(priv->dev, "%s: nand->ecc.layout = %p\n", __func__,
812 chip->ecc.layout);
813 dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
814 dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
815 dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
816 mtd->erasesize);
817 dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
818 mtd->writesize);
819 dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
820 mtd->oobsize);
821
822 return 0;
823 }
824
825 static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
826 {
827 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
828 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
829 uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
830 uint32_t cs = priv->bank;
831
832 /* Save CSOR and CSOR_ext */
833 csor = ioread32be(&ifc->csor_cs[cs].csor);
834 csor_ext = ioread32be(&ifc->csor_cs[cs].csor_ext);
835
836 /* chage PageSize 8K and SpareSize 1K*/
837 csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
838 iowrite32be(csor_8k, &ifc->csor_cs[cs].csor);
839 iowrite32be(0x0000400, &ifc->csor_cs[cs].csor_ext);
840
841 /* READID */
842 iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
843 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
844 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
845 &ifc->ifc_nand.nand_fir0);
846 iowrite32be(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
847 &ifc->ifc_nand.nand_fcr0);
848 iowrite32be(0x0, &ifc->ifc_nand.row3);
849
850 iowrite32be(0x0, &ifc->ifc_nand.nand_fbcr);
851
852 /* Program ROW0/COL0 */
853 iowrite32be(0x0, &ifc->ifc_nand.row0);
854 iowrite32be(0x0, &ifc->ifc_nand.col0);
855
856 /* set the chip select for NAND Transaction */
857 iowrite32be(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel);
858
859 /* start read seq */
860 iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
861
862 /* wait for command complete flag or timeout */
863 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
864 IFC_TIMEOUT_MSECS * HZ/1000);
865
866 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
867 printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
868
869 /* Restore CSOR and CSOR_ext */
870 iowrite32be(csor, &ifc->csor_cs[cs].csor);
871 iowrite32be(csor_ext, &ifc->csor_cs[cs].csor_ext);
872 }
873
874 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
875 {
876 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
877 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
878 struct nand_chip *chip = &priv->chip;
879 struct nand_ecclayout *layout;
880 u32 csor, ver;
881
882 /* Fill in fsl_ifc_mtd structure */
883 priv->mtd.priv = chip;
884 priv->mtd.owner = THIS_MODULE;
885
886 /* fill in nand_chip structure */
887 /* set up function call table */
888 if ((ioread32be(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
889 chip->read_byte = fsl_ifc_read_byte16;
890 else
891 chip->read_byte = fsl_ifc_read_byte;
892
893 chip->write_buf = fsl_ifc_write_buf;
894 chip->read_buf = fsl_ifc_read_buf;
895 chip->select_chip = fsl_ifc_select_chip;
896 chip->cmdfunc = fsl_ifc_cmdfunc;
897 chip->waitfunc = fsl_ifc_wait;
898
899 chip->bbt_td = &bbt_main_descr;
900 chip->bbt_md = &bbt_mirror_descr;
901
902 iowrite32be(0x0, &ifc->ifc_nand.ncfgr);
903
904 /* set up nand options */
905 chip->bbt_options = NAND_BBT_USE_FLASH;
906 chip->options = NAND_NO_SUBPAGE_WRITE;
907
908 if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
909 chip->read_byte = fsl_ifc_read_byte16;
910 chip->options |= NAND_BUSWIDTH_16;
911 } else {
912 chip->read_byte = fsl_ifc_read_byte;
913 }
914
915 chip->controller = &ifc_nand_ctrl->controller;
916 chip->priv = priv;
917
918 chip->ecc.read_page = fsl_ifc_read_page;
919 chip->ecc.write_page = fsl_ifc_write_page;
920
921 csor = ioread32be(&ifc->csor_cs[priv->bank].csor);
922
923 /* Hardware generates ECC per 512 Bytes */
924 chip->ecc.size = 512;
925 chip->ecc.bytes = 8;
926 chip->ecc.strength = 4;
927
928 switch (csor & CSOR_NAND_PGS_MASK) {
929 case CSOR_NAND_PGS_512:
930 if (chip->options & NAND_BUSWIDTH_16) {
931 layout = &oob_512_16bit_ecc4;
932 } else {
933 layout = &oob_512_8bit_ecc4;
934
935 /* Avoid conflict with bad block marker */
936 bbt_main_descr.offs = 0;
937 bbt_mirror_descr.offs = 0;
938 }
939
940 priv->bufnum_mask = 15;
941 break;
942
943 case CSOR_NAND_PGS_2K:
944 layout = &oob_2048_ecc4;
945 priv->bufnum_mask = 3;
946 break;
947
948 case CSOR_NAND_PGS_4K:
949 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
950 CSOR_NAND_ECC_MODE_4) {
951 layout = &oob_4096_ecc4;
952 } else {
953 layout = &oob_4096_ecc8;
954 chip->ecc.bytes = 16;
955 chip->ecc.strength = 8;
956 }
957
958 priv->bufnum_mask = 1;
959 break;
960
961 case CSOR_NAND_PGS_8K:
962 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
963 CSOR_NAND_ECC_MODE_4) {
964 layout = &oob_8192_ecc4;
965 } else {
966 layout = &oob_8192_ecc8;
967 chip->ecc.bytes = 16;
968 chip->ecc.strength = 8;
969 }
970
971 priv->bufnum_mask = 0;
972 break;
973
974 default:
975 dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
976 return -ENODEV;
977 }
978
979 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
980 if (csor & CSOR_NAND_ECC_DEC_EN) {
981 chip->ecc.mode = NAND_ECC_HW;
982 chip->ecc.layout = layout;
983 } else {
984 chip->ecc.mode = NAND_ECC_SOFT;
985 }
986
987 ver = ioread32be(&ifc->ifc_rev);
988 if (ver == FSL_IFC_V1_1_0)
989 fsl_ifc_sram_init(priv);
990
991 return 0;
992 }
993
994 static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
995 {
996 nand_release(&priv->mtd);
997
998 kfree(priv->mtd.name);
999
1000 if (priv->vbase)
1001 iounmap(priv->vbase);
1002
1003 ifc_nand_ctrl->chips[priv->bank] = NULL;
1004
1005 return 0;
1006 }
1007
1008 static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
1009 phys_addr_t addr)
1010 {
1011 u32 cspr = ioread32be(&ifc->cspr_cs[bank].cspr);
1012
1013 if (!(cspr & CSPR_V))
1014 return 0;
1015 if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
1016 return 0;
1017
1018 return (cspr & CSPR_BA) == convert_ifc_address(addr);
1019 }
1020
1021 static DEFINE_MUTEX(fsl_ifc_nand_mutex);
1022
1023 static int fsl_ifc_nand_probe(struct platform_device *dev)
1024 {
1025 struct fsl_ifc_regs __iomem *ifc;
1026 struct fsl_ifc_mtd *priv;
1027 struct resource res;
1028 static const char *part_probe_types[]
1029 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
1030 int ret;
1031 int bank;
1032 struct device_node *node = dev->dev.of_node;
1033 struct mtd_part_parser_data ppdata;
1034
1035 ppdata.of_node = dev->dev.of_node;
1036 if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
1037 return -ENODEV;
1038 ifc = fsl_ifc_ctrl_dev->regs;
1039
1040 /* get, allocate and map the memory resource */
1041 ret = of_address_to_resource(node, 0, &res);
1042 if (ret) {
1043 dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
1044 return ret;
1045 }
1046
1047 /* find which chip select it is connected to */
1048 for (bank = 0; bank < FSL_IFC_BANK_COUNT; bank++) {
1049 if (match_bank(ifc, bank, res.start))
1050 break;
1051 }
1052
1053 if (bank >= FSL_IFC_BANK_COUNT) {
1054 dev_err(&dev->dev, "%s: address did not match any chip selects\n",
1055 __func__);
1056 return -ENODEV;
1057 }
1058
1059 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1060 if (!priv)
1061 return -ENOMEM;
1062
1063 mutex_lock(&fsl_ifc_nand_mutex);
1064 if (!fsl_ifc_ctrl_dev->nand) {
1065 ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
1066 if (!ifc_nand_ctrl) {
1067 mutex_unlock(&fsl_ifc_nand_mutex);
1068 return -ENOMEM;
1069 }
1070
1071 ifc_nand_ctrl->read_bytes = 0;
1072 ifc_nand_ctrl->index = 0;
1073 ifc_nand_ctrl->addr = NULL;
1074 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
1075
1076 spin_lock_init(&ifc_nand_ctrl->controller.lock);
1077 init_waitqueue_head(&ifc_nand_ctrl->controller.wq);
1078 } else {
1079 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
1080 }
1081 mutex_unlock(&fsl_ifc_nand_mutex);
1082
1083 ifc_nand_ctrl->chips[bank] = priv;
1084 priv->bank = bank;
1085 priv->ctrl = fsl_ifc_ctrl_dev;
1086 priv->dev = &dev->dev;
1087
1088 priv->vbase = ioremap(res.start, resource_size(&res));
1089 if (!priv->vbase) {
1090 dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
1091 ret = -ENOMEM;
1092 goto err;
1093 }
1094
1095 dev_set_drvdata(priv->dev, priv);
1096
1097 iowrite32be(IFC_NAND_EVTER_EN_OPC_EN |
1098 IFC_NAND_EVTER_EN_FTOER_EN |
1099 IFC_NAND_EVTER_EN_WPER_EN,
1100 &ifc->ifc_nand.nand_evter_en);
1101
1102 /* enable NAND Machine Interrupts */
1103 iowrite32be(IFC_NAND_EVTER_INTR_OPCIR_EN |
1104 IFC_NAND_EVTER_INTR_FTOERIR_EN |
1105 IFC_NAND_EVTER_INTR_WPERIR_EN,
1106 &ifc->ifc_nand.nand_evter_intr_en);
1107 priv->mtd.name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
1108 if (!priv->mtd.name) {
1109 ret = -ENOMEM;
1110 goto err;
1111 }
1112
1113 ret = fsl_ifc_chip_init(priv);
1114 if (ret)
1115 goto err;
1116
1117 ret = nand_scan_ident(&priv->mtd, 1, NULL);
1118 if (ret)
1119 goto err;
1120
1121 ret = fsl_ifc_chip_init_tail(&priv->mtd);
1122 if (ret)
1123 goto err;
1124
1125 ret = nand_scan_tail(&priv->mtd);
1126 if (ret)
1127 goto err;
1128
1129 /* First look for RedBoot table or partitions on the command
1130 * line, these take precedence over device tree information */
1131 mtd_device_parse_register(&priv->mtd, part_probe_types, &ppdata,
1132 NULL, 0);
1133
1134 dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1135 (unsigned long long)res.start, priv->bank);
1136 return 0;
1137
1138 err:
1139 fsl_ifc_chip_remove(priv);
1140 return ret;
1141 }
1142
1143 static int fsl_ifc_nand_remove(struct platform_device *dev)
1144 {
1145 struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1146
1147 fsl_ifc_chip_remove(priv);
1148
1149 mutex_lock(&fsl_ifc_nand_mutex);
1150 ifc_nand_ctrl->counter--;
1151 if (!ifc_nand_ctrl->counter) {
1152 fsl_ifc_ctrl_dev->nand = NULL;
1153 kfree(ifc_nand_ctrl);
1154 }
1155 mutex_unlock(&fsl_ifc_nand_mutex);
1156
1157 return 0;
1158 }
1159
1160 static const struct of_device_id fsl_ifc_nand_match[] = {
1161 {
1162 .compatible = "fsl,ifc-nand",
1163 },
1164 {}
1165 };
1166
1167 static struct platform_driver fsl_ifc_nand_driver = {
1168 .driver = {
1169 .name = "fsl,ifc-nand",
1170 .owner = THIS_MODULE,
1171 .of_match_table = fsl_ifc_nand_match,
1172 },
1173 .probe = fsl_ifc_nand_probe,
1174 .remove = fsl_ifc_nand_remove,
1175 };
1176
1177 module_platform_driver(fsl_ifc_nand_driver);
1178
1179 MODULE_LICENSE("GPL");
1180 MODULE_AUTHOR("Freescale");
1181 MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");
Linux with added FPC-III support