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arm: Add devicetree fixup machine function
[linux/fpc-iii.git] / drivers / mtd / nand / omap2.c
blobf0ed92e210a1fc39d1944e8240d0f4728d91835b
1 /*
2 * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
3 * Copyright © 2004 Micron Technology Inc.
4 * Copyright © 2004 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/platform_device.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/jiffies.h>
18 #include <linux/sched.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/omap-dma.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27
28 #include <linux/mtd/nand_bch.h>
29 #include <linux/platform_data/elm.h>
30
31 #include <linux/platform_data/mtd-nand-omap2.h>
32
33 #define DRIVER_NAME "omap2-nand"
34 #define OMAP_NAND_TIMEOUT_MS 5000
35
36 #define NAND_Ecc_P1e (1 << 0)
37 #define NAND_Ecc_P2e (1 << 1)
38 #define NAND_Ecc_P4e (1 << 2)
39 #define NAND_Ecc_P8e (1 << 3)
40 #define NAND_Ecc_P16e (1 << 4)
41 #define NAND_Ecc_P32e (1 << 5)
42 #define NAND_Ecc_P64e (1 << 6)
43 #define NAND_Ecc_P128e (1 << 7)
44 #define NAND_Ecc_P256e (1 << 8)
45 #define NAND_Ecc_P512e (1 << 9)
46 #define NAND_Ecc_P1024e (1 << 10)
47 #define NAND_Ecc_P2048e (1 << 11)
48
49 #define NAND_Ecc_P1o (1 << 16)
50 #define NAND_Ecc_P2o (1 << 17)
51 #define NAND_Ecc_P4o (1 << 18)
52 #define NAND_Ecc_P8o (1 << 19)
53 #define NAND_Ecc_P16o (1 << 20)
54 #define NAND_Ecc_P32o (1 << 21)
55 #define NAND_Ecc_P64o (1 << 22)
56 #define NAND_Ecc_P128o (1 << 23)
57 #define NAND_Ecc_P256o (1 << 24)
58 #define NAND_Ecc_P512o (1 << 25)
59 #define NAND_Ecc_P1024o (1 << 26)
60 #define NAND_Ecc_P2048o (1 << 27)
61
62 #define TF(value) (value ? 1 : 0)
63
64 #define P2048e(a) (TF(a & NAND_Ecc_P2048e) << 0)
65 #define P2048o(a) (TF(a & NAND_Ecc_P2048o) << 1)
66 #define P1e(a) (TF(a & NAND_Ecc_P1e) << 2)
67 #define P1o(a) (TF(a & NAND_Ecc_P1o) << 3)
68 #define P2e(a) (TF(a & NAND_Ecc_P2e) << 4)
69 #define P2o(a) (TF(a & NAND_Ecc_P2o) << 5)
70 #define P4e(a) (TF(a & NAND_Ecc_P4e) << 6)
71 #define P4o(a) (TF(a & NAND_Ecc_P4o) << 7)
72
73 #define P8e(a) (TF(a & NAND_Ecc_P8e) << 0)
74 #define P8o(a) (TF(a & NAND_Ecc_P8o) << 1)
75 #define P16e(a) (TF(a & NAND_Ecc_P16e) << 2)
76 #define P16o(a) (TF(a & NAND_Ecc_P16o) << 3)
77 #define P32e(a) (TF(a & NAND_Ecc_P32e) << 4)
78 #define P32o(a) (TF(a & NAND_Ecc_P32o) << 5)
79 #define P64e(a) (TF(a & NAND_Ecc_P64e) << 6)
80 #define P64o(a) (TF(a & NAND_Ecc_P64o) << 7)
81
82 #define P128e(a) (TF(a & NAND_Ecc_P128e) << 0)
83 #define P128o(a) (TF(a & NAND_Ecc_P128o) << 1)
84 #define P256e(a) (TF(a & NAND_Ecc_P256e) << 2)
85 #define P256o(a) (TF(a & NAND_Ecc_P256o) << 3)
86 #define P512e(a) (TF(a & NAND_Ecc_P512e) << 4)
87 #define P512o(a) (TF(a & NAND_Ecc_P512o) << 5)
88 #define P1024e(a) (TF(a & NAND_Ecc_P1024e) << 6)
89 #define P1024o(a) (TF(a & NAND_Ecc_P1024o) << 7)
90
91 #define P8e_s(a) (TF(a & NAND_Ecc_P8e) << 0)
92 #define P8o_s(a) (TF(a & NAND_Ecc_P8o) << 1)
93 #define P16e_s(a) (TF(a & NAND_Ecc_P16e) << 2)
94 #define P16o_s(a) (TF(a & NAND_Ecc_P16o) << 3)
95 #define P1e_s(a) (TF(a & NAND_Ecc_P1e) << 4)
96 #define P1o_s(a) (TF(a & NAND_Ecc_P1o) << 5)
97 #define P2e_s(a) (TF(a & NAND_Ecc_P2e) << 6)
98 #define P2o_s(a) (TF(a & NAND_Ecc_P2o) << 7)
99
100 #define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
101 #define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
102
103 #define PREFETCH_CONFIG1_CS_SHIFT 24
104 #define ECC_CONFIG_CS_SHIFT 1
105 #define CS_MASK 0x7
106 #define ENABLE_PREFETCH (0x1 << 7)
107 #define DMA_MPU_MODE_SHIFT 2
108 #define ECCSIZE0_SHIFT 12
109 #define ECCSIZE1_SHIFT 22
110 #define ECC1RESULTSIZE 0x1
111 #define ECCCLEAR 0x100
112 #define ECC1 0x1
113 #define PREFETCH_FIFOTHRESHOLD_MAX 0x40
114 #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
115 #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
116 #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
117 #define STATUS_BUFF_EMPTY 0x00000001
118
119 #define OMAP24XX_DMA_GPMC 4
120
121 #define SECTOR_BYTES 512
122 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
123 #define BCH4_BIT_PAD 4
124
125 /* GPMC ecc engine settings for read */
126 #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
127 #define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */
128 #define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */
129 #define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */
130 #define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */
131
132 /* GPMC ecc engine settings for write */
133 #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
134 #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */
135 #define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */
136
137 #define BADBLOCK_MARKER_LENGTH 2
138
139 #ifdef CONFIG_MTD_NAND_OMAP_BCH
140 static u_char bch16_vector[] = {0xf5, 0x24, 0x1c, 0xd0, 0x61, 0xb3, 0xf1, 0x55,
141 0x2e, 0x2c, 0x86, 0xa3, 0xed, 0x36, 0x1b, 0x78,
142 0x48, 0x76, 0xa9, 0x3b, 0x97, 0xd1, 0x7a, 0x93,
143 0x07, 0x0e};
144 static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
145 0xac, 0x6b, 0xff, 0x99, 0x7b};
146 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
147 #endif
148
149 /* oob info generated runtime depending on ecc algorithm and layout selected */
150 static struct nand_ecclayout omap_oobinfo;
151
152 struct omap_nand_info {
153 struct nand_hw_control controller;
154 struct omap_nand_platform_data *pdata;
155 struct mtd_info mtd;
156 struct nand_chip nand;
157 struct platform_device *pdev;
158
159 int gpmc_cs;
160 unsigned long phys_base;
161 enum omap_ecc ecc_opt;
162 struct completion comp;
163 struct dma_chan *dma;
164 int gpmc_irq_fifo;
165 int gpmc_irq_count;
166 enum {
167 OMAP_NAND_IO_READ = 0, /* read */
168 OMAP_NAND_IO_WRITE, /* write */
169 } iomode;
170 u_char *buf;
171 int buf_len;
172 struct gpmc_nand_regs reg;
173 /* fields specific for BCHx_HW ECC scheme */
174 struct device *elm_dev;
175 struct device_node *of_node;
176 };
177
178 /**
179 * omap_prefetch_enable - configures and starts prefetch transfer
180 * @cs: cs (chip select) number
181 * @fifo_th: fifo threshold to be used for read/ write
182 * @dma_mode: dma mode enable (1) or disable (0)
183 * @u32_count: number of bytes to be transferred
184 * @is_write: prefetch read(0) or write post(1) mode
185 */
186 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
187 unsigned int u32_count, int is_write, struct omap_nand_info *info)
188 {
189 u32 val;
190
191 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
192 return -1;
193
194 if (readl(info->reg.gpmc_prefetch_control))
195 return -EBUSY;
196
197 /* Set the amount of bytes to be prefetched */
198 writel(u32_count, info->reg.gpmc_prefetch_config2);
199
200 /* Set dma/mpu mode, the prefetch read / post write and
201 * enable the engine. Set which cs is has requested for.
202 */
203 val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
204 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
205 (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
206 writel(val, info->reg.gpmc_prefetch_config1);
207
208 /* Start the prefetch engine */
209 writel(0x1, info->reg.gpmc_prefetch_control);
210
211 return 0;
212 }
213
214 /**
215 * omap_prefetch_reset - disables and stops the prefetch engine
216 */
217 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
218 {
219 u32 config1;
220
221 /* check if the same module/cs is trying to reset */
222 config1 = readl(info->reg.gpmc_prefetch_config1);
223 if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
224 return -EINVAL;
225
226 /* Stop the PFPW engine */
227 writel(0x0, info->reg.gpmc_prefetch_control);
228
229 /* Reset/disable the PFPW engine */
230 writel(0x0, info->reg.gpmc_prefetch_config1);
231
232 return 0;
233 }
234
235 /**
236 * omap_hwcontrol - hardware specific access to control-lines
237 * @mtd: MTD device structure
238 * @cmd: command to device
239 * @ctrl:
240 * NAND_NCE: bit 0 -> don't care
241 * NAND_CLE: bit 1 -> Command Latch
242 * NAND_ALE: bit 2 -> Address Latch
243 *
244 * NOTE: boards may use different bits for these!!
245 */
246 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
247 {
248 struct omap_nand_info *info = container_of(mtd,
249 struct omap_nand_info, mtd);
250
251 if (cmd != NAND_CMD_NONE) {
252 if (ctrl & NAND_CLE)
253 writeb(cmd, info->reg.gpmc_nand_command);
254
255 else if (ctrl & NAND_ALE)
256 writeb(cmd, info->reg.gpmc_nand_address);
257
258 else /* NAND_NCE */
259 writeb(cmd, info->reg.gpmc_nand_data);
260 }
261 }
262
263 /**
264 * omap_read_buf8 - read data from NAND controller into buffer
265 * @mtd: MTD device structure
266 * @buf: buffer to store date
267 * @len: number of bytes to read
268 */
269 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
270 {
271 struct nand_chip *nand = mtd->priv;
272
273 ioread8_rep(nand->IO_ADDR_R, buf, len);
274 }
275
276 /**
277 * omap_write_buf8 - write buffer to NAND controller
278 * @mtd: MTD device structure
279 * @buf: data buffer
280 * @len: number of bytes to write
281 */
282 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
283 {
284 struct omap_nand_info *info = container_of(mtd,
285 struct omap_nand_info, mtd);
286 u_char *p = (u_char *)buf;
287 u32 status = 0;
288
289 while (len--) {
290 iowrite8(*p++, info->nand.IO_ADDR_W);
291 /* wait until buffer is available for write */
292 do {
293 status = readl(info->reg.gpmc_status) &
294 STATUS_BUFF_EMPTY;
295 } while (!status);
296 }
297 }
298
299 /**
300 * omap_read_buf16 - read data from NAND controller into buffer
301 * @mtd: MTD device structure
302 * @buf: buffer to store date
303 * @len: number of bytes to read
304 */
305 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
306 {
307 struct nand_chip *nand = mtd->priv;
308
309 ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
310 }
311
312 /**
313 * omap_write_buf16 - write buffer to NAND controller
314 * @mtd: MTD device structure
315 * @buf: data buffer
316 * @len: number of bytes to write
317 */
318 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
319 {
320 struct omap_nand_info *info = container_of(mtd,
321 struct omap_nand_info, mtd);
322 u16 *p = (u16 *) buf;
323 u32 status = 0;
324 /* FIXME try bursts of writesw() or DMA ... */
325 len >>= 1;
326
327 while (len--) {
328 iowrite16(*p++, info->nand.IO_ADDR_W);
329 /* wait until buffer is available for write */
330 do {
331 status = readl(info->reg.gpmc_status) &
332 STATUS_BUFF_EMPTY;
333 } while (!status);
334 }
335 }
336
337 /**
338 * omap_read_buf_pref - read data from NAND controller into buffer
339 * @mtd: MTD device structure
340 * @buf: buffer to store date
341 * @len: number of bytes to read
342 */
343 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
344 {
345 struct omap_nand_info *info = container_of(mtd,
346 struct omap_nand_info, mtd);
347 uint32_t r_count = 0;
348 int ret = 0;
349 u32 *p = (u32 *)buf;
350
351 /* take care of subpage reads */
352 if (len % 4) {
353 if (info->nand.options & NAND_BUSWIDTH_16)
354 omap_read_buf16(mtd, buf, len % 4);
355 else
356 omap_read_buf8(mtd, buf, len % 4);
357 p = (u32 *) (buf + len % 4);
358 len -= len % 4;
359 }
360
361 /* configure and start prefetch transfer */
362 ret = omap_prefetch_enable(info->gpmc_cs,
363 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
364 if (ret) {
365 /* PFPW engine is busy, use cpu copy method */
366 if (info->nand.options & NAND_BUSWIDTH_16)
367 omap_read_buf16(mtd, (u_char *)p, len);
368 else
369 omap_read_buf8(mtd, (u_char *)p, len);
370 } else {
371 do {
372 r_count = readl(info->reg.gpmc_prefetch_status);
373 r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
374 r_count = r_count >> 2;
375 ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
376 p += r_count;
377 len -= r_count << 2;
378 } while (len);
379 /* disable and stop the PFPW engine */
380 omap_prefetch_reset(info->gpmc_cs, info);
381 }
382 }
383
384 /**
385 * omap_write_buf_pref - write buffer to NAND controller
386 * @mtd: MTD device structure
387 * @buf: data buffer
388 * @len: number of bytes to write
389 */
390 static void omap_write_buf_pref(struct mtd_info *mtd,
391 const u_char *buf, int len)
392 {
393 struct omap_nand_info *info = container_of(mtd,
394 struct omap_nand_info, mtd);
395 uint32_t w_count = 0;
396 int i = 0, ret = 0;
397 u16 *p = (u16 *)buf;
398 unsigned long tim, limit;
399 u32 val;
400
401 /* take care of subpage writes */
402 if (len % 2 != 0) {
403 writeb(*buf, info->nand.IO_ADDR_W);
404 p = (u16 *)(buf + 1);
405 len--;
406 }
407
408 /* configure and start prefetch transfer */
409 ret = omap_prefetch_enable(info->gpmc_cs,
410 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
411 if (ret) {
412 /* PFPW engine is busy, use cpu copy method */
413 if (info->nand.options & NAND_BUSWIDTH_16)
414 omap_write_buf16(mtd, (u_char *)p, len);
415 else
416 omap_write_buf8(mtd, (u_char *)p, len);
417 } else {
418 while (len) {
419 w_count = readl(info->reg.gpmc_prefetch_status);
420 w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
421 w_count = w_count >> 1;
422 for (i = 0; (i < w_count) && len; i++, len -= 2)
423 iowrite16(*p++, info->nand.IO_ADDR_W);
424 }
425 /* wait for data to flushed-out before reset the prefetch */
426 tim = 0;
427 limit = (loops_per_jiffy *
428 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
429 do {
430 cpu_relax();
431 val = readl(info->reg.gpmc_prefetch_status);
432 val = PREFETCH_STATUS_COUNT(val);
433 } while (val && (tim++ < limit));
434
435 /* disable and stop the PFPW engine */
436 omap_prefetch_reset(info->gpmc_cs, info);
437 }
438 }
439
440 /*
441 * omap_nand_dma_callback: callback on the completion of dma transfer
442 * @data: pointer to completion data structure
443 */
444 static void omap_nand_dma_callback(void *data)
445 {
446 complete((struct completion *) data);
447 }
448
449 /*
450 * omap_nand_dma_transfer: configure and start dma transfer
451 * @mtd: MTD device structure
452 * @addr: virtual address in RAM of source/destination
453 * @len: number of data bytes to be transferred
454 * @is_write: flag for read/write operation
455 */
456 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
457 unsigned int len, int is_write)
458 {
459 struct omap_nand_info *info = container_of(mtd,
460 struct omap_nand_info, mtd);
461 struct dma_async_tx_descriptor *tx;
462 enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
463 DMA_FROM_DEVICE;
464 struct scatterlist sg;
465 unsigned long tim, limit;
466 unsigned n;
467 int ret;
468 u32 val;
469
470 if (addr >= high_memory) {
471 struct page *p1;
472
473 if (((size_t)addr & PAGE_MASK) !=
474 ((size_t)(addr + len - 1) & PAGE_MASK))
475 goto out_copy;
476 p1 = vmalloc_to_page(addr);
477 if (!p1)
478 goto out_copy;
479 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
480 }
481
482 sg_init_one(&sg, addr, len);
483 n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
484 if (n == 0) {
485 dev_err(&info->pdev->dev,
486 "Couldn't DMA map a %d byte buffer\n", len);
487 goto out_copy;
488 }
489
490 tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
491 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
492 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
493 if (!tx)
494 goto out_copy_unmap;
495
496 tx->callback = omap_nand_dma_callback;
497 tx->callback_param = &info->comp;
498 dmaengine_submit(tx);
499
500 /* configure and start prefetch transfer */
501 ret = omap_prefetch_enable(info->gpmc_cs,
502 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
503 if (ret)
504 /* PFPW engine is busy, use cpu copy method */
505 goto out_copy_unmap;
506
507 init_completion(&info->comp);
508 dma_async_issue_pending(info->dma);
509
510 /* setup and start DMA using dma_addr */
511 wait_for_completion(&info->comp);
512 tim = 0;
513 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
514
515 do {
516 cpu_relax();
517 val = readl(info->reg.gpmc_prefetch_status);
518 val = PREFETCH_STATUS_COUNT(val);
519 } while (val && (tim++ < limit));
520
521 /* disable and stop the PFPW engine */
522 omap_prefetch_reset(info->gpmc_cs, info);
523
524 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
525 return 0;
526
527 out_copy_unmap:
528 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
529 out_copy:
530 if (info->nand.options & NAND_BUSWIDTH_16)
531 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
532 : omap_write_buf16(mtd, (u_char *) addr, len);
533 else
534 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
535 : omap_write_buf8(mtd, (u_char *) addr, len);
536 return 0;
537 }
538
539 /**
540 * omap_read_buf_dma_pref - read data from NAND controller into buffer
541 * @mtd: MTD device structure
542 * @buf: buffer to store date
543 * @len: number of bytes to read
544 */
545 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
546 {
547 if (len <= mtd->oobsize)
548 omap_read_buf_pref(mtd, buf, len);
549 else
550 /* start transfer in DMA mode */
551 omap_nand_dma_transfer(mtd, buf, len, 0x0);
552 }
553
554 /**
555 * omap_write_buf_dma_pref - write buffer to NAND controller
556 * @mtd: MTD device structure
557 * @buf: data buffer
558 * @len: number of bytes to write
559 */
560 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
561 const u_char *buf, int len)
562 {
563 if (len <= mtd->oobsize)
564 omap_write_buf_pref(mtd, buf, len);
565 else
566 /* start transfer in DMA mode */
567 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
568 }
569
570 /*
571 * omap_nand_irq - GPMC irq handler
572 * @this_irq: gpmc irq number
573 * @dev: omap_nand_info structure pointer is passed here
574 */
575 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
576 {
577 struct omap_nand_info *info = (struct omap_nand_info *) dev;
578 u32 bytes;
579
580 bytes = readl(info->reg.gpmc_prefetch_status);
581 bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
582 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
583 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
584 if (this_irq == info->gpmc_irq_count)
585 goto done;
586
587 if (info->buf_len && (info->buf_len < bytes))
588 bytes = info->buf_len;
589 else if (!info->buf_len)
590 bytes = 0;
591 iowrite32_rep(info->nand.IO_ADDR_W,
592 (u32 *)info->buf, bytes >> 2);
593 info->buf = info->buf + bytes;
594 info->buf_len -= bytes;
595
596 } else {
597 ioread32_rep(info->nand.IO_ADDR_R,
598 (u32 *)info->buf, bytes >> 2);
599 info->buf = info->buf + bytes;
600
601 if (this_irq == info->gpmc_irq_count)
602 goto done;
603 }
604
605 return IRQ_HANDLED;
606
607 done:
608 complete(&info->comp);
609
610 disable_irq_nosync(info->gpmc_irq_fifo);
611 disable_irq_nosync(info->gpmc_irq_count);
612
613 return IRQ_HANDLED;
614 }
615
616 /*
617 * omap_read_buf_irq_pref - read data from NAND controller into buffer
618 * @mtd: MTD device structure
619 * @buf: buffer to store date
620 * @len: number of bytes to read
621 */
622 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
623 {
624 struct omap_nand_info *info = container_of(mtd,
625 struct omap_nand_info, mtd);
626 int ret = 0;
627
628 if (len <= mtd->oobsize) {
629 omap_read_buf_pref(mtd, buf, len);
630 return;
631 }
632
633 info->iomode = OMAP_NAND_IO_READ;
634 info->buf = buf;
635 init_completion(&info->comp);
636
637 /* configure and start prefetch transfer */
638 ret = omap_prefetch_enable(info->gpmc_cs,
639 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
640 if (ret)
641 /* PFPW engine is busy, use cpu copy method */
642 goto out_copy;
643
644 info->buf_len = len;
645
646 enable_irq(info->gpmc_irq_count);
647 enable_irq(info->gpmc_irq_fifo);
648
649 /* waiting for read to complete */
650 wait_for_completion(&info->comp);
651
652 /* disable and stop the PFPW engine */
653 omap_prefetch_reset(info->gpmc_cs, info);
654 return;
655
656 out_copy:
657 if (info->nand.options & NAND_BUSWIDTH_16)
658 omap_read_buf16(mtd, buf, len);
659 else
660 omap_read_buf8(mtd, buf, len);
661 }
662
663 /*
664 * omap_write_buf_irq_pref - write buffer to NAND controller
665 * @mtd: MTD device structure
666 * @buf: data buffer
667 * @len: number of bytes to write
668 */
669 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
670 const u_char *buf, int len)
671 {
672 struct omap_nand_info *info = container_of(mtd,
673 struct omap_nand_info, mtd);
674 int ret = 0;
675 unsigned long tim, limit;
676 u32 val;
677
678 if (len <= mtd->oobsize) {
679 omap_write_buf_pref(mtd, buf, len);
680 return;
681 }
682
683 info->iomode = OMAP_NAND_IO_WRITE;
684 info->buf = (u_char *) buf;
685 init_completion(&info->comp);
686
687 /* configure and start prefetch transfer : size=24 */
688 ret = omap_prefetch_enable(info->gpmc_cs,
689 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
690 if (ret)
691 /* PFPW engine is busy, use cpu copy method */
692 goto out_copy;
693
694 info->buf_len = len;
695
696 enable_irq(info->gpmc_irq_count);
697 enable_irq(info->gpmc_irq_fifo);
698
699 /* waiting for write to complete */
700 wait_for_completion(&info->comp);
701
702 /* wait for data to flushed-out before reset the prefetch */
703 tim = 0;
704 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
705 do {
706 val = readl(info->reg.gpmc_prefetch_status);
707 val = PREFETCH_STATUS_COUNT(val);
708 cpu_relax();
709 } while (val && (tim++ < limit));
710
711 /* disable and stop the PFPW engine */
712 omap_prefetch_reset(info->gpmc_cs, info);
713 return;
714
715 out_copy:
716 if (info->nand.options & NAND_BUSWIDTH_16)
717 omap_write_buf16(mtd, buf, len);
718 else
719 omap_write_buf8(mtd, buf, len);
720 }
721
722 /**
723 * gen_true_ecc - This function will generate true ECC value
724 * @ecc_buf: buffer to store ecc code
725 *
726 * This generated true ECC value can be used when correcting
727 * data read from NAND flash memory core
728 */
729 static void gen_true_ecc(u8 *ecc_buf)
730 {
731 u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
732 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
733
734 ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
735 P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
736 ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
737 P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
738 ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
739 P1e(tmp) | P2048o(tmp) | P2048e(tmp));
740 }
741
742 /**
743 * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
744 * @ecc_data1: ecc code from nand spare area
745 * @ecc_data2: ecc code from hardware register obtained from hardware ecc
746 * @page_data: page data
747 *
748 * This function compares two ECC's and indicates if there is an error.
749 * If the error can be corrected it will be corrected to the buffer.
750 * If there is no error, %0 is returned. If there is an error but it
751 * was corrected, %1 is returned. Otherwise, %-1 is returned.
752 */
753 static int omap_compare_ecc(u8 *ecc_data1, /* read from NAND memory */
754 u8 *ecc_data2, /* read from register */
755 u8 *page_data)
756 {
757 uint i;
758 u8 tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
759 u8 comp0_bit[8], comp1_bit[8], comp2_bit[8];
760 u8 ecc_bit[24];
761 u8 ecc_sum = 0;
762 u8 find_bit = 0;
763 uint find_byte = 0;
764 int isEccFF;
765
766 isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
767
768 gen_true_ecc(ecc_data1);
769 gen_true_ecc(ecc_data2);
770
771 for (i = 0; i <= 2; i++) {
772 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
773 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
774 }
775
776 for (i = 0; i < 8; i++) {
777 tmp0_bit[i] = *ecc_data1 % 2;
778 *ecc_data1 = *ecc_data1 / 2;
779 }
780
781 for (i = 0; i < 8; i++) {
782 tmp1_bit[i] = *(ecc_data1 + 1) % 2;
783 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
784 }
785
786 for (i = 0; i < 8; i++) {
787 tmp2_bit[i] = *(ecc_data1 + 2) % 2;
788 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
789 }
790
791 for (i = 0; i < 8; i++) {
792 comp0_bit[i] = *ecc_data2 % 2;
793 *ecc_data2 = *ecc_data2 / 2;
794 }
795
796 for (i = 0; i < 8; i++) {
797 comp1_bit[i] = *(ecc_data2 + 1) % 2;
798 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
799 }
800
801 for (i = 0; i < 8; i++) {
802 comp2_bit[i] = *(ecc_data2 + 2) % 2;
803 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
804 }
805
806 for (i = 0; i < 6; i++)
807 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
808
809 for (i = 0; i < 8; i++)
810 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
811
812 for (i = 0; i < 8; i++)
813 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
814
815 ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
816 ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
817
818 for (i = 0; i < 24; i++)
819 ecc_sum += ecc_bit[i];
820
821 switch (ecc_sum) {
822 case 0:
823 /* Not reached because this function is not called if
824 * ECC values are equal
825 */
826 return 0;
827
828 case 1:
829 /* Uncorrectable error */
830 pr_debug("ECC UNCORRECTED_ERROR 1\n");
831 return -1;
832
833 case 11:
834 /* UN-Correctable error */
835 pr_debug("ECC UNCORRECTED_ERROR B\n");
836 return -1;
837
838 case 12:
839 /* Correctable error */
840 find_byte = (ecc_bit[23] << 8) +
841 (ecc_bit[21] << 7) +
842 (ecc_bit[19] << 6) +
843 (ecc_bit[17] << 5) +
844 (ecc_bit[15] << 4) +
845 (ecc_bit[13] << 3) +
846 (ecc_bit[11] << 2) +
847 (ecc_bit[9] << 1) +
848 ecc_bit[7];
849
850 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
851
852 pr_debug("Correcting single bit ECC error at offset: "
853 "%d, bit: %d\n", find_byte, find_bit);
854
855 page_data[find_byte] ^= (1 << find_bit);
856
857 return 1;
858 default:
859 if (isEccFF) {
860 if (ecc_data2[0] == 0 &&
861 ecc_data2[1] == 0 &&
862 ecc_data2[2] == 0)
863 return 0;
864 }
865 pr_debug("UNCORRECTED_ERROR default\n");
866 return -1;
867 }
868 }
869
870 /**
871 * omap_correct_data - Compares the ECC read with HW generated ECC
872 * @mtd: MTD device structure
873 * @dat: page data
874 * @read_ecc: ecc read from nand flash
875 * @calc_ecc: ecc read from HW ECC registers
876 *
877 * Compares the ecc read from nand spare area with ECC registers values
878 * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
879 * detection and correction. If there are no errors, %0 is returned. If
880 * there were errors and all of the errors were corrected, the number of
881 * corrected errors is returned. If uncorrectable errors exist, %-1 is
882 * returned.
883 */
884 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
885 u_char *read_ecc, u_char *calc_ecc)
886 {
887 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
888 mtd);
889 int blockCnt = 0, i = 0, ret = 0;
890 int stat = 0;
891
892 /* Ex NAND_ECC_HW12_2048 */
893 if ((info->nand.ecc.mode == NAND_ECC_HW) &&
894 (info->nand.ecc.size == 2048))
895 blockCnt = 4;
896 else
897 blockCnt = 1;
898
899 for (i = 0; i < blockCnt; i++) {
900 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
901 ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
902 if (ret < 0)
903 return ret;
904 /* keep track of the number of corrected errors */
905 stat += ret;
906 }
907 read_ecc += 3;
908 calc_ecc += 3;
909 dat += 512;
910 }
911 return stat;
912 }
913
914 /**
915 * omap_calcuate_ecc - Generate non-inverted ECC bytes.
916 * @mtd: MTD device structure
917 * @dat: The pointer to data on which ecc is computed
918 * @ecc_code: The ecc_code buffer
919 *
920 * Using noninverted ECC can be considered ugly since writing a blank
921 * page ie. padding will clear the ECC bytes. This is no problem as long
922 * nobody is trying to write data on the seemingly unused page. Reading
923 * an erased page will produce an ECC mismatch between generated and read
924 * ECC bytes that has to be dealt with separately.
925 */
926 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
927 u_char *ecc_code)
928 {
929 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
930 mtd);
931 u32 val;
932
933 val = readl(info->reg.gpmc_ecc_config);
934 if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs)
935 return -EINVAL;
936
937 /* read ecc result */
938 val = readl(info->reg.gpmc_ecc1_result);
939 *ecc_code++ = val; /* P128e, ..., P1e */
940 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
941 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
942 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
943
944 return 0;
945 }
946
947 /**
948 * omap_enable_hwecc - This function enables the hardware ecc functionality
949 * @mtd: MTD device structure
950 * @mode: Read/Write mode
951 */
952 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
953 {
954 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
955 mtd);
956 struct nand_chip *chip = mtd->priv;
957 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
958 u32 val;
959
960 /* clear ecc and enable bits */
961 val = ECCCLEAR | ECC1;
962 writel(val, info->reg.gpmc_ecc_control);
963
964 /* program ecc and result sizes */
965 val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
966 ECC1RESULTSIZE);
967 writel(val, info->reg.gpmc_ecc_size_config);
968
969 switch (mode) {
970 case NAND_ECC_READ:
971 case NAND_ECC_WRITE:
972 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
973 break;
974 case NAND_ECC_READSYN:
975 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
976 break;
977 default:
978 dev_info(&info->pdev->dev,
979 "error: unrecognized Mode[%d]!\n", mode);
980 break;
981 }
982
983 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
984 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
985 writel(val, info->reg.gpmc_ecc_config);
986 }
987
988 /**
989 * omap_wait - wait until the command is done
990 * @mtd: MTD device structure
991 * @chip: NAND Chip structure
992 *
993 * Wait function is called during Program and erase operations and
994 * the way it is called from MTD layer, we should wait till the NAND
995 * chip is ready after the programming/erase operation has completed.
996 *
997 * Erase can take up to 400ms and program up to 20ms according to
998 * general NAND and SmartMedia specs
999 */
1000 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
1001 {
1002 struct nand_chip *this = mtd->priv;
1003 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1004 mtd);
1005 unsigned long timeo = jiffies;
1006 int status, state = this->state;
1007
1008 if (state == FL_ERASING)
1009 timeo += msecs_to_jiffies(400);
1010 else
1011 timeo += msecs_to_jiffies(20);
1012
1013 writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1014 while (time_before(jiffies, timeo)) {
1015 status = readb(info->reg.gpmc_nand_data);
1016 if (status & NAND_STATUS_READY)
1017 break;
1018 cond_resched();
1019 }
1020
1021 status = readb(info->reg.gpmc_nand_data);
1022 return status;
1023 }
1024
1025 /**
1026 * omap_dev_ready - calls the platform specific dev_ready function
1027 * @mtd: MTD device structure
1028 */
1029 static int omap_dev_ready(struct mtd_info *mtd)
1030 {
1031 unsigned int val = 0;
1032 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1033 mtd);
1034
1035 val = readl(info->reg.gpmc_status);
1036
1037 if ((val & 0x100) == 0x100) {
1038 return 1;
1039 } else {
1040 return 0;
1041 }
1042 }
1043
1044 /**
1045 * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation
1046 * @mtd: MTD device structure
1047 * @mode: Read/Write mode
1048 *
1049 * When using BCH, sector size is hardcoded to 512 bytes.
1050 * Using wrapping mode 6 both for reading and writing if ELM module not uses
1051 * for error correction.
1052 * On writing,
1053 * eccsize0 = 0 (no additional protected byte in spare area)
1054 * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1055 */
1056 static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode)
1057 {
1058 unsigned int bch_type;
1059 unsigned int dev_width, nsectors;
1060 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1061 mtd);
1062 enum omap_ecc ecc_opt = info->ecc_opt;
1063 struct nand_chip *chip = mtd->priv;
1064 u32 val, wr_mode;
1065 unsigned int ecc_size1, ecc_size0;
1066
1067 /* GPMC configurations for calculating ECC */
1068 switch (ecc_opt) {
1069 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1070 bch_type = 0;
1071 nsectors = 1;
1072 if (mode == NAND_ECC_READ) {
1073 wr_mode = BCH_WRAPMODE_6;
1074 ecc_size0 = BCH_ECC_SIZE0;
1075 ecc_size1 = BCH_ECC_SIZE1;
1076 } else {
1077 wr_mode = BCH_WRAPMODE_6;
1078 ecc_size0 = BCH_ECC_SIZE0;
1079 ecc_size1 = BCH_ECC_SIZE1;
1080 }
1081 break;
1082 case OMAP_ECC_BCH4_CODE_HW:
1083 bch_type = 0;
1084 nsectors = chip->ecc.steps;
1085 if (mode == NAND_ECC_READ) {
1086 wr_mode = BCH_WRAPMODE_1;
1087 ecc_size0 = BCH4R_ECC_SIZE0;
1088 ecc_size1 = BCH4R_ECC_SIZE1;
1089 } else {
1090 wr_mode = BCH_WRAPMODE_6;
1091 ecc_size0 = BCH_ECC_SIZE0;
1092 ecc_size1 = BCH_ECC_SIZE1;
1093 }
1094 break;
1095 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1096 bch_type = 1;
1097 nsectors = 1;
1098 if (mode == NAND_ECC_READ) {
1099 wr_mode = BCH_WRAPMODE_6;
1100 ecc_size0 = BCH_ECC_SIZE0;
1101 ecc_size1 = BCH_ECC_SIZE1;
1102 } else {
1103 wr_mode = BCH_WRAPMODE_6;
1104 ecc_size0 = BCH_ECC_SIZE0;
1105 ecc_size1 = BCH_ECC_SIZE1;
1106 }
1107 break;
1108 case OMAP_ECC_BCH8_CODE_HW:
1109 bch_type = 1;
1110 nsectors = chip->ecc.steps;
1111 if (mode == NAND_ECC_READ) {
1112 wr_mode = BCH_WRAPMODE_1;
1113 ecc_size0 = BCH8R_ECC_SIZE0;
1114 ecc_size1 = BCH8R_ECC_SIZE1;
1115 } else {
1116 wr_mode = BCH_WRAPMODE_6;
1117 ecc_size0 = BCH_ECC_SIZE0;
1118 ecc_size1 = BCH_ECC_SIZE1;
1119 }
1120 break;
1121 case OMAP_ECC_BCH16_CODE_HW:
1122 bch_type = 0x2;
1123 nsectors = chip->ecc.steps;
1124 if (mode == NAND_ECC_READ) {
1125 wr_mode = 0x01;
1126 ecc_size0 = 52; /* ECC bits in nibbles per sector */
1127 ecc_size1 = 0; /* non-ECC bits in nibbles per sector */
1128 } else {
1129 wr_mode = 0x01;
1130 ecc_size0 = 0; /* extra bits in nibbles per sector */
1131 ecc_size1 = 52; /* OOB bits in nibbles per sector */
1132 }
1133 break;
1134 default:
1135 return;
1136 }
1137
1138 writel(ECC1, info->reg.gpmc_ecc_control);
1139
1140 /* Configure ecc size for BCH */
1141 val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
1142 writel(val, info->reg.gpmc_ecc_size_config);
1143
1144 dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1145
1146 /* BCH configuration */
1147 val = ((1 << 16) | /* enable BCH */
1148 (bch_type << 12) | /* BCH4/BCH8/BCH16 */
1149 (wr_mode << 8) | /* wrap mode */
1150 (dev_width << 7) | /* bus width */
1151 (((nsectors-1) & 0x7) << 4) | /* number of sectors */
1152 (info->gpmc_cs << 1) | /* ECC CS */
1153 (0x1)); /* enable ECC */
1154
1155 writel(val, info->reg.gpmc_ecc_config);
1156
1157 /* Clear ecc and enable bits */
1158 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1159 }
1160
1161 static u8 bch4_polynomial[] = {0x28, 0x13, 0xcc, 0x39, 0x96, 0xac, 0x7f};
1162 static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
1163 0x97, 0x79, 0xe5, 0x24, 0xb5};
1164
1165 /**
1166 * omap_calculate_ecc_bch - Generate bytes of ECC bytes
1167 * @mtd: MTD device structure
1168 * @dat: The pointer to data on which ecc is computed
1169 * @ecc_code: The ecc_code buffer
1170 *
1171 * Support calculating of BCH4/8 ecc vectors for the page
1172 */
1173 static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd,
1174 const u_char *dat, u_char *ecc_calc)
1175 {
1176 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1177 mtd);
1178 int eccbytes = info->nand.ecc.bytes;
1179 struct gpmc_nand_regs *gpmc_regs = &info->reg;
1180 u8 *ecc_code;
1181 unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
1182 u32 val;
1183 int i, j;
1184
1185 nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1186 for (i = 0; i < nsectors; i++) {
1187 ecc_code = ecc_calc;
1188 switch (info->ecc_opt) {
1189 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1190 case OMAP_ECC_BCH8_CODE_HW:
1191 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1192 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1193 bch_val3 = readl(gpmc_regs->gpmc_bch_result2[i]);
1194 bch_val4 = readl(gpmc_regs->gpmc_bch_result3[i]);
1195 *ecc_code++ = (bch_val4 & 0xFF);
1196 *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1197 *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1198 *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1199 *ecc_code++ = (bch_val3 & 0xFF);
1200 *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1201 *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1202 *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1203 *ecc_code++ = (bch_val2 & 0xFF);
1204 *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1205 *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1206 *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1207 *ecc_code++ = (bch_val1 & 0xFF);
1208 break;
1209 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1210 case OMAP_ECC_BCH4_CODE_HW:
1211 bch_val1 = readl(gpmc_regs->gpmc_bch_result0[i]);
1212 bch_val2 = readl(gpmc_regs->gpmc_bch_result1[i]);
1213 *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1214 *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1215 *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1216 ((bch_val1 >> 28) & 0xF);
1217 *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1218 *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1219 *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1220 *ecc_code++ = ((bch_val1 & 0xF) << 4);
1221 break;
1222 case OMAP_ECC_BCH16_CODE_HW:
1223 val = readl(gpmc_regs->gpmc_bch_result6[i]);
1224 ecc_code[0] = ((val >> 8) & 0xFF);
1225 ecc_code[1] = ((val >> 0) & 0xFF);
1226 val = readl(gpmc_regs->gpmc_bch_result5[i]);
1227 ecc_code[2] = ((val >> 24) & 0xFF);
1228 ecc_code[3] = ((val >> 16) & 0xFF);
1229 ecc_code[4] = ((val >> 8) & 0xFF);
1230 ecc_code[5] = ((val >> 0) & 0xFF);
1231 val = readl(gpmc_regs->gpmc_bch_result4[i]);
1232 ecc_code[6] = ((val >> 24) & 0xFF);
1233 ecc_code[7] = ((val >> 16) & 0xFF);
1234 ecc_code[8] = ((val >> 8) & 0xFF);
1235 ecc_code[9] = ((val >> 0) & 0xFF);
1236 val = readl(gpmc_regs->gpmc_bch_result3[i]);
1237 ecc_code[10] = ((val >> 24) & 0xFF);
1238 ecc_code[11] = ((val >> 16) & 0xFF);
1239 ecc_code[12] = ((val >> 8) & 0xFF);
1240 ecc_code[13] = ((val >> 0) & 0xFF);
1241 val = readl(gpmc_regs->gpmc_bch_result2[i]);
1242 ecc_code[14] = ((val >> 24) & 0xFF);
1243 ecc_code[15] = ((val >> 16) & 0xFF);
1244 ecc_code[16] = ((val >> 8) & 0xFF);
1245 ecc_code[17] = ((val >> 0) & 0xFF);
1246 val = readl(gpmc_regs->gpmc_bch_result1[i]);
1247 ecc_code[18] = ((val >> 24) & 0xFF);
1248 ecc_code[19] = ((val >> 16) & 0xFF);
1249 ecc_code[20] = ((val >> 8) & 0xFF);
1250 ecc_code[21] = ((val >> 0) & 0xFF);
1251 val = readl(gpmc_regs->gpmc_bch_result0[i]);
1252 ecc_code[22] = ((val >> 24) & 0xFF);
1253 ecc_code[23] = ((val >> 16) & 0xFF);
1254 ecc_code[24] = ((val >> 8) & 0xFF);
1255 ecc_code[25] = ((val >> 0) & 0xFF);
1256 break;
1257 default:
1258 return -EINVAL;
1259 }
1260
1261 /* ECC scheme specific syndrome customizations */
1262 switch (info->ecc_opt) {
1263 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1264 /* Add constant polynomial to remainder, so that
1265 * ECC of blank pages results in 0x0 on reading back */
1266 for (j = 0; j < eccbytes; j++)
1267 ecc_calc[j] ^= bch4_polynomial[j];
1268 break;
1269 case OMAP_ECC_BCH4_CODE_HW:
1270 /* Set 8th ECC byte as 0x0 for ROM compatibility */
1271 ecc_calc[eccbytes - 1] = 0x0;
1272 break;
1273 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1274 /* Add constant polynomial to remainder, so that
1275 * ECC of blank pages results in 0x0 on reading back */
1276 for (j = 0; j < eccbytes; j++)
1277 ecc_calc[j] ^= bch8_polynomial[j];
1278 break;
1279 case OMAP_ECC_BCH8_CODE_HW:
1280 /* Set 14th ECC byte as 0x0 for ROM compatibility */
1281 ecc_calc[eccbytes - 1] = 0x0;
1282 break;
1283 case OMAP_ECC_BCH16_CODE_HW:
1284 break;
1285 default:
1286 return -EINVAL;
1287 }
1288
1289 ecc_calc += eccbytes;
1290 }
1291
1292 return 0;
1293 }
1294
1295 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1296 /**
1297 * erased_sector_bitflips - count bit flips
1298 * @data: data sector buffer
1299 * @oob: oob buffer
1300 * @info: omap_nand_info
1301 *
1302 * Check the bit flips in erased page falls below correctable level.
1303 * If falls below, report the page as erased with correctable bit
1304 * flip, else report as uncorrectable page.
1305 */
1306 static int erased_sector_bitflips(u_char *data, u_char *oob,
1307 struct omap_nand_info *info)
1308 {
1309 int flip_bits = 0, i;
1310
1311 for (i = 0; i < info->nand.ecc.size; i++) {
1312 flip_bits += hweight8(~data[i]);
1313 if (flip_bits > info->nand.ecc.strength)
1314 return 0;
1315 }
1316
1317 for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1318 flip_bits += hweight8(~oob[i]);
1319 if (flip_bits > info->nand.ecc.strength)
1320 return 0;
1321 }
1322
1323 /*
1324 * Bit flips falls in correctable level.
1325 * Fill data area with 0xFF
1326 */
1327 if (flip_bits) {
1328 memset(data, 0xFF, info->nand.ecc.size);
1329 memset(oob, 0xFF, info->nand.ecc.bytes);
1330 }
1331
1332 return flip_bits;
1333 }
1334
1335 /**
1336 * omap_elm_correct_data - corrects page data area in case error reported
1337 * @mtd: MTD device structure
1338 * @data: page data
1339 * @read_ecc: ecc read from nand flash
1340 * @calc_ecc: ecc read from HW ECC registers
1341 *
1342 * Calculated ecc vector reported as zero in case of non-error pages.
1343 * In case of non-zero ecc vector, first filter out erased-pages, and
1344 * then process data via ELM to detect bit-flips.
1345 */
1346 static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data,
1347 u_char *read_ecc, u_char *calc_ecc)
1348 {
1349 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1350 mtd);
1351 struct nand_ecc_ctrl *ecc = &info->nand.ecc;
1352 int eccsteps = info->nand.ecc.steps;
1353 int i , j, stat = 0;
1354 int eccflag, actual_eccbytes;
1355 struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1356 u_char *ecc_vec = calc_ecc;
1357 u_char *spare_ecc = read_ecc;
1358 u_char *erased_ecc_vec;
1359 u_char *buf;
1360 int bitflip_count;
1361 bool is_error_reported = false;
1362 u32 bit_pos, byte_pos, error_max, pos;
1363 int err;
1364
1365 switch (info->ecc_opt) {
1366 case OMAP_ECC_BCH4_CODE_HW:
1367 /* omit 7th ECC byte reserved for ROM code compatibility */
1368 actual_eccbytes = ecc->bytes - 1;
1369 erased_ecc_vec = bch4_vector;
1370 break;
1371 case OMAP_ECC_BCH8_CODE_HW:
1372 /* omit 14th ECC byte reserved for ROM code compatibility */
1373 actual_eccbytes = ecc->bytes - 1;
1374 erased_ecc_vec = bch8_vector;
1375 break;
1376 case OMAP_ECC_BCH16_CODE_HW:
1377 actual_eccbytes = ecc->bytes;
1378 erased_ecc_vec = bch16_vector;
1379 break;
1380 default:
1381 pr_err("invalid driver configuration\n");
1382 return -EINVAL;
1383 }
1384
1385 /* Initialize elm error vector to zero */
1386 memset(err_vec, 0, sizeof(err_vec));
1387
1388 for (i = 0; i < eccsteps ; i++) {
1389 eccflag = 0; /* initialize eccflag */
1390
1391 /*
1392 * Check any error reported,
1393 * In case of error, non zero ecc reported.
1394 */
1395 for (j = 0; j < actual_eccbytes; j++) {
1396 if (calc_ecc[j] != 0) {
1397 eccflag = 1; /* non zero ecc, error present */
1398 break;
1399 }
1400 }
1401
1402 if (eccflag == 1) {
1403 if (memcmp(calc_ecc, erased_ecc_vec,
1404 actual_eccbytes) == 0) {
1405 /*
1406 * calc_ecc[] matches pattern for ECC(all 0xff)
1407 * so this is definitely an erased-page
1408 */
1409 } else {
1410 buf = &data[info->nand.ecc.size * i];
1411 /*
1412 * count number of 0-bits in read_buf.
1413 * This check can be removed once a similar
1414 * check is introduced in generic NAND driver
1415 */
1416 bitflip_count = erased_sector_bitflips(
1417 buf, read_ecc, info);
1418 if (bitflip_count) {
1419 /*
1420 * number of 0-bits within ECC limits
1421 * So this may be an erased-page
1422 */
1423 stat += bitflip_count;
1424 } else {
1425 /*
1426 * Too many 0-bits. It may be a
1427 * - programmed-page, OR
1428 * - erased-page with many bit-flips
1429 * So this page requires check by ELM
1430 */
1431 err_vec[i].error_reported = true;
1432 is_error_reported = true;
1433 }
1434 }
1435 }
1436
1437 /* Update the ecc vector */
1438 calc_ecc += ecc->bytes;
1439 read_ecc += ecc->bytes;
1440 }
1441
1442 /* Check if any error reported */
1443 if (!is_error_reported)
1444 return stat;
1445
1446 /* Decode BCH error using ELM module */
1447 elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1448
1449 err = 0;
1450 for (i = 0; i < eccsteps; i++) {
1451 if (err_vec[i].error_uncorrectable) {
1452 pr_err("nand: uncorrectable bit-flips found\n");
1453 err = -EBADMSG;
1454 } else if (err_vec[i].error_reported) {
1455 for (j = 0; j < err_vec[i].error_count; j++) {
1456 switch (info->ecc_opt) {
1457 case OMAP_ECC_BCH4_CODE_HW:
1458 /* Add 4 bits to take care of padding */
1459 pos = err_vec[i].error_loc[j] +
1460 BCH4_BIT_PAD;
1461 break;
1462 case OMAP_ECC_BCH8_CODE_HW:
1463 case OMAP_ECC_BCH16_CODE_HW:
1464 pos = err_vec[i].error_loc[j];
1465 break;
1466 default:
1467 return -EINVAL;
1468 }
1469 error_max = (ecc->size + actual_eccbytes) * 8;
1470 /* Calculate bit position of error */
1471 bit_pos = pos % 8;
1472
1473 /* Calculate byte position of error */
1474 byte_pos = (error_max - pos - 1) / 8;
1475
1476 if (pos < error_max) {
1477 if (byte_pos < 512) {
1478 pr_debug("bitflip@dat[%d]=%x\n",
1479 byte_pos, data[byte_pos]);
1480 data[byte_pos] ^= 1 << bit_pos;
1481 } else {
1482 pr_debug("bitflip@oob[%d]=%x\n",
1483 (byte_pos - 512),
1484 spare_ecc[byte_pos - 512]);
1485 spare_ecc[byte_pos - 512] ^=
1486 1 << bit_pos;
1487 }
1488 } else {
1489 pr_err("invalid bit-flip @ %d:%d\n",
1490 byte_pos, bit_pos);
1491 err = -EBADMSG;
1492 }
1493 }
1494 }
1495
1496 /* Update number of correctable errors */
1497 stat += err_vec[i].error_count;
1498
1499 /* Update page data with sector size */
1500 data += ecc->size;
1501 spare_ecc += ecc->bytes;
1502 }
1503
1504 return (err) ? err : stat;
1505 }
1506
1507 /**
1508 * omap_write_page_bch - BCH ecc based write page function for entire page
1509 * @mtd: mtd info structure
1510 * @chip: nand chip info structure
1511 * @buf: data buffer
1512 * @oob_required: must write chip->oob_poi to OOB
1513 *
1514 * Custom write page method evolved to support multi sector writing in one shot
1515 */
1516 static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1517 const uint8_t *buf, int oob_required)
1518 {
1519 int i;
1520 uint8_t *ecc_calc = chip->buffers->ecccalc;
1521 uint32_t *eccpos = chip->ecc.layout->eccpos;
1522
1523 /* Enable GPMC ecc engine */
1524 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1525
1526 /* Write data */
1527 chip->write_buf(mtd, buf, mtd->writesize);
1528
1529 /* Update ecc vector from GPMC result registers */
1530 chip->ecc.calculate(mtd, buf, &ecc_calc[0]);
1531
1532 for (i = 0; i < chip->ecc.total; i++)
1533 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1534
1535 /* Write ecc vector to OOB area */
1536 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1537 return 0;
1538 }
1539
1540 /**
1541 * omap_read_page_bch - BCH ecc based page read function for entire page
1542 * @mtd: mtd info structure
1543 * @chip: nand chip info structure
1544 * @buf: buffer to store read data
1545 * @oob_required: caller requires OOB data read to chip->oob_poi
1546 * @page: page number to read
1547 *
1548 * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1549 * used for error correction.
1550 * Custom method evolved to support ELM error correction & multi sector
1551 * reading. On reading page data area is read along with OOB data with
1552 * ecc engine enabled. ecc vector updated after read of OOB data.
1553 * For non error pages ecc vector reported as zero.
1554 */
1555 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1556 uint8_t *buf, int oob_required, int page)
1557 {
1558 uint8_t *ecc_calc = chip->buffers->ecccalc;
1559 uint8_t *ecc_code = chip->buffers->ecccode;
1560 uint32_t *eccpos = chip->ecc.layout->eccpos;
1561 uint8_t *oob = &chip->oob_poi[eccpos[0]];
1562 uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0];
1563 int stat;
1564 unsigned int max_bitflips = 0;
1565
1566 /* Enable GPMC ecc engine */
1567 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1568
1569 /* Read data */
1570 chip->read_buf(mtd, buf, mtd->writesize);
1571
1572 /* Read oob bytes */
1573 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
1574 chip->read_buf(mtd, oob, chip->ecc.total);
1575
1576 /* Calculate ecc bytes */
1577 chip->ecc.calculate(mtd, buf, ecc_calc);
1578
1579 memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total);
1580
1581 stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc);
1582
1583 if (stat < 0) {
1584 mtd->ecc_stats.failed++;
1585 } else {
1586 mtd->ecc_stats.corrected += stat;
1587 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1588 }
1589
1590 return max_bitflips;
1591 }
1592
1593 /**
1594 * is_elm_present - checks for presence of ELM module by scanning DT nodes
1595 * @omap_nand_info: NAND device structure containing platform data
1596 * @bch_type: 0x0=BCH4, 0x1=BCH8, 0x2=BCH16
1597 */
1598 static int is_elm_present(struct omap_nand_info *info,
1599 struct device_node *elm_node, enum bch_ecc bch_type)
1600 {
1601 struct platform_device *pdev;
1602 struct nand_ecc_ctrl *ecc = &info->nand.ecc;
1603 int err;
1604 /* check whether elm-id is passed via DT */
1605 if (!elm_node) {
1606 pr_err("nand: error: ELM DT node not found\n");
1607 return -ENODEV;
1608 }
1609 pdev = of_find_device_by_node(elm_node);
1610 /* check whether ELM device is registered */
1611 if (!pdev) {
1612 pr_err("nand: error: ELM device not found\n");
1613 return -ENODEV;
1614 }
1615 /* ELM module available, now configure it */
1616 info->elm_dev = &pdev->dev;
1617 err = elm_config(info->elm_dev, bch_type,
1618 (info->mtd.writesize / ecc->size), ecc->size, ecc->bytes);
1619
1620 return err;
1621 }
1622 #endif /* CONFIG_MTD_NAND_ECC_BCH */
1623
1624 static int omap_nand_probe(struct platform_device *pdev)
1625 {
1626 struct omap_nand_info *info;
1627 struct omap_nand_platform_data *pdata;
1628 struct mtd_info *mtd;
1629 struct nand_chip *nand_chip;
1630 struct nand_ecclayout *ecclayout;
1631 int err;
1632 int i;
1633 dma_cap_mask_t mask;
1634 unsigned sig;
1635 unsigned oob_index;
1636 struct resource *res;
1637 struct mtd_part_parser_data ppdata = {};
1638
1639 pdata = dev_get_platdata(&pdev->dev);
1640 if (pdata == NULL) {
1641 dev_err(&pdev->dev, "platform data missing\n");
1642 return -ENODEV;
1643 }
1644
1645 info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info),
1646 GFP_KERNEL);
1647 if (!info)
1648 return -ENOMEM;
1649
1650 platform_set_drvdata(pdev, info);
1651
1652 spin_lock_init(&info->controller.lock);
1653 init_waitqueue_head(&info->controller.wq);
1654
1655 info->pdev = pdev;
1656 info->gpmc_cs = pdata->cs;
1657 info->reg = pdata->reg;
1658 info->of_node = pdata->of_node;
1659 info->ecc_opt = pdata->ecc_opt;
1660 mtd = &info->mtd;
1661 mtd->priv = &info->nand;
1662 mtd->name = dev_name(&pdev->dev);
1663 mtd->owner = THIS_MODULE;
1664 nand_chip = &info->nand;
1665 nand_chip->ecc.priv = NULL;
1666 nand_chip->options |= NAND_SKIP_BBTSCAN;
1667
1668 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1669 nand_chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
1670 if (IS_ERR(nand_chip->IO_ADDR_R))
1671 return PTR_ERR(nand_chip->IO_ADDR_R);
1672
1673 info->phys_base = res->start;
1674
1675 nand_chip->controller = &info->controller;
1676
1677 nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
1678 nand_chip->cmd_ctrl = omap_hwcontrol;
1679
1680 /*
1681 * If RDY/BSY line is connected to OMAP then use the omap ready
1682 * function and the generic nand_wait function which reads the status
1683 * register after monitoring the RDY/BSY line. Otherwise use a standard
1684 * chip delay which is slightly more than tR (AC Timing) of the NAND
1685 * device and read status register until you get a failure or success
1686 */
1687 if (pdata->dev_ready) {
1688 nand_chip->dev_ready = omap_dev_ready;
1689 nand_chip->chip_delay = 0;
1690 } else {
1691 nand_chip->waitfunc = omap_wait;
1692 nand_chip->chip_delay = 50;
1693 }
1694
1695 /* scan NAND device connected to chip controller */
1696 nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16;
1697 if (nand_scan_ident(mtd, 1, NULL)) {
1698 pr_err("nand device scan failed, may be bus-width mismatch\n");
1699 err = -ENXIO;
1700 goto return_error;
1701 }
1702
1703 /* check for small page devices */
1704 if ((mtd->oobsize < 64) && (pdata->ecc_opt != OMAP_ECC_HAM1_CODE_HW)) {
1705 pr_err("small page devices are not supported\n");
1706 err = -EINVAL;
1707 goto return_error;
1708 }
1709
1710 /* re-populate low-level callbacks based on xfer modes */
1711 switch (pdata->xfer_type) {
1712 case NAND_OMAP_PREFETCH_POLLED:
1713 nand_chip->read_buf = omap_read_buf_pref;
1714 nand_chip->write_buf = omap_write_buf_pref;
1715 break;
1716
1717 case NAND_OMAP_POLLED:
1718 /* Use nand_base defaults for {read,write}_buf */
1719 break;
1720
1721 case NAND_OMAP_PREFETCH_DMA:
1722 dma_cap_zero(mask);
1723 dma_cap_set(DMA_SLAVE, mask);
1724 sig = OMAP24XX_DMA_GPMC;
1725 info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1726 if (!info->dma) {
1727 dev_err(&pdev->dev, "DMA engine request failed\n");
1728 err = -ENXIO;
1729 goto return_error;
1730 } else {
1731 struct dma_slave_config cfg;
1732
1733 memset(&cfg, 0, sizeof(cfg));
1734 cfg.src_addr = info->phys_base;
1735 cfg.dst_addr = info->phys_base;
1736 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1737 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1738 cfg.src_maxburst = 16;
1739 cfg.dst_maxburst = 16;
1740 err = dmaengine_slave_config(info->dma, &cfg);
1741 if (err) {
1742 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
1743 err);
1744 goto return_error;
1745 }
1746 nand_chip->read_buf = omap_read_buf_dma_pref;
1747 nand_chip->write_buf = omap_write_buf_dma_pref;
1748 }
1749 break;
1750
1751 case NAND_OMAP_PREFETCH_IRQ:
1752 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1753 if (info->gpmc_irq_fifo <= 0) {
1754 dev_err(&pdev->dev, "error getting fifo irq\n");
1755 err = -ENODEV;
1756 goto return_error;
1757 }
1758 err = devm_request_irq(&pdev->dev, info->gpmc_irq_fifo,
1759 omap_nand_irq, IRQF_SHARED,
1760 "gpmc-nand-fifo", info);
1761 if (err) {
1762 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1763 info->gpmc_irq_fifo, err);
1764 info->gpmc_irq_fifo = 0;
1765 goto return_error;
1766 }
1767
1768 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1769 if (info->gpmc_irq_count <= 0) {
1770 dev_err(&pdev->dev, "error getting count irq\n");
1771 err = -ENODEV;
1772 goto return_error;
1773 }
1774 err = devm_request_irq(&pdev->dev, info->gpmc_irq_count,
1775 omap_nand_irq, IRQF_SHARED,
1776 "gpmc-nand-count", info);
1777 if (err) {
1778 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1779 info->gpmc_irq_count, err);
1780 info->gpmc_irq_count = 0;
1781 goto return_error;
1782 }
1783
1784 nand_chip->read_buf = omap_read_buf_irq_pref;
1785 nand_chip->write_buf = omap_write_buf_irq_pref;
1786
1787 break;
1788
1789 default:
1790 dev_err(&pdev->dev,
1791 "xfer_type(%d) not supported!\n", pdata->xfer_type);
1792 err = -EINVAL;
1793 goto return_error;
1794 }
1795
1796 /* populate MTD interface based on ECC scheme */
1797 nand_chip->ecc.layout = &omap_oobinfo;
1798 ecclayout = &omap_oobinfo;
1799 switch (info->ecc_opt) {
1800 case OMAP_ECC_HAM1_CODE_HW:
1801 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
1802 nand_chip->ecc.mode = NAND_ECC_HW;
1803 nand_chip->ecc.bytes = 3;
1804 nand_chip->ecc.size = 512;
1805 nand_chip->ecc.strength = 1;
1806 nand_chip->ecc.calculate = omap_calculate_ecc;
1807 nand_chip->ecc.hwctl = omap_enable_hwecc;
1808 nand_chip->ecc.correct = omap_correct_data;
1809 /* define ECC layout */
1810 ecclayout->eccbytes = nand_chip->ecc.bytes *
1811 (mtd->writesize /
1812 nand_chip->ecc.size);
1813 if (nand_chip->options & NAND_BUSWIDTH_16)
1814 oob_index = BADBLOCK_MARKER_LENGTH;
1815 else
1816 oob_index = 1;
1817 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1818 ecclayout->eccpos[i] = oob_index;
1819 /* no reserved-marker in ecclayout for this ecc-scheme */
1820 ecclayout->oobfree->offset =
1821 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1822 break;
1823
1824 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1825 #ifdef CONFIG_MTD_NAND_ECC_BCH
1826 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
1827 nand_chip->ecc.mode = NAND_ECC_HW;
1828 nand_chip->ecc.size = 512;
1829 nand_chip->ecc.bytes = 7;
1830 nand_chip->ecc.strength = 4;
1831 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1832 nand_chip->ecc.correct = nand_bch_correct_data;
1833 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1834 /* define ECC layout */
1835 ecclayout->eccbytes = nand_chip->ecc.bytes *
1836 (mtd->writesize /
1837 nand_chip->ecc.size);
1838 oob_index = BADBLOCK_MARKER_LENGTH;
1839 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1840 ecclayout->eccpos[i] = oob_index;
1841 if (((i + 1) % nand_chip->ecc.bytes) == 0)
1842 oob_index++;
1843 }
1844 /* include reserved-marker in ecclayout->oobfree calculation */
1845 ecclayout->oobfree->offset = 1 +
1846 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1847 /* software bch library is used for locating errors */
1848 nand_chip->ecc.priv = nand_bch_init(mtd,
1849 nand_chip->ecc.size,
1850 nand_chip->ecc.bytes,
1851 &nand_chip->ecc.layout);
1852 if (!nand_chip->ecc.priv) {
1853 pr_err("nand: error: unable to use s/w BCH library\n");
1854 err = -EINVAL;
1855 }
1856 break;
1857 #else
1858 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1859 err = -EINVAL;
1860 goto return_error;
1861 #endif
1862
1863 case OMAP_ECC_BCH4_CODE_HW:
1864 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1865 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
1866 nand_chip->ecc.mode = NAND_ECC_HW;
1867 nand_chip->ecc.size = 512;
1868 /* 14th bit is kept reserved for ROM-code compatibility */
1869 nand_chip->ecc.bytes = 7 + 1;
1870 nand_chip->ecc.strength = 4;
1871 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1872 nand_chip->ecc.correct = omap_elm_correct_data;
1873 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1874 nand_chip->ecc.read_page = omap_read_page_bch;
1875 nand_chip->ecc.write_page = omap_write_page_bch;
1876 /* define ECC layout */
1877 ecclayout->eccbytes = nand_chip->ecc.bytes *
1878 (mtd->writesize /
1879 nand_chip->ecc.size);
1880 oob_index = BADBLOCK_MARKER_LENGTH;
1881 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1882 ecclayout->eccpos[i] = oob_index;
1883 /* reserved marker already included in ecclayout->eccbytes */
1884 ecclayout->oobfree->offset =
1885 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1886 /* This ECC scheme requires ELM H/W block */
1887 if (is_elm_present(info, pdata->elm_of_node, BCH4_ECC) < 0) {
1888 pr_err("nand: error: could not initialize ELM\n");
1889 err = -ENODEV;
1890 goto return_error;
1891 }
1892 break;
1893 #else
1894 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1895 err = -EINVAL;
1896 goto return_error;
1897 #endif
1898
1899 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1900 #ifdef CONFIG_MTD_NAND_ECC_BCH
1901 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
1902 nand_chip->ecc.mode = NAND_ECC_HW;
1903 nand_chip->ecc.size = 512;
1904 nand_chip->ecc.bytes = 13;
1905 nand_chip->ecc.strength = 8;
1906 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1907 nand_chip->ecc.correct = nand_bch_correct_data;
1908 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1909 /* define ECC layout */
1910 ecclayout->eccbytes = nand_chip->ecc.bytes *
1911 (mtd->writesize /
1912 nand_chip->ecc.size);
1913 oob_index = BADBLOCK_MARKER_LENGTH;
1914 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) {
1915 ecclayout->eccpos[i] = oob_index;
1916 if (((i + 1) % nand_chip->ecc.bytes) == 0)
1917 oob_index++;
1918 }
1919 /* include reserved-marker in ecclayout->oobfree calculation */
1920 ecclayout->oobfree->offset = 1 +
1921 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1922 /* software bch library is used for locating errors */
1923 nand_chip->ecc.priv = nand_bch_init(mtd,
1924 nand_chip->ecc.size,
1925 nand_chip->ecc.bytes,
1926 &nand_chip->ecc.layout);
1927 if (!nand_chip->ecc.priv) {
1928 pr_err("nand: error: unable to use s/w BCH library\n");
1929 err = -EINVAL;
1930 goto return_error;
1931 }
1932 break;
1933 #else
1934 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1935 err = -EINVAL;
1936 goto return_error;
1937 #endif
1938
1939 case OMAP_ECC_BCH8_CODE_HW:
1940 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1941 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
1942 nand_chip->ecc.mode = NAND_ECC_HW;
1943 nand_chip->ecc.size = 512;
1944 /* 14th bit is kept reserved for ROM-code compatibility */
1945 nand_chip->ecc.bytes = 13 + 1;
1946 nand_chip->ecc.strength = 8;
1947 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1948 nand_chip->ecc.correct = omap_elm_correct_data;
1949 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1950 nand_chip->ecc.read_page = omap_read_page_bch;
1951 nand_chip->ecc.write_page = omap_write_page_bch;
1952 /* This ECC scheme requires ELM H/W block */
1953 err = is_elm_present(info, pdata->elm_of_node, BCH8_ECC);
1954 if (err < 0) {
1955 pr_err("nand: error: could not initialize ELM\n");
1956 goto return_error;
1957 }
1958 /* define ECC layout */
1959 ecclayout->eccbytes = nand_chip->ecc.bytes *
1960 (mtd->writesize /
1961 nand_chip->ecc.size);
1962 oob_index = BADBLOCK_MARKER_LENGTH;
1963 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1964 ecclayout->eccpos[i] = oob_index;
1965 /* reserved marker already included in ecclayout->eccbytes */
1966 ecclayout->oobfree->offset =
1967 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
1968 break;
1969 #else
1970 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1971 err = -EINVAL;
1972 goto return_error;
1973 #endif
1974
1975 case OMAP_ECC_BCH16_CODE_HW:
1976 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1977 pr_info("using OMAP_ECC_BCH16_CODE_HW ECC scheme\n");
1978 nand_chip->ecc.mode = NAND_ECC_HW;
1979 nand_chip->ecc.size = 512;
1980 nand_chip->ecc.bytes = 26;
1981 nand_chip->ecc.strength = 16;
1982 nand_chip->ecc.hwctl = omap_enable_hwecc_bch;
1983 nand_chip->ecc.correct = omap_elm_correct_data;
1984 nand_chip->ecc.calculate = omap_calculate_ecc_bch;
1985 nand_chip->ecc.read_page = omap_read_page_bch;
1986 nand_chip->ecc.write_page = omap_write_page_bch;
1987 /* This ECC scheme requires ELM H/W block */
1988 err = is_elm_present(info, pdata->elm_of_node, BCH16_ECC);
1989 if (err < 0) {
1990 pr_err("ELM is required for this ECC scheme\n");
1991 goto return_error;
1992 }
1993 /* define ECC layout */
1994 ecclayout->eccbytes = nand_chip->ecc.bytes *
1995 (mtd->writesize /
1996 nand_chip->ecc.size);
1997 oob_index = BADBLOCK_MARKER_LENGTH;
1998 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++)
1999 ecclayout->eccpos[i] = oob_index;
2000 /* reserved marker already included in ecclayout->eccbytes */
2001 ecclayout->oobfree->offset =
2002 ecclayout->eccpos[ecclayout->eccbytes - 1] + 1;
2003 break;
2004 #else
2005 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
2006 err = -EINVAL;
2007 goto return_error;
2008 #endif
2009 default:
2010 pr_err("nand: error: invalid or unsupported ECC scheme\n");
2011 err = -EINVAL;
2012 goto return_error;
2013 }
2014
2015 /* all OOB bytes from oobfree->offset till end off OOB are free */
2016 ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
2017 /* check if NAND device's OOB is enough to store ECC signatures */
2018 if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) {
2019 pr_err("not enough OOB bytes required = %d, available=%d\n",
2020 ecclayout->eccbytes, mtd->oobsize);
2021 err = -EINVAL;
2022 goto return_error;
2023 }
2024
2025 /* second phase scan */
2026 if (nand_scan_tail(mtd)) {
2027 err = -ENXIO;
2028 goto return_error;
2029 }
2030
2031 ppdata.of_node = pdata->of_node;
2032 mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts,
2033 pdata->nr_parts);
2034
2035 platform_set_drvdata(pdev, mtd);
2036
2037 return 0;
2038
2039 return_error:
2040 if (info->dma)
2041 dma_release_channel(info->dma);
2042 if (nand_chip->ecc.priv) {
2043 nand_bch_free(nand_chip->ecc.priv);
2044 nand_chip->ecc.priv = NULL;
2045 }
2046 return err;
2047 }
2048
2049 static int omap_nand_remove(struct platform_device *pdev)
2050 {
2051 struct mtd_info *mtd = platform_get_drvdata(pdev);
2052 struct nand_chip *nand_chip = mtd->priv;
2053 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
2054 mtd);
2055 if (nand_chip->ecc.priv) {
2056 nand_bch_free(nand_chip->ecc.priv);
2057 nand_chip->ecc.priv = NULL;
2058 }
2059 if (info->dma)
2060 dma_release_channel(info->dma);
2061 nand_release(mtd);
2062 return 0;
2063 }
2064
2065 static struct platform_driver omap_nand_driver = {
2066 .probe = omap_nand_probe,
2067 .remove = omap_nand_remove,
2068 .driver = {
2069 .name = DRIVER_NAME,
2070 .owner = THIS_MODULE,
2071 },
2072 };
2073
2074 module_platform_driver(omap_nand_driver);
2075
2076 MODULE_ALIAS("platform:" DRIVER_NAME);
2077 MODULE_LICENSE("GPL");
2078 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");
Linux with added FPC-III support