drivers/pinctrl/pinctrl-ipq8064.c

   1 /*
   2  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pinctrl/pinctrl.h>
  19
  20 #include "pinctrl-msm.h"
  21
  22 static const struct pinctrl_pin_desc ipq8064_pins[] = {
  23         PINCTRL_PIN(0, "GPIO_0"),
  24         PINCTRL_PIN(1, "GPIO_1"),
  25         PINCTRL_PIN(2, "GPIO_2"),
  26         PINCTRL_PIN(3, "GPIO_3"),
  27         PINCTRL_PIN(4, "GPIO_4"),
  28         PINCTRL_PIN(5, "GPIO_5"),
  29         PINCTRL_PIN(6, "GPIO_6"),
  30         PINCTRL_PIN(7, "GPIO_7"),
  31         PINCTRL_PIN(8, "GPIO_8"),
  32         PINCTRL_PIN(9, "GPIO_9"),
  33         PINCTRL_PIN(10, "GPIO_10"),
  34         PINCTRL_PIN(11, "GPIO_11"),
  35         PINCTRL_PIN(12, "GPIO_12"),
  36         PINCTRL_PIN(13, "GPIO_13"),
  37         PINCTRL_PIN(14, "GPIO_14"),
  38         PINCTRL_PIN(15, "GPIO_15"),
  39         PINCTRL_PIN(16, "GPIO_16"),
  40         PINCTRL_PIN(17, "GPIO_17"),
  41         PINCTRL_PIN(18, "GPIO_18"),
  42         PINCTRL_PIN(19, "GPIO_19"),
  43         PINCTRL_PIN(20, "GPIO_20"),
  44         PINCTRL_PIN(21, "GPIO_21"),
  45         PINCTRL_PIN(22, "GPIO_22"),
  46         PINCTRL_PIN(23, "GPIO_23"),
  47         PINCTRL_PIN(24, "GPIO_24"),
  48         PINCTRL_PIN(25, "GPIO_25"),
  49         PINCTRL_PIN(26, "GPIO_26"),
  50         PINCTRL_PIN(27, "GPIO_27"),
  51         PINCTRL_PIN(28, "GPIO_28"),
  52         PINCTRL_PIN(29, "GPIO_29"),
  53         PINCTRL_PIN(30, "GPIO_30"),
  54         PINCTRL_PIN(31, "GPIO_31"),
  55         PINCTRL_PIN(32, "GPIO_32"),
  56         PINCTRL_PIN(33, "GPIO_33"),
  57         PINCTRL_PIN(34, "GPIO_34"),
  58         PINCTRL_PIN(35, "GPIO_35"),
  59         PINCTRL_PIN(36, "GPIO_36"),
  60         PINCTRL_PIN(37, "GPIO_37"),
  61         PINCTRL_PIN(38, "GPIO_38"),
  62         PINCTRL_PIN(39, "GPIO_39"),
  63         PINCTRL_PIN(40, "GPIO_40"),
  64         PINCTRL_PIN(41, "GPIO_41"),
  65         PINCTRL_PIN(42, "GPIO_42"),
  66         PINCTRL_PIN(43, "GPIO_43"),
  67         PINCTRL_PIN(44, "GPIO_44"),
  68         PINCTRL_PIN(45, "GPIO_45"),
  69         PINCTRL_PIN(46, "GPIO_46"),
  70         PINCTRL_PIN(47, "GPIO_47"),
  71         PINCTRL_PIN(48, "GPIO_48"),
  72         PINCTRL_PIN(49, "GPIO_49"),
  73         PINCTRL_PIN(50, "GPIO_50"),
  74         PINCTRL_PIN(51, "GPIO_51"),
  75         PINCTRL_PIN(52, "GPIO_52"),
  76         PINCTRL_PIN(53, "GPIO_53"),
  77         PINCTRL_PIN(54, "GPIO_54"),
  78         PINCTRL_PIN(55, "GPIO_55"),
  79         PINCTRL_PIN(56, "GPIO_56"),
  80         PINCTRL_PIN(57, "GPIO_57"),
  81         PINCTRL_PIN(58, "GPIO_58"),
  82         PINCTRL_PIN(59, "GPIO_59"),
  83         PINCTRL_PIN(60, "GPIO_60"),
  84         PINCTRL_PIN(61, "GPIO_61"),
  85         PINCTRL_PIN(62, "GPIO_62"),
  86         PINCTRL_PIN(63, "GPIO_63"),
  87         PINCTRL_PIN(64, "GPIO_64"),
  88         PINCTRL_PIN(65, "GPIO_65"),
  89         PINCTRL_PIN(66, "GPIO_66"),
  90         PINCTRL_PIN(67, "GPIO_67"),
  91         PINCTRL_PIN(68, "GPIO_68"),
  92
  93         PINCTRL_PIN(69, "SDC3_CLK"),
  94         PINCTRL_PIN(70, "SDC3_CMD"),
  95         PINCTRL_PIN(71, "SDC3_DATA"),
  96 };
  97
  98 #define DECLARE_IPQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
  99 DECLARE_IPQ_GPIO_PINS(0);
 100 DECLARE_IPQ_GPIO_PINS(1);
 101 DECLARE_IPQ_GPIO_PINS(2);
 102 DECLARE_IPQ_GPIO_PINS(3);
 103 DECLARE_IPQ_GPIO_PINS(4);
 104 DECLARE_IPQ_GPIO_PINS(5);
 105 DECLARE_IPQ_GPIO_PINS(6);
 106 DECLARE_IPQ_GPIO_PINS(7);
 107 DECLARE_IPQ_GPIO_PINS(8);
 108 DECLARE_IPQ_GPIO_PINS(9);
 109 DECLARE_IPQ_GPIO_PINS(10);
 110 DECLARE_IPQ_GPIO_PINS(11);
 111 DECLARE_IPQ_GPIO_PINS(12);
 112 DECLARE_IPQ_GPIO_PINS(13);
 113 DECLARE_IPQ_GPIO_PINS(14);
 114 DECLARE_IPQ_GPIO_PINS(15);
 115 DECLARE_IPQ_GPIO_PINS(16);
 116 DECLARE_IPQ_GPIO_PINS(17);
 117 DECLARE_IPQ_GPIO_PINS(18);
 118 DECLARE_IPQ_GPIO_PINS(19);
 119 DECLARE_IPQ_GPIO_PINS(20);
 120 DECLARE_IPQ_GPIO_PINS(21);
 121 DECLARE_IPQ_GPIO_PINS(22);
 122 DECLARE_IPQ_GPIO_PINS(23);
 123 DECLARE_IPQ_GPIO_PINS(24);
 124 DECLARE_IPQ_GPIO_PINS(25);
 125 DECLARE_IPQ_GPIO_PINS(26);
 126 DECLARE_IPQ_GPIO_PINS(27);
 127 DECLARE_IPQ_GPIO_PINS(28);
 128 DECLARE_IPQ_GPIO_PINS(29);
 129 DECLARE_IPQ_GPIO_PINS(30);
 130 DECLARE_IPQ_GPIO_PINS(31);
 131 DECLARE_IPQ_GPIO_PINS(32);
 132 DECLARE_IPQ_GPIO_PINS(33);
 133 DECLARE_IPQ_GPIO_PINS(34);
 134 DECLARE_IPQ_GPIO_PINS(35);
 135 DECLARE_IPQ_GPIO_PINS(36);
 136 DECLARE_IPQ_GPIO_PINS(37);
 137 DECLARE_IPQ_GPIO_PINS(38);
 138 DECLARE_IPQ_GPIO_PINS(39);
 139 DECLARE_IPQ_GPIO_PINS(40);
 140 DECLARE_IPQ_GPIO_PINS(41);
 141 DECLARE_IPQ_GPIO_PINS(42);
 142 DECLARE_IPQ_GPIO_PINS(43);
 143 DECLARE_IPQ_GPIO_PINS(44);
 144 DECLARE_IPQ_GPIO_PINS(45);
 145 DECLARE_IPQ_GPIO_PINS(46);
 146 DECLARE_IPQ_GPIO_PINS(47);
 147 DECLARE_IPQ_GPIO_PINS(48);
 148 DECLARE_IPQ_GPIO_PINS(49);
 149 DECLARE_IPQ_GPIO_PINS(50);
 150 DECLARE_IPQ_GPIO_PINS(51);
 151 DECLARE_IPQ_GPIO_PINS(52);
 152 DECLARE_IPQ_GPIO_PINS(53);
 153 DECLARE_IPQ_GPIO_PINS(54);
 154 DECLARE_IPQ_GPIO_PINS(55);
 155 DECLARE_IPQ_GPIO_PINS(56);
 156 DECLARE_IPQ_GPIO_PINS(57);
 157 DECLARE_IPQ_GPIO_PINS(58);
 158 DECLARE_IPQ_GPIO_PINS(59);
 159 DECLARE_IPQ_GPIO_PINS(60);
 160 DECLARE_IPQ_GPIO_PINS(61);
 161 DECLARE_IPQ_GPIO_PINS(62);
 162 DECLARE_IPQ_GPIO_PINS(63);
 163 DECLARE_IPQ_GPIO_PINS(64);
 164 DECLARE_IPQ_GPIO_PINS(65);
 165 DECLARE_IPQ_GPIO_PINS(66);
 166 DECLARE_IPQ_GPIO_PINS(67);
 167 DECLARE_IPQ_GPIO_PINS(68);
 168
 169 static const unsigned int sdc3_clk_pins[] = { 69 };
 170 static const unsigned int sdc3_cmd_pins[] = { 70 };
 171 static const unsigned int sdc3_data_pins[] = { 71 };
 172
 173 #define FUNCTION(fname)                                 \
 174         [IPQ_MUX_##fname] = {                           \
 175                 .name = #fname,                         \
 176                 .groups = fname##_groups,               \
 177                 .ngroups = ARRAY_SIZE(fname##_groups),  \
 178         }
 179
 180 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
 181         {                                               \
 182                 .name = "gpio" #id,                     \
 183                 .pins = gpio##id##_pins,                \
 184                 .npins = ARRAY_SIZE(gpio##id##_pins),   \
 185                 .funcs = (int[]){                       \
 186                         IPQ_MUX_NA, /* gpio mode */     \
 187                         IPQ_MUX_##f1,                   \
 188                         IPQ_MUX_##f2,                   \
 189                         IPQ_MUX_##f3,                   \
 190                         IPQ_MUX_##f4,                   \
 191                         IPQ_MUX_##f5,                   \
 192                         IPQ_MUX_##f6,                   \
 193                         IPQ_MUX_##f7,                   \
 194                         IPQ_MUX_##f8,                   \
 195                         IPQ_MUX_##f9,                   \
 196                         IPQ_MUX_##f10,                  \
 197                 },                                      \
 198                 .nfuncs = 11,                           \
 199                 .ctl_reg = 0x1000 + 0x10 * id,          \
 200                 .io_reg = 0x1004 + 0x10 * id,           \
 201                 .intr_cfg_reg = 0x1008 + 0x10 * id,     \
 202                 .intr_status_reg = 0x100c + 0x10 * id,  \
 203                 .intr_target_reg = 0x400 + 0x4 * id,    \
 204                 .mux_bit = 2,                           \
 205                 .pull_bit = 0,                          \
 206                 .drv_bit = 6,                           \
 207                 .oe_bit = 9,                            \
 208                 .in_bit = 0,                            \
 209                 .out_bit = 1,                           \
 210                 .intr_enable_bit = 0,                   \
 211                 .intr_status_bit = 0,                   \
 212                 .intr_ack_high = 1,                     \
 213                 .intr_target_bit = 0,                   \
 214                 .intr_raw_status_bit = 3,               \
 215                 .intr_polarity_bit = 1,                 \
 216                 .intr_detection_bit = 2,                \
 217                 .intr_detection_width = 1,              \
 218         }
 219
 220 #define SDC_PINGROUP(pg_name, ctl, pull, drv)           \
 221         {                                               \
 222                 .name = #pg_name,                       \
 223                 .pins = pg_name##_pins,                 \
 224                 .npins = ARRAY_SIZE(pg_name##_pins),    \
 225                 .ctl_reg = ctl,                         \
 226                 .io_reg = 0,                            \
 227                 .intr_cfg_reg = 0,                      \
 228                 .intr_status_reg = 0,                   \
 229                 .intr_target_reg = 0,                   \
 230                 .mux_bit = -1,                          \
 231                 .pull_bit = pull,                       \
 232                 .drv_bit = drv,                         \
 233                 .oe_bit = -1,                           \
 234                 .in_bit = -1,                           \
 235                 .out_bit = -1,                          \
 236                 .intr_enable_bit = -1,                  \
 237                 .intr_status_bit = -1,                  \
 238                 .intr_target_bit = -1,                  \
 239                 .intr_raw_status_bit = -1,              \
 240                 .intr_polarity_bit = -1,                \
 241                 .intr_detection_bit = -1,               \
 242                 .intr_detection_width = -1,             \
 243         }
 244
 245 enum ipq8064_functions {
 246         IPQ_MUX_mdio,
 247         IPQ_MUX_mi2s,
 248         IPQ_MUX_pdm,
 249         IPQ_MUX_ssbi,
 250         IPQ_MUX_spmi,
 251         IPQ_MUX_audio_pcm,
 252         IPQ_MUX_gsbi1,
 253         IPQ_MUX_gsbi2,
 254         IPQ_MUX_gsbi4,
 255         IPQ_MUX_gsbi5,
 256         IPQ_MUX_gsbi5_spi_cs1,
 257         IPQ_MUX_gsbi5_spi_cs2,
 258         IPQ_MUX_gsbi5_spi_cs3,
 259         IPQ_MUX_gsbi6,
 260         IPQ_MUX_gsbi7,
 261         IPQ_MUX_nss_spi,
 262         IPQ_MUX_sdc1,
 263         IPQ_MUX_spdif,
 264         IPQ_MUX_nand,
 265         IPQ_MUX_tsif1,
 266         IPQ_MUX_tsif2,
 267         IPQ_MUX_usb_fs_n,
 268         IPQ_MUX_usb_fs,
 269         IPQ_MUX_usb2_hsic,
 270         IPQ_MUX_rgmii2,
 271         IPQ_MUX_sata,
 272         IPQ_MUX_pcie1_rst,
 273         IPQ_MUX_pcie1_prsnt,
 274         IPQ_MUX_pcie1_pwrflt,
 275         IPQ_MUX_pcie1_pwren_n,
 276         IPQ_MUX_pcie1_pwren,
 277         IPQ_MUX_pcie1_clk_req,
 278         IPQ_MUX_pcie2_rst,
 279         IPQ_MUX_pcie2_prsnt,
 280         IPQ_MUX_pcie2_pwrflt,
 281         IPQ_MUX_pcie2_pwren_n,
 282         IPQ_MUX_pcie2_pwren,
 283         IPQ_MUX_pcie2_clk_req,
 284         IPQ_MUX_pcie3_rst,
 285         IPQ_MUX_pcie3_prsnt,
 286         IPQ_MUX_pcie3_pwrflt,
 287         IPQ_MUX_pcie3_pwren_n,
 288         IPQ_MUX_pcie3_pwren,
 289         IPQ_MUX_pcie3_clk_req,
 290         IPQ_MUX_ps_hold,
 291         IPQ_MUX_NA,
 292 };
 293
 294 static const char * const mdio_groups[] = {
 295         "gpio0", "gpio1", "gpio10", "gpio11",
 296 };
 297
 298 static const char * const mi2s_groups[] = {
 299         "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
 300         "gpio33", "gpio55", "gpio56", "gpio57", "gpio58",
 301 };
 302
 303 static const char * const pdm_groups[] = {
 304         "gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31",
 305         "gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58",
 306         "gpio59",
 307 };
 308
 309 static const char * const ssbi_groups[] = {
 310         "gpio10", "gpio11",
 311 };
 312
 313 static const char * const spmi_groups[] = {
 314         "gpio10", "gpio11",
 315 };
 316
 317 static const char * const audio_pcm_groups[] = {
 318         "gpio14", "gpio15", "gpio16", "gpio17",
 319 };
 320
 321 static const char * const gsbi1_groups[] = {
 322         "gpio51", "gpio52", "gpio53", "gpio54",
 323 };
 324
 325 static const char * const gsbi2_groups[] = {
 326         "gpio22", "gpio23", "gpio24", "gpio25",
 327 };
 328
 329 static const char * const gsbi4_groups[] = {
 330         "gpio10", "gpio11", "gpio12", "gpio13",
 331 };
 332
 333 static const char * const gsbi5_groups[] = {
 334         "gpio18", "gpio19", "gpio20", "gpio21",
 335 };
 336
 337 static const char * const gsbi5_spi_cs1_groups[] = {
 338         "gpio6", "gpio61",
 339 };
 340
 341 static const char * const gsbi5_spi_cs2_groups[] = {
 342         "gpio7", "gpio62",
 343 };
 344
 345 static const char * const gsbi5_spi_cs3_groups[] = {
 346         "gpio2",
 347 };
 348
 349 static const char * const gsbi6_groups[] = {
 350         "gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56",
 351         "gpio57", "gpio58",
 352 };
 353
 354 static const char * const gsbi7_groups[] = {
 355         "gpio6", "gpio7", "gpio8", "gpio9",
 356 };
 357
 358 static const char * const nss_spi_groups[] = {
 359         "gpio14", "gpio15", "gpio16", "gpio17", "gpio55", "gpio56",
 360         "gpio57", "gpio58",
 361 };
 362
 363 static const char * const sdc1_groups[] = {
 364         "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
 365         "gpio44", "gpio45", "gpio46", "gpio47",
 366 };
 367
 368 static const char * const spdif_groups[] = {
 369         "gpio10", "gpio48",
 370 };
 371
 372 static const char * const nand_groups[] = {
 373         "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39",
 374         "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
 375         "gpio46", "gpio47",
 376 };
 377
 378 static const char * const tsif1_groups[] = {
 379         "gpio55", "gpio56", "gpio57", "gpio58",
 380 };
 381
 382 static const char * const tsif2_groups[] = {
 383         "gpio59", "gpio60", "gpio61", "gpio62",
 384 };
 385
 386 static const char * const usb_fs_n_groups[] = {
 387         "gpio6",
 388 };
 389
 390 static const char * const usb_fs_groups[] = {
 391         "gpio6", "gpio7", "gpio8",
 392 };
 393
 394 static const char * const usb2_hsic_groups[] = {
 395         "gpio67", "gpio68",
 396 };
 397
 398 static const char * const rgmii2_groups[] = {
 399         "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
 400         "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62",
 401 };
 402
 403 static const char * const sata_groups[] = {
 404         "gpio10",
 405 };
 406
 407 static const char * const pcie1_rst_groups[] = {
 408         "gpio3",
 409 };
 410
 411 static const char * const pcie1_prsnt_groups[] = {
 412         "gpio3", "gpio11",
 413 };
 414
 415 static const char * const pcie1_pwren_n_groups[] = {
 416         "gpio4", "gpio12",
 417 };
 418
 419 static const char * const pcie1_pwren_groups[] = {
 420         "gpio4", "gpio12",
 421 };
 422
 423 static const char * const pcie1_pwrflt_groups[] = {
 424         "gpio5", "gpio13",
 425 };
 426
 427 static const char * const pcie1_clk_req_groups[] = {
 428         "gpio5",
 429 };
 430
 431 static const char * const pcie2_rst_groups[] = {
 432         "gpio48",
 433 };
 434
 435 static const char * const pcie2_prsnt_groups[] = {
 436         "gpio11", "gpio48",
 437 };
 438
 439 static const char * const pcie2_pwren_n_groups[] = {
 440         "gpio12", "gpio49",
 441 };
 442
 443 static const char * const pcie2_pwren_groups[] = {
 444         "gpio12", "gpio49",
 445 };
 446
 447 static const char * const pcie2_pwrflt_groups[] = {
 448         "gpio13", "gpio50",
 449 };
 450
 451 static const char * const pcie2_clk_req_groups[] = {
 452         "gpio50",
 453 };
 454
 455 static const char * const pcie3_rst_groups[] = {
 456         "gpio63",
 457 };
 458
 459 static const char * const pcie3_prsnt_groups[] = {
 460         "gpio11",
 461 };
 462
 463 static const char * const pcie3_pwren_n_groups[] = {
 464         "gpio12",
 465 };
 466
 467 static const char * const pcie3_pwren_groups[] = {
 468         "gpio12",
 469 };
 470
 471 static const char * const pcie3_pwrflt_groups[] = {
 472         "gpio13",
 473 };
 474
 475 static const char * const pcie3_clk_req_groups[] = {
 476         "gpio65",
 477 };
 478
 479 static const char * const ps_hold_groups[] = {
 480         "gpio26",
 481 };
 482
 483 static const struct msm_function ipq8064_functions[] = {
 484         FUNCTION(mdio),
 485         FUNCTION(ssbi),
 486         FUNCTION(spmi),
 487         FUNCTION(mi2s),
 488         FUNCTION(pdm),
 489         FUNCTION(audio_pcm),
 490         FUNCTION(gsbi1),
 491         FUNCTION(gsbi2),
 492         FUNCTION(gsbi4),
 493         FUNCTION(gsbi5),
 494         FUNCTION(gsbi5_spi_cs1),
 495         FUNCTION(gsbi5_spi_cs2),
 496         FUNCTION(gsbi5_spi_cs3),
 497         FUNCTION(gsbi6),
 498         FUNCTION(gsbi7),
 499         FUNCTION(nss_spi),
 500         FUNCTION(sdc1),
 501         FUNCTION(spdif),
 502         FUNCTION(nand),
 503         FUNCTION(tsif1),
 504         FUNCTION(tsif2),
 505         FUNCTION(usb_fs_n),
 506         FUNCTION(usb_fs),
 507         FUNCTION(usb2_hsic),
 508         FUNCTION(rgmii2),
 509         FUNCTION(sata),
 510         FUNCTION(pcie1_rst),
 511         FUNCTION(pcie1_prsnt),
 512         FUNCTION(pcie1_pwren_n),
 513         FUNCTION(pcie1_pwren),
 514         FUNCTION(pcie1_pwrflt),
 515         FUNCTION(pcie1_clk_req),
 516         FUNCTION(pcie2_rst),
 517         FUNCTION(pcie2_prsnt),
 518         FUNCTION(pcie2_pwren_n),
 519         FUNCTION(pcie2_pwren),
 520         FUNCTION(pcie2_pwrflt),
 521         FUNCTION(pcie2_clk_req),
 522         FUNCTION(pcie3_rst),
 523         FUNCTION(pcie3_prsnt),
 524         FUNCTION(pcie3_pwren_n),
 525         FUNCTION(pcie3_pwren),
 526         FUNCTION(pcie3_pwrflt),
 527         FUNCTION(pcie3_clk_req),
 528         FUNCTION(ps_hold),
 529 };
 530
 531 static const struct msm_pingroup ipq8064_groups[] = {
 532         PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 533         PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 534         PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 535         PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA),
 536         PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
 537         PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
 538         PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA),
 539         PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
 540         PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA),
 541         PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 542         PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA),
 543         PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA),
 544         PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA),
 545         PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA),
 546         PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
 547         PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
 548         PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
 549         PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
 550         PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 551         PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 552         PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 553         PINGROUP(21, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 554         PINGROUP(22, gsbi2, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
 555         PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 556         PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 557         PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 558         PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 559         PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
 560         PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
 561         PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
 562         PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA),
 563         PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
 564         PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
 565         PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 566         PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
 567         PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
 568         PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 569         PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 570         PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 571         PINGROUP(39, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 572         PINGROUP(40, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 573         PINGROUP(41, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 574         PINGROUP(42, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 575         PINGROUP(43, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 576         PINGROUP(44, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 577         PINGROUP(45, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 578         PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 579         PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 580         PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA),
 581         PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
 582         PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
 583         PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
 584         PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
 585         PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 586         PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 587         PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
 588         PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
 589         PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA),
 590         PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
 591         PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
 592         PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
 593         PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA),
 594         PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
 595         PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 596         PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 597         PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 598         PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 599         PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 600         PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 601         SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6),
 602         SDC_PINGROUP(sdc3_cmd, 0x204a, 11, 3),
 603         SDC_PINGROUP(sdc3_data, 0x204a, 9, 0),
 604 };
 605
 606 #define NUM_GPIO_PINGROUPS 69
 607
 608 static const struct msm_pinctrl_soc_data ipq8064_pinctrl = {
 609         .pins = ipq8064_pins,
 610         .npins = ARRAY_SIZE(ipq8064_pins),
 611         .functions = ipq8064_functions,
 612         .nfunctions = ARRAY_SIZE(ipq8064_functions),
 613         .groups = ipq8064_groups,
 614         .ngroups = ARRAY_SIZE(ipq8064_groups),
 615         .ngpios = NUM_GPIO_PINGROUPS,
 616 };
 617
 618 static int ipq8064_pinctrl_probe(struct platform_device *pdev)
 619 {
 620         return msm_pinctrl_probe(pdev, &ipq8064_pinctrl);
 621 }
 622
 623 static const struct of_device_id ipq8064_pinctrl_of_match[] = {
 624         { .compatible = "qcom,ipq8064-pinctrl", },
 625         { },
 626 };
 627
 628 static struct platform_driver ipq8064_pinctrl_driver = {
 629         .driver = {
 630                 .name = "ipq8064-pinctrl",
 631                 .owner = THIS_MODULE,
 632                 .of_match_table = ipq8064_pinctrl_of_match,
 633         },
 634         .probe = ipq8064_pinctrl_probe,
 635         .remove = msm_pinctrl_remove,
 636 };
 637
 638 static int __init ipq8064_pinctrl_init(void)
 639 {
 640         return platform_driver_register(&ipq8064_pinctrl_driver);
 641 }
 642 arch_initcall(ipq8064_pinctrl_init);
 643
 644 static void __exit ipq8064_pinctrl_exit(void)
 645 {
 646         platform_driver_unregister(&ipq8064_pinctrl_driver);
 647 }
 648 module_exit(ipq8064_pinctrl_exit);
 649
 650 MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
 651 MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver");
 652 MODULE_LICENSE("GPL v2");
 653 MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match);