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firmware loader: allow disabling of udev as firmware loader
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-rockchip.c
blobbb805d5e9ff066a37275fb3e758d7dbae8ab87c9
1 /*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
26 #include <linux/module.h>
27 #include <linux/platform_device.h>
28 #include <linux/io.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk.h>
40 #include <linux/regmap.h>
41 #include <linux/mfd/syscon.h>
42 #include <dt-bindings/pinctrl/rockchip.h>
43
44 #include "core.h"
45 #include "pinconf.h"
46
47 /* GPIO control registers */
48 #define GPIO_SWPORT_DR 0x00
49 #define GPIO_SWPORT_DDR 0x04
50 #define GPIO_INTEN 0x30
51 #define GPIO_INTMASK 0x34
52 #define GPIO_INTTYPE_LEVEL 0x38
53 #define GPIO_INT_POLARITY 0x3c
54 #define GPIO_INT_STATUS 0x40
55 #define GPIO_INT_RAWSTATUS 0x44
56 #define GPIO_DEBOUNCE 0x48
57 #define GPIO_PORTS_EOI 0x4c
58 #define GPIO_EXT_PORT 0x50
59 #define GPIO_LS_SYNC 0x60
60
61 enum rockchip_pinctrl_type {
62 RK2928,
63 RK3066B,
64 RK3188,
65 };
66
67 enum rockchip_pin_bank_type {
68 COMMON_BANK,
69 RK3188_BANK0,
70 };
71
72 /**
73 * @reg_base: register base of the gpio bank
74 * @reg_pull: optional separate register for additional pull settings
75 * @clk: clock of the gpio bank
76 * @irq: interrupt of the gpio bank
77 * @pin_base: first pin number
78 * @nr_pins: number of pins in this bank
79 * @name: name of the bank
80 * @bank_num: number of the bank, to account for holes
81 * @valid: are all necessary informations present
82 * @of_node: dt node of this bank
83 * @drvdata: common pinctrl basedata
84 * @domain: irqdomain of the gpio bank
85 * @gpio_chip: gpiolib chip
86 * @grange: gpio range
87 * @slock: spinlock for the gpio bank
88 */
89 struct rockchip_pin_bank {
90 void __iomem *reg_base;
91 struct regmap *regmap_pull;
92 struct clk *clk;
93 int irq;
94 u32 pin_base;
95 u8 nr_pins;
96 char *name;
97 u8 bank_num;
98 enum rockchip_pin_bank_type bank_type;
99 bool valid;
100 struct device_node *of_node;
101 struct rockchip_pinctrl *drvdata;
102 struct irq_domain *domain;
103 struct gpio_chip gpio_chip;
104 struct pinctrl_gpio_range grange;
105 spinlock_t slock;
106 u32 toggle_edge_mode;
107 };
108
109 #define PIN_BANK(id, pins, label) \
110 { \
111 .bank_num = id, \
112 .nr_pins = pins, \
113 .name = label, \
114 }
115
116 /**
117 */
118 struct rockchip_pin_ctrl {
119 struct rockchip_pin_bank *pin_banks;
120 u32 nr_banks;
121 u32 nr_pins;
122 char *label;
123 enum rockchip_pinctrl_type type;
124 int mux_offset;
125 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
126 int pin_num, struct regmap **regmap,
127 int *reg, u8 *bit);
128 };
129
130 struct rockchip_pin_config {
131 unsigned int func;
132 unsigned long *configs;
133 unsigned int nconfigs;
134 };
135
136 /**
137 * struct rockchip_pin_group: represent group of pins of a pinmux function.
138 * @name: name of the pin group, used to lookup the group.
139 * @pins: the pins included in this group.
140 * @npins: number of pins included in this group.
141 * @func: the mux function number to be programmed when selected.
142 * @configs: the config values to be set for each pin
143 * @nconfigs: number of configs for each pin
144 */
145 struct rockchip_pin_group {
146 const char *name;
147 unsigned int npins;
148 unsigned int *pins;
149 struct rockchip_pin_config *data;
150 };
151
152 /**
153 * struct rockchip_pmx_func: represent a pin function.
154 * @name: name of the pin function, used to lookup the function.
155 * @groups: one or more names of pin groups that provide this function.
156 * @num_groups: number of groups included in @groups.
157 */
158 struct rockchip_pmx_func {
159 const char *name;
160 const char **groups;
161 u8 ngroups;
162 };
163
164 struct rockchip_pinctrl {
165 struct regmap *regmap_base;
166 int reg_size;
167 struct regmap *regmap_pull;
168 struct regmap *regmap_pmu;
169 struct device *dev;
170 struct rockchip_pin_ctrl *ctrl;
171 struct pinctrl_desc pctl;
172 struct pinctrl_dev *pctl_dev;
173 struct rockchip_pin_group *groups;
174 unsigned int ngroups;
175 struct rockchip_pmx_func *functions;
176 unsigned int nfunctions;
177 };
178
179 static struct regmap_config rockchip_regmap_config = {
180 .reg_bits = 32,
181 .val_bits = 32,
182 .reg_stride = 4,
183 };
184
185 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
186 {
187 return container_of(gc, struct rockchip_pin_bank, gpio_chip);
188 }
189
190 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
191 const struct rockchip_pinctrl *info,
192 const char *name)
193 {
194 int i;
195
196 for (i = 0; i < info->ngroups; i++) {
197 if (!strcmp(info->groups[i].name, name))
198 return &info->groups[i];
199 }
200
201 return NULL;
202 }
203
204 /*
205 * given a pin number that is local to a pin controller, find out the pin bank
206 * and the register base of the pin bank.
207 */
208 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
209 unsigned pin)
210 {
211 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
212
213 while (pin >= (b->pin_base + b->nr_pins))
214 b++;
215
216 return b;
217 }
218
219 static struct rockchip_pin_bank *bank_num_to_bank(
220 struct rockchip_pinctrl *info,
221 unsigned num)
222 {
223 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
224 int i;
225
226 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
227 if (b->bank_num == num)
228 return b;
229 }
230
231 return ERR_PTR(-EINVAL);
232 }
233
234 /*
235 * Pinctrl_ops handling
236 */
237
238 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
239 {
240 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
241
242 return info->ngroups;
243 }
244
245 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
246 unsigned selector)
247 {
248 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
249
250 return info->groups[selector].name;
251 }
252
253 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
254 unsigned selector, const unsigned **pins,
255 unsigned *npins)
256 {
257 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
258
259 if (selector >= info->ngroups)
260 return -EINVAL;
261
262 *pins = info->groups[selector].pins;
263 *npins = info->groups[selector].npins;
264
265 return 0;
266 }
267
268 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
269 struct device_node *np,
270 struct pinctrl_map **map, unsigned *num_maps)
271 {
272 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
273 const struct rockchip_pin_group *grp;
274 struct pinctrl_map *new_map;
275 struct device_node *parent;
276 int map_num = 1;
277 int i;
278
279 /*
280 * first find the group of this node and check if we need to create
281 * config maps for pins
282 */
283 grp = pinctrl_name_to_group(info, np->name);
284 if (!grp) {
285 dev_err(info->dev, "unable to find group for node %s\n",
286 np->name);
287 return -EINVAL;
288 }
289
290 map_num += grp->npins;
291 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
292 GFP_KERNEL);
293 if (!new_map)
294 return -ENOMEM;
295
296 *map = new_map;
297 *num_maps = map_num;
298
299 /* create mux map */
300 parent = of_get_parent(np);
301 if (!parent) {
302 devm_kfree(pctldev->dev, new_map);
303 return -EINVAL;
304 }
305 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
306 new_map[0].data.mux.function = parent->name;
307 new_map[0].data.mux.group = np->name;
308 of_node_put(parent);
309
310 /* create config map */
311 new_map++;
312 for (i = 0; i < grp->npins; i++) {
313 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
314 new_map[i].data.configs.group_or_pin =
315 pin_get_name(pctldev, grp->pins[i]);
316 new_map[i].data.configs.configs = grp->data[i].configs;
317 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
318 }
319
320 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
321 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
322
323 return 0;
324 }
325
326 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
327 struct pinctrl_map *map, unsigned num_maps)
328 {
329 }
330
331 static const struct pinctrl_ops rockchip_pctrl_ops = {
332 .get_groups_count = rockchip_get_groups_count,
333 .get_group_name = rockchip_get_group_name,
334 .get_group_pins = rockchip_get_group_pins,
335 .dt_node_to_map = rockchip_dt_node_to_map,
336 .dt_free_map = rockchip_dt_free_map,
337 };
338
339 /*
340 * Hardware access
341 */
342
343 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
344 {
345 struct rockchip_pinctrl *info = bank->drvdata;
346 unsigned int val;
347 int reg, ret;
348 u8 bit;
349
350 if (bank->bank_type == RK3188_BANK0 && pin < 16)
351 return RK_FUNC_GPIO;
352
353 /* get basic quadrupel of mux registers and the correct reg inside */
354 reg = info->ctrl->mux_offset;
355 reg += bank->bank_num * 0x10;
356 reg += (pin / 8) * 4;
357 bit = (pin % 8) * 2;
358
359 ret = regmap_read(info->regmap_base, reg, &val);
360 if (ret)
361 return ret;
362
363 return ((val >> bit) & 3);
364 }
365
366 /*
367 * Set a new mux function for a pin.
368 *
369 * The register is divided into the upper and lower 16 bit. When changing
370 * a value, the previous register value is not read and changed. Instead
371 * it seems the changed bits are marked in the upper 16 bit, while the
372 * changed value gets set in the same offset in the lower 16 bit.
373 * All pin settings seem to be 2 bit wide in both the upper and lower
374 * parts.
375 * @bank: pin bank to change
376 * @pin: pin to change
377 * @mux: new mux function to set
378 */
379 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
380 {
381 struct rockchip_pinctrl *info = bank->drvdata;
382 int reg, ret;
383 unsigned long flags;
384 u8 bit;
385 u32 data;
386
387 /*
388 * The first 16 pins of rk3188_bank0 are always gpios and do not have
389 * a mux register at all.
390 */
391 if (bank->bank_type == RK3188_BANK0 && pin < 16) {
392 if (mux != RK_FUNC_GPIO) {
393 dev_err(info->dev,
394 "pin %d only supports a gpio mux\n", pin);
395 return -ENOTSUPP;
396 } else {
397 return 0;
398 }
399 }
400
401 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
402 bank->bank_num, pin, mux);
403
404 /* get basic quadrupel of mux registers and the correct reg inside */
405 reg = info->ctrl->mux_offset;
406 reg += bank->bank_num * 0x10;
407 reg += (pin / 8) * 4;
408 bit = (pin % 8) * 2;
409
410 spin_lock_irqsave(&bank->slock, flags);
411
412 data = (3 << (bit + 16));
413 data |= (mux & 3) << bit;
414 ret = regmap_write(info->regmap_base, reg, data);
415
416 spin_unlock_irqrestore(&bank->slock, flags);
417
418 return ret;
419 }
420
421 #define RK2928_PULL_OFFSET 0x118
422 #define RK2928_PULL_PINS_PER_REG 16
423 #define RK2928_PULL_BANK_STRIDE 8
424
425 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
426 int pin_num, struct regmap **regmap,
427 int *reg, u8 *bit)
428 {
429 struct rockchip_pinctrl *info = bank->drvdata;
430
431 *regmap = info->regmap_base;
432 *reg = RK2928_PULL_OFFSET;
433 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
434 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
435
436 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
437 };
438
439 #define RK3188_PULL_OFFSET 0x164
440 #define RK3188_PULL_BITS_PER_PIN 2
441 #define RK3188_PULL_PINS_PER_REG 8
442 #define RK3188_PULL_BANK_STRIDE 16
443 #define RK3188_PULL_PMU_OFFSET 0x64
444
445 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
446 int pin_num, struct regmap **regmap,
447 int *reg, u8 *bit)
448 {
449 struct rockchip_pinctrl *info = bank->drvdata;
450
451 /* The first 12 pins of the first bank are located elsewhere */
452 if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
453 *regmap = info->regmap_pmu ? info->regmap_pmu
454 : bank->regmap_pull;
455 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
456 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
457 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
458 *bit *= RK3188_PULL_BITS_PER_PIN;
459 } else {
460 *regmap = info->regmap_pull ? info->regmap_pull
461 : info->regmap_base;
462 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
463
464 /* correct the offset, as it is the 2nd pull register */
465 *reg -= 4;
466 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
467 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
468
469 /*
470 * The bits in these registers have an inverse ordering
471 * with the lowest pin being in bits 15:14 and the highest
472 * pin in bits 1:0
473 */
474 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
475 *bit *= RK3188_PULL_BITS_PER_PIN;
476 }
477 }
478
479 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
480 {
481 struct rockchip_pinctrl *info = bank->drvdata;
482 struct rockchip_pin_ctrl *ctrl = info->ctrl;
483 struct regmap *regmap;
484 int reg, ret;
485 u8 bit;
486 u32 data;
487
488 /* rk3066b does support any pulls */
489 if (ctrl->type == RK3066B)
490 return PIN_CONFIG_BIAS_DISABLE;
491
492 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
493
494 ret = regmap_read(regmap, reg, &data);
495 if (ret)
496 return ret;
497
498 switch (ctrl->type) {
499 case RK2928:
500 return !(data & BIT(bit))
501 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
502 : PIN_CONFIG_BIAS_DISABLE;
503 case RK3188:
504 data >>= bit;
505 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
506
507 switch (data) {
508 case 0:
509 return PIN_CONFIG_BIAS_DISABLE;
510 case 1:
511 return PIN_CONFIG_BIAS_PULL_UP;
512 case 2:
513 return PIN_CONFIG_BIAS_PULL_DOWN;
514 case 3:
515 return PIN_CONFIG_BIAS_BUS_HOLD;
516 }
517
518 dev_err(info->dev, "unknown pull setting\n");
519 return -EIO;
520 default:
521 dev_err(info->dev, "unsupported pinctrl type\n");
522 return -EINVAL;
523 };
524 }
525
526 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
527 int pin_num, int pull)
528 {
529 struct rockchip_pinctrl *info = bank->drvdata;
530 struct rockchip_pin_ctrl *ctrl = info->ctrl;
531 struct regmap *regmap;
532 int reg, ret;
533 unsigned long flags;
534 u8 bit;
535 u32 data;
536
537 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
538 bank->bank_num, pin_num, pull);
539
540 /* rk3066b does support any pulls */
541 if (ctrl->type == RK3066B)
542 return pull ? -EINVAL : 0;
543
544 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
545
546 switch (ctrl->type) {
547 case RK2928:
548 spin_lock_irqsave(&bank->slock, flags);
549
550 data = BIT(bit + 16);
551 if (pull == PIN_CONFIG_BIAS_DISABLE)
552 data |= BIT(bit);
553 ret = regmap_write(regmap, reg, data);
554
555 spin_unlock_irqrestore(&bank->slock, flags);
556 break;
557 case RK3188:
558 spin_lock_irqsave(&bank->slock, flags);
559
560 /* enable the write to the equivalent lower bits */
561 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
562
563 switch (pull) {
564 case PIN_CONFIG_BIAS_DISABLE:
565 break;
566 case PIN_CONFIG_BIAS_PULL_UP:
567 data |= (1 << bit);
568 break;
569 case PIN_CONFIG_BIAS_PULL_DOWN:
570 data |= (2 << bit);
571 break;
572 case PIN_CONFIG_BIAS_BUS_HOLD:
573 data |= (3 << bit);
574 break;
575 default:
576 spin_unlock_irqrestore(&bank->slock, flags);
577 dev_err(info->dev, "unsupported pull setting %d\n",
578 pull);
579 return -EINVAL;
580 }
581
582 ret = regmap_write(regmap, reg, data);
583
584 spin_unlock_irqrestore(&bank->slock, flags);
585 break;
586 default:
587 dev_err(info->dev, "unsupported pinctrl type\n");
588 return -EINVAL;
589 }
590
591 return ret;
592 }
593
594 /*
595 * Pinmux_ops handling
596 */
597
598 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
599 {
600 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
601
602 return info->nfunctions;
603 }
604
605 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
606 unsigned selector)
607 {
608 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
609
610 return info->functions[selector].name;
611 }
612
613 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
614 unsigned selector, const char * const **groups,
615 unsigned * const num_groups)
616 {
617 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
618
619 *groups = info->functions[selector].groups;
620 *num_groups = info->functions[selector].ngroups;
621
622 return 0;
623 }
624
625 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
626 unsigned group)
627 {
628 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
629 const unsigned int *pins = info->groups[group].pins;
630 const struct rockchip_pin_config *data = info->groups[group].data;
631 struct rockchip_pin_bank *bank;
632 int cnt, ret = 0;
633
634 dev_dbg(info->dev, "enable function %s group %s\n",
635 info->functions[selector].name, info->groups[group].name);
636
637 /*
638 * for each pin in the pin group selected, program the correspoding pin
639 * pin function number in the config register.
640 */
641 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
642 bank = pin_to_bank(info, pins[cnt]);
643 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
644 data[cnt].func);
645 if (ret)
646 break;
647 }
648
649 if (ret) {
650 /* revert the already done pin settings */
651 for (cnt--; cnt >= 0; cnt--)
652 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
653
654 return ret;
655 }
656
657 return 0;
658 }
659
660 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
661 unsigned selector, unsigned group)
662 {
663 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
664 const unsigned int *pins = info->groups[group].pins;
665 struct rockchip_pin_bank *bank;
666 int cnt;
667
668 dev_dbg(info->dev, "disable function %s group %s\n",
669 info->functions[selector].name, info->groups[group].name);
670
671 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
672 bank = pin_to_bank(info, pins[cnt]);
673 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
674 }
675 }
676
677 /*
678 * The calls to gpio_direction_output() and gpio_direction_input()
679 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
680 * function called from the gpiolib interface).
681 */
682 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
683 struct pinctrl_gpio_range *range,
684 unsigned offset, bool input)
685 {
686 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
687 struct rockchip_pin_bank *bank;
688 struct gpio_chip *chip;
689 int pin, ret;
690 u32 data;
691
692 chip = range->gc;
693 bank = gc_to_pin_bank(chip);
694 pin = offset - chip->base;
695
696 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
697 offset, range->name, pin, input ? "input" : "output");
698
699 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
700 if (ret < 0)
701 return ret;
702
703 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
704 /* set bit to 1 for output, 0 for input */
705 if (!input)
706 data |= BIT(pin);
707 else
708 data &= ~BIT(pin);
709 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
710
711 return 0;
712 }
713
714 static const struct pinmux_ops rockchip_pmx_ops = {
715 .get_functions_count = rockchip_pmx_get_funcs_count,
716 .get_function_name = rockchip_pmx_get_func_name,
717 .get_function_groups = rockchip_pmx_get_groups,
718 .enable = rockchip_pmx_enable,
719 .disable = rockchip_pmx_disable,
720 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
721 };
722
723 /*
724 * Pinconf_ops handling
725 */
726
727 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
728 enum pin_config_param pull)
729 {
730 switch (ctrl->type) {
731 case RK2928:
732 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
733 pull == PIN_CONFIG_BIAS_DISABLE);
734 case RK3066B:
735 return pull ? false : true;
736 case RK3188:
737 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
738 }
739
740 return false;
741 }
742
743 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
744 unsigned offset, int value);
745 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
746
747 /* set the pin config settings for a specified pin */
748 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
749 unsigned long *configs, unsigned num_configs)
750 {
751 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
752 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
753 enum pin_config_param param;
754 u16 arg;
755 int i;
756 int rc;
757
758 for (i = 0; i < num_configs; i++) {
759 param = pinconf_to_config_param(configs[i]);
760 arg = pinconf_to_config_argument(configs[i]);
761
762 switch (param) {
763 case PIN_CONFIG_BIAS_DISABLE:
764 rc = rockchip_set_pull(bank, pin - bank->pin_base,
765 param);
766 if (rc)
767 return rc;
768 break;
769 case PIN_CONFIG_BIAS_PULL_UP:
770 case PIN_CONFIG_BIAS_PULL_DOWN:
771 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
772 case PIN_CONFIG_BIAS_BUS_HOLD:
773 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
774 return -ENOTSUPP;
775
776 if (!arg)
777 return -EINVAL;
778
779 rc = rockchip_set_pull(bank, pin - bank->pin_base,
780 param);
781 if (rc)
782 return rc;
783 break;
784 case PIN_CONFIG_OUTPUT:
785 rc = rockchip_gpio_direction_output(&bank->gpio_chip,
786 pin - bank->pin_base,
787 arg);
788 if (rc)
789 return rc;
790 break;
791 default:
792 return -ENOTSUPP;
793 break;
794 }
795 } /* for each config */
796
797 return 0;
798 }
799
800 /* get the pin config settings for a specified pin */
801 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
802 unsigned long *config)
803 {
804 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
805 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
806 enum pin_config_param param = pinconf_to_config_param(*config);
807 u16 arg;
808 int rc;
809
810 switch (param) {
811 case PIN_CONFIG_BIAS_DISABLE:
812 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
813 return -EINVAL;
814
815 arg = 0;
816 break;
817 case PIN_CONFIG_BIAS_PULL_UP:
818 case PIN_CONFIG_BIAS_PULL_DOWN:
819 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
820 case PIN_CONFIG_BIAS_BUS_HOLD:
821 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
822 return -ENOTSUPP;
823
824 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
825 return -EINVAL;
826
827 arg = 1;
828 break;
829 case PIN_CONFIG_OUTPUT:
830 rc = rockchip_get_mux(bank, pin - bank->pin_base);
831 if (rc != RK_FUNC_GPIO)
832 return -EINVAL;
833
834 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
835 if (rc < 0)
836 return rc;
837
838 arg = rc ? 1 : 0;
839 break;
840 default:
841 return -ENOTSUPP;
842 break;
843 }
844
845 *config = pinconf_to_config_packed(param, arg);
846
847 return 0;
848 }
849
850 static const struct pinconf_ops rockchip_pinconf_ops = {
851 .pin_config_get = rockchip_pinconf_get,
852 .pin_config_set = rockchip_pinconf_set,
853 };
854
855 static const struct of_device_id rockchip_bank_match[] = {
856 { .compatible = "rockchip,gpio-bank" },
857 { .compatible = "rockchip,rk3188-gpio-bank0" },
858 {},
859 };
860
861 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
862 struct device_node *np)
863 {
864 struct device_node *child;
865
866 for_each_child_of_node(np, child) {
867 if (of_match_node(rockchip_bank_match, child))
868 continue;
869
870 info->nfunctions++;
871 info->ngroups += of_get_child_count(child);
872 }
873 }
874
875 static int rockchip_pinctrl_parse_groups(struct device_node *np,
876 struct rockchip_pin_group *grp,
877 struct rockchip_pinctrl *info,
878 u32 index)
879 {
880 struct rockchip_pin_bank *bank;
881 int size;
882 const __be32 *list;
883 int num;
884 int i, j;
885 int ret;
886
887 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
888
889 /* Initialise group */
890 grp->name = np->name;
891
892 /*
893 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
894 * do sanity check and calculate pins number
895 */
896 list = of_get_property(np, "rockchip,pins", &size);
897 /* we do not check return since it's safe node passed down */
898 size /= sizeof(*list);
899 if (!size || size % 4) {
900 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
901 return -EINVAL;
902 }
903
904 grp->npins = size / 4;
905
906 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
907 GFP_KERNEL);
908 grp->data = devm_kzalloc(info->dev, grp->npins *
909 sizeof(struct rockchip_pin_config),
910 GFP_KERNEL);
911 if (!grp->pins || !grp->data)
912 return -ENOMEM;
913
914 for (i = 0, j = 0; i < size; i += 4, j++) {
915 const __be32 *phandle;
916 struct device_node *np_config;
917
918 num = be32_to_cpu(*list++);
919 bank = bank_num_to_bank(info, num);
920 if (IS_ERR(bank))
921 return PTR_ERR(bank);
922
923 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
924 grp->data[j].func = be32_to_cpu(*list++);
925
926 phandle = list++;
927 if (!phandle)
928 return -EINVAL;
929
930 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
931 ret = pinconf_generic_parse_dt_config(np_config,
932 &grp->data[j].configs, &grp->data[j].nconfigs);
933 if (ret)
934 return ret;
935 }
936
937 return 0;
938 }
939
940 static int rockchip_pinctrl_parse_functions(struct device_node *np,
941 struct rockchip_pinctrl *info,
942 u32 index)
943 {
944 struct device_node *child;
945 struct rockchip_pmx_func *func;
946 struct rockchip_pin_group *grp;
947 int ret;
948 static u32 grp_index;
949 u32 i = 0;
950
951 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
952
953 func = &info->functions[index];
954
955 /* Initialise function */
956 func->name = np->name;
957 func->ngroups = of_get_child_count(np);
958 if (func->ngroups <= 0)
959 return 0;
960
961 func->groups = devm_kzalloc(info->dev,
962 func->ngroups * sizeof(char *), GFP_KERNEL);
963 if (!func->groups)
964 return -ENOMEM;
965
966 for_each_child_of_node(np, child) {
967 func->groups[i] = child->name;
968 grp = &info->groups[grp_index++];
969 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
970 if (ret)
971 return ret;
972 }
973
974 return 0;
975 }
976
977 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
978 struct rockchip_pinctrl *info)
979 {
980 struct device *dev = &pdev->dev;
981 struct device_node *np = dev->of_node;
982 struct device_node *child;
983 int ret;
984 int i;
985
986 rockchip_pinctrl_child_count(info, np);
987
988 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
989 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
990
991 info->functions = devm_kzalloc(dev, info->nfunctions *
992 sizeof(struct rockchip_pmx_func),
993 GFP_KERNEL);
994 if (!info->functions) {
995 dev_err(dev, "failed to allocate memory for function list\n");
996 return -EINVAL;
997 }
998
999 info->groups = devm_kzalloc(dev, info->ngroups *
1000 sizeof(struct rockchip_pin_group),
1001 GFP_KERNEL);
1002 if (!info->groups) {
1003 dev_err(dev, "failed allocate memory for ping group list\n");
1004 return -EINVAL;
1005 }
1006
1007 i = 0;
1008
1009 for_each_child_of_node(np, child) {
1010 if (of_match_node(rockchip_bank_match, child))
1011 continue;
1012
1013 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1014 if (ret) {
1015 dev_err(&pdev->dev, "failed to parse function\n");
1016 return ret;
1017 }
1018 }
1019
1020 return 0;
1021 }
1022
1023 static int rockchip_pinctrl_register(struct platform_device *pdev,
1024 struct rockchip_pinctrl *info)
1025 {
1026 struct pinctrl_desc *ctrldesc = &info->pctl;
1027 struct pinctrl_pin_desc *pindesc, *pdesc;
1028 struct rockchip_pin_bank *pin_bank;
1029 int pin, bank, ret;
1030 int k;
1031
1032 ctrldesc->name = "rockchip-pinctrl";
1033 ctrldesc->owner = THIS_MODULE;
1034 ctrldesc->pctlops = &rockchip_pctrl_ops;
1035 ctrldesc->pmxops = &rockchip_pmx_ops;
1036 ctrldesc->confops = &rockchip_pinconf_ops;
1037
1038 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1039 info->ctrl->nr_pins, GFP_KERNEL);
1040 if (!pindesc) {
1041 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1042 return -ENOMEM;
1043 }
1044 ctrldesc->pins = pindesc;
1045 ctrldesc->npins = info->ctrl->nr_pins;
1046
1047 pdesc = pindesc;
1048 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1049 pin_bank = &info->ctrl->pin_banks[bank];
1050 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1051 pdesc->number = k;
1052 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1053 pin_bank->name, pin);
1054 pdesc++;
1055 }
1056 }
1057
1058 info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
1059 if (!info->pctl_dev) {
1060 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1061 return -EINVAL;
1062 }
1063
1064 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1065 pin_bank = &info->ctrl->pin_banks[bank];
1066 pin_bank->grange.name = pin_bank->name;
1067 pin_bank->grange.id = bank;
1068 pin_bank->grange.pin_base = pin_bank->pin_base;
1069 pin_bank->grange.base = pin_bank->gpio_chip.base;
1070 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1071 pin_bank->grange.gc = &pin_bank->gpio_chip;
1072 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1073 }
1074
1075 ret = rockchip_pinctrl_parse_dt(pdev, info);
1076 if (ret) {
1077 pinctrl_unregister(info->pctl_dev);
1078 return ret;
1079 }
1080
1081 return 0;
1082 }
1083
1084 /*
1085 * GPIO handling
1086 */
1087
1088 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
1089 {
1090 return pinctrl_request_gpio(chip->base + offset);
1091 }
1092
1093 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
1094 {
1095 pinctrl_free_gpio(chip->base + offset);
1096 }
1097
1098 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1099 {
1100 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1101 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1102 unsigned long flags;
1103 u32 data;
1104
1105 spin_lock_irqsave(&bank->slock, flags);
1106
1107 data = readl(reg);
1108 data &= ~BIT(offset);
1109 if (value)
1110 data |= BIT(offset);
1111 writel(data, reg);
1112
1113 spin_unlock_irqrestore(&bank->slock, flags);
1114 }
1115
1116 /*
1117 * Returns the level of the pin for input direction and setting of the DR
1118 * register for output gpios.
1119 */
1120 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1121 {
1122 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1123 u32 data;
1124
1125 data = readl(bank->reg_base + GPIO_EXT_PORT);
1126 data >>= offset;
1127 data &= 1;
1128 return data;
1129 }
1130
1131 /*
1132 * gpiolib gpio_direction_input callback function. The setting of the pin
1133 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1134 * interface.
1135 */
1136 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
1137 {
1138 return pinctrl_gpio_direction_input(gc->base + offset);
1139 }
1140
1141 /*
1142 * gpiolib gpio_direction_output callback function. The setting of the pin
1143 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1144 * interface.
1145 */
1146 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
1147 unsigned offset, int value)
1148 {
1149 rockchip_gpio_set(gc, offset, value);
1150 return pinctrl_gpio_direction_output(gc->base + offset);
1151 }
1152
1153 /*
1154 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
1155 * and a virtual IRQ, if not already present.
1156 */
1157 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
1158 {
1159 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1160 unsigned int virq;
1161
1162 if (!bank->domain)
1163 return -ENXIO;
1164
1165 virq = irq_create_mapping(bank->domain, offset);
1166
1167 return (virq) ? : -ENXIO;
1168 }
1169
1170 static const struct gpio_chip rockchip_gpiolib_chip = {
1171 .request = rockchip_gpio_request,
1172 .free = rockchip_gpio_free,
1173 .set = rockchip_gpio_set,
1174 .get = rockchip_gpio_get,
1175 .direction_input = rockchip_gpio_direction_input,
1176 .direction_output = rockchip_gpio_direction_output,
1177 .to_irq = rockchip_gpio_to_irq,
1178 .owner = THIS_MODULE,
1179 };
1180
1181 /*
1182 * Interrupt handling
1183 */
1184
1185 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1186 {
1187 struct irq_chip *chip = irq_get_chip(irq);
1188 struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1189 u32 polarity = 0, data = 0;
1190 u32 pend;
1191 bool edge_changed = false;
1192
1193 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1194
1195 chained_irq_enter(chip, desc);
1196
1197 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1198
1199 if (bank->toggle_edge_mode) {
1200 polarity = readl_relaxed(bank->reg_base +
1201 GPIO_INT_POLARITY);
1202 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1203 }
1204
1205 while (pend) {
1206 unsigned int virq;
1207
1208 irq = __ffs(pend);
1209 pend &= ~BIT(irq);
1210 virq = irq_linear_revmap(bank->domain, irq);
1211
1212 if (!virq) {
1213 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1214 continue;
1215 }
1216
1217 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1218
1219 /*
1220 * Triggering IRQ on both rising and falling edge
1221 * needs manual intervention.
1222 */
1223 if (bank->toggle_edge_mode & BIT(irq)) {
1224 if (data & BIT(irq))
1225 polarity &= ~BIT(irq);
1226 else
1227 polarity |= BIT(irq);
1228
1229 edge_changed = true;
1230 }
1231
1232 generic_handle_irq(virq);
1233 }
1234
1235 if (bank->toggle_edge_mode && edge_changed) {
1236 /* Interrupt params should only be set with ints disabled */
1237 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1238 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1239 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1240 writel(data, bank->reg_base + GPIO_INTEN);
1241 }
1242
1243 chained_irq_exit(chip, desc);
1244 }
1245
1246 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1247 {
1248 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1249 struct rockchip_pin_bank *bank = gc->private;
1250 u32 mask = BIT(d->hwirq);
1251 u32 polarity;
1252 u32 level;
1253 u32 data;
1254 int ret;
1255
1256 /* make sure the pin is configured as gpio input */
1257 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1258 if (ret < 0)
1259 return ret;
1260
1261 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1262 data &= ~mask;
1263 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1264
1265 if (type & IRQ_TYPE_EDGE_BOTH)
1266 __irq_set_handler_locked(d->irq, handle_edge_irq);
1267 else
1268 __irq_set_handler_locked(d->irq, handle_level_irq);
1269
1270 irq_gc_lock(gc);
1271
1272 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1273 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1274
1275 switch (type) {
1276 case IRQ_TYPE_EDGE_BOTH:
1277 bank->toggle_edge_mode |= mask;
1278 level |= mask;
1279
1280 /*
1281 * Determine gpio state. If 1 next interrupt should be falling
1282 * otherwise rising.
1283 */
1284 data = readl(bank->reg_base + GPIO_EXT_PORT);
1285 if (data & mask)
1286 polarity &= ~mask;
1287 else
1288 polarity |= mask;
1289 break;
1290 case IRQ_TYPE_EDGE_RISING:
1291 bank->toggle_edge_mode &= ~mask;
1292 level |= mask;
1293 polarity |= mask;
1294 break;
1295 case IRQ_TYPE_EDGE_FALLING:
1296 bank->toggle_edge_mode &= ~mask;
1297 level |= mask;
1298 polarity &= ~mask;
1299 break;
1300 case IRQ_TYPE_LEVEL_HIGH:
1301 bank->toggle_edge_mode &= ~mask;
1302 level &= ~mask;
1303 polarity |= mask;
1304 break;
1305 case IRQ_TYPE_LEVEL_LOW:
1306 bank->toggle_edge_mode &= ~mask;
1307 level &= ~mask;
1308 polarity &= ~mask;
1309 break;
1310 default:
1311 irq_gc_unlock(gc);
1312 return -EINVAL;
1313 }
1314
1315 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1316 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1317
1318 irq_gc_unlock(gc);
1319
1320 return 0;
1321 }
1322
1323 static int rockchip_interrupts_register(struct platform_device *pdev,
1324 struct rockchip_pinctrl *info)
1325 {
1326 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1327 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1328 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1329 struct irq_chip_generic *gc;
1330 int ret;
1331 int i;
1332
1333 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1334 if (!bank->valid) {
1335 dev_warn(&pdev->dev, "bank %s is not valid\n",
1336 bank->name);
1337 continue;
1338 }
1339
1340 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1341 &irq_generic_chip_ops, NULL);
1342 if (!bank->domain) {
1343 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1344 bank->name);
1345 continue;
1346 }
1347
1348 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1349 "rockchip_gpio_irq", handle_level_irq,
1350 clr, 0, IRQ_GC_INIT_MASK_CACHE);
1351 if (ret) {
1352 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1353 bank->name);
1354 irq_domain_remove(bank->domain);
1355 continue;
1356 }
1357
1358 gc = irq_get_domain_generic_chip(bank->domain, 0);
1359 gc->reg_base = bank->reg_base;
1360 gc->private = bank;
1361 gc->chip_types[0].regs.mask = GPIO_INTEN;
1362 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1363 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1364 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1365 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1366 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1367 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1368
1369 irq_set_handler_data(bank->irq, bank);
1370 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1371 }
1372
1373 return 0;
1374 }
1375
1376 static int rockchip_gpiolib_register(struct platform_device *pdev,
1377 struct rockchip_pinctrl *info)
1378 {
1379 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1380 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1381 struct gpio_chip *gc;
1382 int ret;
1383 int i;
1384
1385 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1386 if (!bank->valid) {
1387 dev_warn(&pdev->dev, "bank %s is not valid\n",
1388 bank->name);
1389 continue;
1390 }
1391
1392 bank->gpio_chip = rockchip_gpiolib_chip;
1393
1394 gc = &bank->gpio_chip;
1395 gc->base = bank->pin_base;
1396 gc->ngpio = bank->nr_pins;
1397 gc->dev = &pdev->dev;
1398 gc->of_node = bank->of_node;
1399 gc->label = bank->name;
1400
1401 ret = gpiochip_add(gc);
1402 if (ret) {
1403 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1404 gc->label, ret);
1405 goto fail;
1406 }
1407 }
1408
1409 rockchip_interrupts_register(pdev, info);
1410
1411 return 0;
1412
1413 fail:
1414 for (--i, --bank; i >= 0; --i, --bank) {
1415 if (!bank->valid)
1416 continue;
1417
1418 if (gpiochip_remove(&bank->gpio_chip))
1419 dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1420 bank->gpio_chip.label);
1421 }
1422 return ret;
1423 }
1424
1425 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1426 struct rockchip_pinctrl *info)
1427 {
1428 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1429 struct rockchip_pin_bank *bank = ctrl->pin_banks;
1430 int ret = 0;
1431 int i;
1432
1433 for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1434 if (!bank->valid)
1435 continue;
1436
1437 ret = gpiochip_remove(&bank->gpio_chip);
1438 }
1439
1440 if (ret)
1441 dev_err(&pdev->dev, "gpio chip remove failed\n");
1442
1443 return ret;
1444 }
1445
1446 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1447 struct rockchip_pinctrl *info)
1448 {
1449 struct resource res;
1450 void __iomem *base;
1451
1452 if (of_address_to_resource(bank->of_node, 0, &res)) {
1453 dev_err(info->dev, "cannot find IO resource for bank\n");
1454 return -ENOENT;
1455 }
1456
1457 bank->reg_base = devm_ioremap_resource(info->dev, &res);
1458 if (IS_ERR(bank->reg_base))
1459 return PTR_ERR(bank->reg_base);
1460
1461 /*
1462 * special case, where parts of the pull setting-registers are
1463 * part of the PMU register space
1464 */
1465 if (of_device_is_compatible(bank->of_node,
1466 "rockchip,rk3188-gpio-bank0")) {
1467 struct device_node *node;
1468
1469 bank->bank_type = RK3188_BANK0;
1470
1471 node = of_parse_phandle(bank->of_node->parent,
1472 "rockchip,pmu", 0);
1473 if (!node) {
1474 if (of_address_to_resource(bank->of_node, 1, &res)) {
1475 dev_err(info->dev, "cannot find IO resource for bank\n");
1476 return -ENOENT;
1477 }
1478
1479 base = devm_ioremap_resource(info->dev, &res);
1480 if (IS_ERR(base))
1481 return PTR_ERR(base);
1482 rockchip_regmap_config.max_register =
1483 resource_size(&res) - 4;
1484 rockchip_regmap_config.name =
1485 "rockchip,rk3188-gpio-bank0-pull";
1486 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
1487 base,
1488 &rockchip_regmap_config);
1489 }
1490
1491 } else {
1492 bank->bank_type = COMMON_BANK;
1493 }
1494
1495 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1496
1497 bank->clk = of_clk_get(bank->of_node, 0);
1498 if (IS_ERR(bank->clk))
1499 return PTR_ERR(bank->clk);
1500
1501 return clk_prepare_enable(bank->clk);
1502 }
1503
1504 static const struct of_device_id rockchip_pinctrl_dt_match[];
1505
1506 /* retrieve the soc specific data */
1507 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1508 struct rockchip_pinctrl *d,
1509 struct platform_device *pdev)
1510 {
1511 const struct of_device_id *match;
1512 struct device_node *node = pdev->dev.of_node;
1513 struct device_node *np;
1514 struct rockchip_pin_ctrl *ctrl;
1515 struct rockchip_pin_bank *bank;
1516 int i;
1517
1518 match = of_match_node(rockchip_pinctrl_dt_match, node);
1519 ctrl = (struct rockchip_pin_ctrl *)match->data;
1520
1521 for_each_child_of_node(node, np) {
1522 if (!of_find_property(np, "gpio-controller", NULL))
1523 continue;
1524
1525 bank = ctrl->pin_banks;
1526 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1527 if (!strcmp(bank->name, np->name)) {
1528 bank->of_node = np;
1529
1530 if (!rockchip_get_bank_data(bank, d))
1531 bank->valid = true;
1532
1533 break;
1534 }
1535 }
1536 }
1537
1538 bank = ctrl->pin_banks;
1539 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1540 spin_lock_init(&bank->slock);
1541 bank->drvdata = d;
1542 bank->pin_base = ctrl->nr_pins;
1543 ctrl->nr_pins += bank->nr_pins;
1544 }
1545
1546 return ctrl;
1547 }
1548
1549 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1550 {
1551 struct rockchip_pinctrl *info;
1552 struct device *dev = &pdev->dev;
1553 struct rockchip_pin_ctrl *ctrl;
1554 struct device_node *np = pdev->dev.of_node, *node;
1555 struct resource *res;
1556 void __iomem *base;
1557 int ret;
1558
1559 if (!dev->of_node) {
1560 dev_err(dev, "device tree node not found\n");
1561 return -ENODEV;
1562 }
1563
1564 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1565 if (!info)
1566 return -ENOMEM;
1567
1568 info->dev = dev;
1569
1570 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1571 if (!ctrl) {
1572 dev_err(dev, "driver data not available\n");
1573 return -EINVAL;
1574 }
1575 info->ctrl = ctrl;
1576
1577 node = of_parse_phandle(np, "rockchip,grf", 0);
1578 if (node) {
1579 info->regmap_base = syscon_node_to_regmap(node);
1580 if (IS_ERR(info->regmap_base))
1581 return PTR_ERR(info->regmap_base);
1582 } else {
1583 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1584 base = devm_ioremap_resource(&pdev->dev, res);
1585 if (IS_ERR(base))
1586 return PTR_ERR(base);
1587
1588 rockchip_regmap_config.max_register = resource_size(res) - 4;
1589 rockchip_regmap_config.name = "rockchip,pinctrl";
1590 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
1591 &rockchip_regmap_config);
1592
1593 /* to check for the old dt-bindings */
1594 info->reg_size = resource_size(res);
1595
1596 /* Honor the old binding, with pull registers as 2nd resource */
1597 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
1598 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1599 base = devm_ioremap_resource(&pdev->dev, res);
1600 if (IS_ERR(base))
1601 return PTR_ERR(base);
1602
1603 rockchip_regmap_config.max_register =
1604 resource_size(res) - 4;
1605 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
1606 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
1607 base,
1608 &rockchip_regmap_config);
1609 }
1610 }
1611
1612 /* try to find the optional reference to the pmu syscon */
1613 node = of_parse_phandle(np, "rockchip,pmu", 0);
1614 if (node) {
1615 info->regmap_pmu = syscon_node_to_regmap(node);
1616 if (IS_ERR(info->regmap_pmu))
1617 return PTR_ERR(info->regmap_pmu);
1618 }
1619
1620 ret = rockchip_gpiolib_register(pdev, info);
1621 if (ret)
1622 return ret;
1623
1624 ret = rockchip_pinctrl_register(pdev, info);
1625 if (ret) {
1626 rockchip_gpiolib_unregister(pdev, info);
1627 return ret;
1628 }
1629
1630 platform_set_drvdata(pdev, info);
1631
1632 return 0;
1633 }
1634
1635 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1636 PIN_BANK(0, 32, "gpio0"),
1637 PIN_BANK(1, 32, "gpio1"),
1638 PIN_BANK(2, 32, "gpio2"),
1639 PIN_BANK(3, 32, "gpio3"),
1640 };
1641
1642 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1643 .pin_banks = rk2928_pin_banks,
1644 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
1645 .label = "RK2928-GPIO",
1646 .type = RK2928,
1647 .mux_offset = 0xa8,
1648 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
1649 };
1650
1651 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1652 PIN_BANK(0, 32, "gpio0"),
1653 PIN_BANK(1, 32, "gpio1"),
1654 PIN_BANK(2, 32, "gpio2"),
1655 PIN_BANK(3, 32, "gpio3"),
1656 PIN_BANK(4, 32, "gpio4"),
1657 PIN_BANK(6, 16, "gpio6"),
1658 };
1659
1660 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1661 .pin_banks = rk3066a_pin_banks,
1662 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
1663 .label = "RK3066a-GPIO",
1664 .type = RK2928,
1665 .mux_offset = 0xa8,
1666 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
1667 };
1668
1669 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1670 PIN_BANK(0, 32, "gpio0"),
1671 PIN_BANK(1, 32, "gpio1"),
1672 PIN_BANK(2, 32, "gpio2"),
1673 PIN_BANK(3, 32, "gpio3"),
1674 };
1675
1676 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1677 .pin_banks = rk3066b_pin_banks,
1678 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
1679 .label = "RK3066b-GPIO",
1680 .type = RK3066B,
1681 .mux_offset = 0x60,
1682 };
1683
1684 static struct rockchip_pin_bank rk3188_pin_banks[] = {
1685 PIN_BANK(0, 32, "gpio0"),
1686 PIN_BANK(1, 32, "gpio1"),
1687 PIN_BANK(2, 32, "gpio2"),
1688 PIN_BANK(3, 32, "gpio3"),
1689 };
1690
1691 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1692 .pin_banks = rk3188_pin_banks,
1693 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
1694 .label = "RK3188-GPIO",
1695 .type = RK3188,
1696 .mux_offset = 0x60,
1697 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
1698 };
1699
1700 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1701 { .compatible = "rockchip,rk2928-pinctrl",
1702 .data = (void *)&rk2928_pin_ctrl },
1703 { .compatible = "rockchip,rk3066a-pinctrl",
1704 .data = (void *)&rk3066a_pin_ctrl },
1705 { .compatible = "rockchip,rk3066b-pinctrl",
1706 .data = (void *)&rk3066b_pin_ctrl },
1707 { .compatible = "rockchip,rk3188-pinctrl",
1708 .data = (void *)&rk3188_pin_ctrl },
1709 {},
1710 };
1711 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1712
1713 static struct platform_driver rockchip_pinctrl_driver = {
1714 .probe = rockchip_pinctrl_probe,
1715 .driver = {
1716 .name = "rockchip-pinctrl",
1717 .owner = THIS_MODULE,
1718 .of_match_table = rockchip_pinctrl_dt_match,
1719 },
1720 };
1721
1722 static int __init rockchip_pinctrl_drv_register(void)
1723 {
1724 return platform_driver_register(&rockchip_pinctrl_driver);
1725 }
1726 postcore_initcall(rockchip_pinctrl_drv_register);
1727
1728 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1729 MODULE_DESCRIPTION("Rockchip pinctrl driver");
1730 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support