drivers/scsi/be2iscsi/be_main.h

   1 /**
   2  * Copyright (C) 2005 - 2013 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11  *
  12  * Contact Information:
  13  * linux-drivers@emulex.com
  14  *
  15  * Emulex
  16  * 3333 Susan Street
  17  * Costa Mesa, CA 92626
  18  */
  19
  20 #ifndef _BEISCSI_MAIN_
  21 #define _BEISCSI_MAIN_
  22
  23 #include <linux/kernel.h>
  24 #include <linux/pci.h>
  25 #include <linux/if_ether.h>
  26 #include <linux/in.h>
  27 #include <linux/ctype.h>
  28 #include <linux/module.h>
  29 #include <linux/aer.h>
  30 #include <scsi/scsi.h>
  31 #include <scsi/scsi_cmnd.h>
  32 #include <scsi/scsi_device.h>
  33 #include <scsi/scsi_host.h>
  34 #include <scsi/iscsi_proto.h>
  35 #include <scsi/libiscsi.h>
  36 #include <scsi/scsi_transport_iscsi.h>
  37
  38 #define DRV_NAME                "be2iscsi"
  39 #define BUILD_STR               "10.2.273.0"
  40 #define BE_NAME                 "Emulex OneConnect" \
  41                                 "Open-iSCSI Driver version" BUILD_STR
  42 #define DRV_DESC                BE_NAME " " "Driver"
  43
  44 #define BE_VENDOR_ID            0x19A2
  45 #define ELX_VENDOR_ID           0x10DF
  46 /* DEVICE ID's for BE2 */
  47 #define BE_DEVICE_ID1           0x212
  48 #define OC_DEVICE_ID1           0x702
  49 #define OC_DEVICE_ID2           0x703
  50
  51 /* DEVICE ID's for BE3 */
  52 #define BE_DEVICE_ID2           0x222
  53 #define OC_DEVICE_ID3           0x712
  54
  55 /* DEVICE ID for SKH */
  56 #define OC_SKH_ID1              0x722
  57
  58 #define BE2_IO_DEPTH            1024
  59 #define BE2_MAX_SESSIONS        256
  60 #define BE2_CMDS_PER_CXN        128
  61 #define BE2_TMFS                16
  62 #define BE2_NOPOUT_REQ          16
  63 #define BE2_SGE                 32
  64 #define BE2_DEFPDU_HDR_SZ       64
  65 #define BE2_DEFPDU_DATA_SZ      8192
  66
  67 #define MAX_CPUS                64
  68 #define BEISCSI_MAX_NUM_CPUS    7
  69
  70 #define BEISCSI_VER_STRLEN 32
  71
  72 #define BEISCSI_SGLIST_ELEMENTS 30
  73
  74 #define BEISCSI_CMD_PER_LUN     128 /* scsi_host->cmd_per_lun */
  75 #define BEISCSI_MAX_SECTORS     1024 /* scsi_host->max_sectors */
  76 #define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
  77
  78 #define BEISCSI_MAX_CMD_LEN     16      /* scsi_host->max_cmd_len */
  79 #define BEISCSI_NUM_MAX_LUN     256     /* scsi_host->max_lun */
  80 #define BEISCSI_NUM_DEVICES_SUPPORTED   0x01
  81 #define BEISCSI_MAX_FRAGS_INIT  192
  82 #define BE_NUM_MSIX_ENTRIES     1
  83
  84 #define MPU_EP_CONTROL          0
  85 #define MPU_EP_SEMAPHORE        0xac
  86 #define BE2_SOFT_RESET          0x5c
  87 #define BE2_PCI_ONLINE0         0xb0
  88 #define BE2_PCI_ONLINE1         0xb4
  89 #define BE2_SET_RESET           0x80
  90 #define BE2_MPU_IRAM_ONLINE     0x00000080
  91
  92 #define BE_SENSE_INFO_SIZE              258
  93 #define BE_ISCSI_PDU_HEADER_SIZE        64
  94 #define BE_MIN_MEM_SIZE                 16384
  95 #define MAX_CMD_SZ                      65536
  96 #define IIOC_SCSI_DATA                  0x05    /* Write Operation */
  97
  98 #define INVALID_SESS_HANDLE     0xFFFFFFFF
  99
 100 /**
 101  * Adapter States
 102  **/
 103 #define BE_ADAPTER_LINK_UP      0x001
 104 #define BE_ADAPTER_LINK_DOWN    0x002
 105 #define BE_ADAPTER_PCI_ERR      0x004
 106 #define BE_ADAPTER_STATE_SHUTDOWN       0x008
 107
 108
 109 #define BEISCSI_CLEAN_UNLOAD    0x01
 110 #define BEISCSI_EEH_UNLOAD      0x02
 111 /**
 112  * hardware needs the async PDU buffers to be posted in multiples of 8
 113  * So have atleast 8 of them by default
 114  */
 115
 116 #define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num)    \
 117         (phwi->phwi_ctxt->pasync_ctx[ulp_num])
 118
 119 /********* Memory BAR register ************/
 120 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET      0xfc
 121 /**
 122  * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
 123  * Disable" may still globally block interrupts in addition to individual
 124  * interrupt masks; a mechanism for the device driver to block all interrupts
 125  * atomically without having to arbitrate for the PCI Interrupt Disable bit
 126  * with the OS.
 127  */
 128 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK      (1 << 29)       /* bit 29 */
 129
 130 /********* ISR0 Register offset **********/
 131 #define CEV_ISR0_OFFSET                         0xC18
 132 #define CEV_ISR_SIZE                            4
 133
 134 /**
 135  * Macros for reading/writing a protection domain or CSR registers
 136  * in BladeEngine.
 137  */
 138
 139 #define DB_TXULP0_OFFSET 0x40
 140 #define DB_RXULP0_OFFSET 0xA0
 141 /********* Event Q door bell *************/
 142 #define DB_EQ_OFFSET                    DB_CQ_OFFSET
 143 #define DB_EQ_RING_ID_LOW_MASK          0x1FF   /* bits 0 - 8 */
 144 /* Clear the interrupt for this eq */
 145 #define DB_EQ_CLR_SHIFT                 (9)     /* bit 9 */
 146 /* Must be 1 */
 147 #define DB_EQ_EVNT_SHIFT                (10)    /* bit 10 */
 148 /* Higher Order EQ_ID bit */
 149 #define DB_EQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
 150 #define DB_EQ_HIGH_SET_SHIFT    11
 151 #define DB_EQ_HIGH_FEILD_SHIFT  9
 152 /* Number of event entries processed */
 153 #define DB_EQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 154 /* Rearm bit */
 155 #define DB_EQ_REARM_SHIFT               (29)    /* bit 29 */
 156
 157 /********* Compl Q door bell *************/
 158 #define DB_CQ_OFFSET                    0x120
 159 #define DB_CQ_RING_ID_LOW_MASK          0x3FF   /* bits 0 - 9 */
 160 /* Higher Order CQ_ID bit */
 161 #define DB_CQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
 162 #define DB_CQ_HIGH_SET_SHIFT    11
 163 #define DB_CQ_HIGH_FEILD_SHIFT  10
 164
 165 /* Number of event entries processed */
 166 #define DB_CQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 167 /* Rearm bit */
 168 #define DB_CQ_REARM_SHIFT               (29)    /* bit 29 */
 169
 170 #define GET_HWI_CONTROLLER_WS(pc)       (pc->phwi_ctrlr)
 171 #define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
 172                 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
 173 #define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
 174                 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
 175
 176 #define PAGES_REQUIRED(x) \
 177         ((x < PAGE_SIZE) ? 1 :  ((x + PAGE_SIZE - 1) / PAGE_SIZE))
 178
 179 #define BEISCSI_MSI_NAME 20 /* size of msi_name string */
 180
 181 #define MEM_DESCR_OFFSET 8
 182 #define BEISCSI_DEFQ_HDR 1
 183 #define BEISCSI_DEFQ_DATA 0
 184 enum be_mem_enum {
 185         HWI_MEM_ADDN_CONTEXT,
 186         HWI_MEM_WRB,
 187         HWI_MEM_WRBH,
 188         HWI_MEM_SGLH,
 189         HWI_MEM_SGE,
 190         HWI_MEM_TEMPLATE_HDR_ULP0,
 191         HWI_MEM_ASYNC_HEADER_BUF_ULP0,  /* 6 */
 192         HWI_MEM_ASYNC_DATA_BUF_ULP0,
 193         HWI_MEM_ASYNC_HEADER_RING_ULP0,
 194         HWI_MEM_ASYNC_DATA_RING_ULP0,
 195         HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
 196         HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
 197         HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
 198         HWI_MEM_TEMPLATE_HDR_ULP1,
 199         HWI_MEM_ASYNC_HEADER_BUF_ULP1,  /* 14 */
 200         HWI_MEM_ASYNC_DATA_BUF_ULP1,
 201         HWI_MEM_ASYNC_HEADER_RING_ULP1,
 202         HWI_MEM_ASYNC_DATA_RING_ULP1,
 203         HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
 204         HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
 205         HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
 206         ISCSI_MEM_GLOBAL_HEADER,
 207         SE_MEM_MAX
 208 };
 209
 210 struct be_bus_address32 {
 211         unsigned int address_lo;
 212         unsigned int address_hi;
 213 };
 214
 215 struct be_bus_address64 {
 216         unsigned long long address;
 217 };
 218
 219 struct be_bus_address {
 220         union {
 221                 struct be_bus_address32 a32;
 222                 struct be_bus_address64 a64;
 223         } u;
 224 };
 225
 226 struct mem_array {
 227         struct be_bus_address bus_address;      /* Bus address of location */
 228         void *virtual_address;          /* virtual address to the location */
 229         unsigned int size;              /* Size required by memory block */
 230 };
 231
 232 struct be_mem_descriptor {
 233         unsigned int index;     /* Index of this memory parameter */
 234         unsigned int category;  /* type indicates cached/non-cached */
 235         unsigned int num_elements;      /* number of elements in this
 236                                          * descriptor
 237                                          */
 238         unsigned int alignment_mask;    /* Alignment mask for this block */
 239         unsigned int size_in_bytes;     /* Size required by memory block */
 240         struct mem_array *mem_array;
 241 };
 242
 243 struct sgl_handle {
 244         unsigned int sgl_index;
 245         unsigned int type;
 246         unsigned int cid;
 247         struct iscsi_task *task;
 248         struct iscsi_sge *pfrag;
 249 };
 250
 251 struct hba_parameters {
 252         unsigned int ios_per_ctrl;
 253         unsigned int cxns_per_ctrl;
 254         unsigned int asyncpdus_per_ctrl;
 255         unsigned int icds_per_ctrl;
 256         unsigned int num_sge_per_io;
 257         unsigned int defpdu_hdr_sz;
 258         unsigned int defpdu_data_sz;
 259         unsigned int num_cq_entries;
 260         unsigned int num_eq_entries;
 261         unsigned int wrbs_per_cxn;
 262         unsigned int crashmode;
 263         unsigned int hba_num;
 264
 265         unsigned int mgmt_ws_sz;
 266         unsigned int hwi_ws_sz;
 267
 268         unsigned int eto;
 269         unsigned int ldto;
 270
 271         unsigned int dbg_flags;
 272         unsigned int num_cxn;
 273
 274         unsigned int eq_timer;
 275         /**
 276          * These are calculated from other params. They're here
 277          * for debug purposes
 278          */
 279         unsigned int num_mcc_pages;
 280         unsigned int num_mcc_cq_pages;
 281         unsigned int num_cq_pages;
 282         unsigned int num_eq_pages;
 283
 284         unsigned int num_async_pdu_buf_pages;
 285         unsigned int num_async_pdu_buf_sgl_pages;
 286         unsigned int num_async_pdu_buf_cq_pages;
 287
 288         unsigned int num_async_pdu_hdr_pages;
 289         unsigned int num_async_pdu_hdr_sgl_pages;
 290         unsigned int num_async_pdu_hdr_cq_pages;
 291
 292         unsigned int num_sge;
 293 };
 294
 295 struct invalidate_command_table {
 296         unsigned short icd;
 297         unsigned short cid;
 298 } __packed;
 299
 300 #define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
 301         (phwi_ctrlr->wrb_context[cri].ulp_num)
 302 struct hwi_wrb_context {
 303         struct list_head wrb_handle_list;
 304         struct list_head wrb_handle_drvr_list;
 305         struct wrb_handle **pwrb_handle_base;
 306         struct wrb_handle **pwrb_handle_basestd;
 307         struct iscsi_wrb *plast_wrb;
 308         unsigned short alloc_index;
 309         unsigned short free_index;
 310         unsigned short wrb_handles_available;
 311         unsigned short cid;
 312         uint8_t ulp_num;        /* ULP to which CID binded */
 313         uint16_t register_set;
 314         uint16_t doorbell_format;
 315         uint32_t doorbell_offset;
 316 };
 317
 318 struct ulp_cid_info {
 319         unsigned short *cid_array;
 320         unsigned short avlbl_cids;
 321         unsigned short cid_alloc;
 322         unsigned short cid_free;
 323 };
 324
 325 #include "be.h"
 326 #define chip_be2(phba)      (phba->generation == BE_GEN2)
 327 #define chip_be3_r(phba)    (phba->generation == BE_GEN3)
 328 #define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
 329
 330 #define BEISCSI_ULP0    0
 331 #define BEISCSI_ULP1    1
 332 #define BEISCSI_ULP_COUNT   2
 333 #define BEISCSI_ULP0_LOADED 0x01
 334 #define BEISCSI_ULP1_LOADED 0x02
 335
 336 #define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \
 337         (((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids)
 338 #define BEISCSI_ULP0_AVLBL_CID(phba) \
 339         BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0)
 340 #define BEISCSI_ULP1_AVLBL_CID(phba) \
 341         BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1)
 342
 343 struct beiscsi_hba {
 344         struct hba_parameters params;
 345         struct hwi_controller *phwi_ctrlr;
 346         unsigned int mem_req[SE_MEM_MAX];
 347         /* PCI BAR mapped addresses */
 348         u8 __iomem *csr_va;     /* CSR */
 349         u8 __iomem *db_va;      /* Door  Bell  */
 350         u8 __iomem *pci_va;     /* PCI Config */
 351         struct be_bus_address csr_pa;   /* CSR */
 352         struct be_bus_address db_pa;    /* CSR */
 353         struct be_bus_address pci_pa;   /* CSR */
 354         /* PCI representation of our HBA */
 355         struct pci_dev *pcidev;
 356         unsigned short asic_revision;
 357         unsigned int num_cpus;
 358         unsigned int nxt_cqid;
 359         struct msix_entry msix_entries[MAX_CPUS];
 360         char *msi_name[MAX_CPUS];
 361         bool msix_enabled;
 362         struct be_mem_descriptor *init_mem;
 363
 364         unsigned short io_sgl_alloc_index;
 365         unsigned short io_sgl_free_index;
 366         unsigned short io_sgl_hndl_avbl;
 367         struct sgl_handle **io_sgl_hndl_base;
 368         struct sgl_handle **sgl_hndl_array;
 369
 370         unsigned short eh_sgl_alloc_index;
 371         unsigned short eh_sgl_free_index;
 372         unsigned short eh_sgl_hndl_avbl;
 373         struct sgl_handle **eh_sgl_hndl_base;
 374         spinlock_t io_sgl_lock;
 375         spinlock_t mgmt_sgl_lock;
 376         spinlock_t isr_lock;
 377         spinlock_t async_pdu_lock;
 378         unsigned int age;
 379         struct list_head hba_queue;
 380 #define BE_MAX_SESSION 2048
 381 #define BE_SET_CID_TO_CRI(cri_index, cid) \
 382                           (phba->cid_to_cri_map[cid] = cri_index)
 383 #define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
 384         unsigned short cid_to_cri_map[BE_MAX_SESSION];
 385         struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT];
 386         struct iscsi_endpoint **ep_array;
 387         struct beiscsi_conn **conn_table;
 388         struct iscsi_boot_kset *boot_kset;
 389         struct Scsi_Host *shost;
 390         struct iscsi_iface *ipv4_iface;
 391         struct iscsi_iface *ipv6_iface;
 392         struct {
 393                 /**
 394                  * group together since they are used most frequently
 395                  * for cid to cri conversion
 396                  */
 397                 unsigned int phys_port;
 398                 unsigned int eqid_count;
 399                 unsigned int cqid_count;
 400                 unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
 401 #define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
 402                 (phba->fw_config.iscsi_cid_count[ulp_num])
 403                 unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
 404                 unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
 405                 unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
 406                 unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
 407                 unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
 408
 409                 unsigned short iscsi_features;
 410                 uint16_t dual_ulp_aware;
 411                 unsigned long ulp_supported;
 412         } fw_config;
 413
 414         unsigned int state;
 415         bool fw_timeout;
 416         bool ue_detected;
 417         struct delayed_work beiscsi_hw_check_task;
 418
 419         bool mac_addr_set;
 420         u8 mac_address[ETH_ALEN];
 421         char fw_ver_str[BEISCSI_VER_STRLEN];
 422         char wq_name[20];
 423         struct workqueue_struct *wq;    /* The actuak work queue */
 424         struct be_ctrl_info ctrl;
 425         unsigned int generation;
 426         unsigned int interface_handle;
 427         struct mgmt_session_info boot_sess;
 428         struct invalidate_command_table inv_tbl[128];
 429
 430         struct be_aic_obj aic_obj[MAX_CPUS];
 431         unsigned int attr_log_enable;
 432         int (*iotask_fn)(struct iscsi_task *,
 433                         struct scatterlist *sg,
 434                         uint32_t num_sg, uint32_t xferlen,
 435                         uint32_t writedir);
 436 };
 437
 438 struct beiscsi_session {
 439         struct pci_pool *bhs_pool;
 440 };
 441
 442 /**
 443  * struct beiscsi_conn - iscsi connection structure
 444  */
 445 struct beiscsi_conn {
 446         struct iscsi_conn *conn;
 447         struct beiscsi_hba *phba;
 448         u32 exp_statsn;
 449         u32 doorbell_offset;
 450         u32 beiscsi_conn_cid;
 451         struct beiscsi_endpoint *ep;
 452         unsigned short login_in_progress;
 453         struct wrb_handle *plogin_wrb_handle;
 454         struct sgl_handle *plogin_sgl_handle;
 455         struct beiscsi_session *beiscsi_sess;
 456         struct iscsi_task *task;
 457 };
 458
 459 /* This structure is used by the chip */
 460 struct pdu_data_out {
 461         u32 dw[12];
 462 };
 463 /**
 464  * Pseudo amap definition in which each bit of the actual structure is defined
 465  * as a byte: used to calculate offset/shift/mask of each field
 466  */
 467 struct amap_pdu_data_out {
 468         u8 opcode[6];           /* opcode */
 469         u8 rsvd0[2];            /* should be 0 */
 470         u8 rsvd1[7];
 471         u8 final_bit;           /* F bit */
 472         u8 rsvd2[16];
 473         u8 ahs_length[8];       /* no AHS */
 474         u8 data_len_hi[8];
 475         u8 data_len_lo[16];     /* DataSegmentLength */
 476         u8 lun[64];
 477         u8 itt[32];             /* ITT; initiator task tag */
 478         u8 ttt[32];             /* TTT; valid for R2T or 0xffffffff */
 479         u8 rsvd3[32];
 480         u8 exp_stat_sn[32];
 481         u8 rsvd4[32];
 482         u8 data_sn[32];
 483         u8 buffer_offset[32];
 484         u8 rsvd5[32];
 485 };
 486
 487 struct be_cmd_bhs {
 488         struct iscsi_scsi_req iscsi_hdr;
 489         unsigned char pad1[16];
 490         struct pdu_data_out iscsi_data_pdu;
 491         unsigned char pad2[BE_SENSE_INFO_SIZE -
 492                         sizeof(struct pdu_data_out)];
 493 };
 494
 495 struct beiscsi_io_task {
 496         struct wrb_handle *pwrb_handle;
 497         struct sgl_handle *psgl_handle;
 498         struct beiscsi_conn *conn;
 499         struct scsi_cmnd *scsi_cmnd;
 500         unsigned int cmd_sn;
 501         unsigned int flags;
 502         unsigned short cid;
 503         unsigned short header_len;
 504         itt_t libiscsi_itt;
 505         struct be_cmd_bhs *cmd_bhs;
 506         struct be_bus_address bhs_pa;
 507         unsigned short bhs_len;
 508         dma_addr_t mtask_addr;
 509         uint32_t mtask_data_count;
 510         uint8_t wrb_type;
 511 };
 512
 513 struct be_nonio_bhs {
 514         struct iscsi_hdr iscsi_hdr;
 515         unsigned char pad1[16];
 516         struct pdu_data_out iscsi_data_pdu;
 517         unsigned char pad2[BE_SENSE_INFO_SIZE -
 518                         sizeof(struct pdu_data_out)];
 519 };
 520
 521 struct be_status_bhs {
 522         struct iscsi_scsi_req iscsi_hdr;
 523         unsigned char pad1[16];
 524         /**
 525          * The plus 2 below is to hold the sense info length that gets
 526          * DMA'ed by RxULP
 527          */
 528         unsigned char sense_info[BE_SENSE_INFO_SIZE];
 529 };
 530
 531 struct iscsi_sge {
 532         u32 dw[4];
 533 };
 534
 535 /**
 536  * Pseudo amap definition in which each bit of the actual structure is defined
 537  * as a byte: used to calculate offset/shift/mask of each field
 538  */
 539 struct amap_iscsi_sge {
 540         u8 addr_hi[32];
 541         u8 addr_lo[32];
 542         u8 sge_offset[22];      /* DWORD 2 */
 543         u8 rsvd0[9];            /* DWORD 2 */
 544         u8 last_sge;            /* DWORD 2 */
 545         u8 len[17];             /* DWORD 3 */
 546         u8 rsvd1[15];           /* DWORD 3 */
 547 };
 548
 549 struct beiscsi_offload_params {
 550         u32 dw[6];
 551 };
 552
 553 #define OFFLD_PARAMS_ERL        0x00000003
 554 #define OFFLD_PARAMS_DDE        0x00000004
 555 #define OFFLD_PARAMS_HDE        0x00000008
 556 #define OFFLD_PARAMS_IR2T       0x00000010
 557 #define OFFLD_PARAMS_IMD        0x00000020
 558 #define OFFLD_PARAMS_DATA_SEQ_INORDER   0x00000040
 559 #define OFFLD_PARAMS_PDU_SEQ_INORDER    0x00000080
 560 #define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
 561
 562 /**
 563  * Pseudo amap definition in which each bit of the actual structure is defined
 564  * as a byte: used to calculate offset/shift/mask of each field
 565  */
 566 struct amap_beiscsi_offload_params {
 567         u8 max_burst_length[32];
 568         u8 max_send_data_segment_length[32];
 569         u8 first_burst_length[32];
 570         u8 erl[2];
 571         u8 dde[1];
 572         u8 hde[1];
 573         u8 ir2t[1];
 574         u8 imd[1];
 575         u8 data_seq_inorder[1];
 576         u8 pdu_seq_inorder[1];
 577         u8 max_r2t[16];
 578         u8 pad[8];
 579         u8 exp_statsn[32];
 580         u8 max_recv_data_segment_length[32];
 581 };
 582
 583 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
 584                 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
 585
 586 struct async_pdu_handle {
 587         struct list_head link;
 588         struct be_bus_address pa;
 589         void *pbuffer;
 590         unsigned int consumed;
 591         unsigned char index;
 592         unsigned char is_header;
 593         unsigned short cri;
 594         unsigned long buffer_len;
 595 };
 596
 597 struct hwi_async_entry {
 598         struct {
 599                 unsigned char hdr_received;
 600                 unsigned char hdr_len;
 601                 unsigned short bytes_received;
 602                 unsigned int bytes_needed;
 603                 struct list_head list;
 604         } wait_queue;
 605
 606         struct list_head header_busy_list;
 607         struct list_head data_busy_list;
 608 };
 609
 610 struct hwi_async_pdu_context {
 611         struct {
 612                 struct be_bus_address pa_base;
 613                 void *va_base;
 614                 void *ring_base;
 615                 struct async_pdu_handle *handle_base;
 616
 617                 unsigned int host_write_ptr;
 618                 unsigned int ep_read_ptr;
 619                 unsigned int writables;
 620
 621                 unsigned int free_entries;
 622                 unsigned int busy_entries;
 623
 624                 struct list_head free_list;
 625         } async_header;
 626
 627         struct {
 628                 struct be_bus_address pa_base;
 629                 void *va_base;
 630                 void *ring_base;
 631                 struct async_pdu_handle *handle_base;
 632
 633                 unsigned int host_write_ptr;
 634                 unsigned int ep_read_ptr;
 635                 unsigned int writables;
 636
 637                 unsigned int free_entries;
 638                 unsigned int busy_entries;
 639                 struct list_head free_list;
 640         } async_data;
 641
 642         unsigned int buffer_size;
 643         unsigned int num_entries;
 644 #define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
 645         unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
 646         /**
 647          * This is a varying size list! Do not add anything
 648          * after this entry!!
 649          */
 650         struct hwi_async_entry *async_entry;
 651 };
 652
 653 #define PDUCQE_CODE_MASK        0x0000003F
 654 #define PDUCQE_DPL_MASK         0xFFFF0000
 655 #define PDUCQE_INDEX_MASK       0x0000FFFF
 656
 657 struct i_t_dpdu_cqe {
 658         u32 dw[4];
 659 } __packed;
 660
 661 /**
 662  * Pseudo amap definition in which each bit of the actual structure is defined
 663  * as a byte: used to calculate offset/shift/mask of each field
 664  */
 665 struct amap_i_t_dpdu_cqe {
 666         u8 db_addr_hi[32];
 667         u8 db_addr_lo[32];
 668         u8 code[6];
 669         u8 cid[10];
 670         u8 dpl[16];
 671         u8 index[16];
 672         u8 num_cons[10];
 673         u8 rsvd0[4];
 674         u8 final;
 675         u8 valid;
 676 } __packed;
 677
 678 struct amap_i_t_dpdu_cqe_v2 {
 679         u8 db_addr_hi[32];  /* DWORD 0 */
 680         u8 db_addr_lo[32];  /* DWORD 1 */
 681         u8 code[6]; /* DWORD 2 */
 682         u8 num_cons; /* DWORD 2*/
 683         u8 rsvd0[8]; /* DWORD 2 */
 684         u8 dpl[17]; /* DWORD 2 */
 685         u8 index[16]; /* DWORD 3 */
 686         u8 cid[13]; /* DWORD 3 */
 687         u8 rsvd1; /* DWORD 3 */
 688         u8 final; /* DWORD 3 */
 689         u8 valid; /* DWORD 3 */
 690 } __packed;
 691
 692 #define CQE_VALID_MASK  0x80000000
 693 #define CQE_CODE_MASK   0x0000003F
 694 #define CQE_CID_MASK    0x0000FFC0
 695
 696 #define EQE_VALID_MASK          0x00000001
 697 #define EQE_MAJORCODE_MASK      0x0000000E
 698 #define EQE_RESID_MASK          0xFFFF0000
 699
 700 struct be_eq_entry {
 701         u32 dw[1];
 702 } __packed;
 703
 704 /**
 705  * Pseudo amap definition in which each bit of the actual structure is defined
 706  * as a byte: used to calculate offset/shift/mask of each field
 707  */
 708 struct amap_eq_entry {
 709         u8 valid;               /* DWORD 0 */
 710         u8 major_code[3];       /* DWORD 0 */
 711         u8 minor_code[12];      /* DWORD 0 */
 712         u8 resource_id[16];     /* DWORD 0 */
 713
 714 } __packed;
 715
 716 struct cq_db {
 717         u32 dw[1];
 718 } __packed;
 719
 720 /**
 721  * Pseudo amap definition in which each bit of the actual structure is defined
 722  * as a byte: used to calculate offset/shift/mask of each field
 723  */
 724 struct amap_cq_db {
 725         u8 qid[10];
 726         u8 event[1];
 727         u8 rsvd0[5];
 728         u8 num_popped[13];
 729         u8 rearm[1];
 730         u8 rsvd1[2];
 731 } __packed;
 732
 733 void beiscsi_process_eq(struct beiscsi_hba *phba);
 734
 735 struct iscsi_wrb {
 736         u32 dw[16];
 737 } __packed;
 738
 739 #define WRB_TYPE_MASK 0xF0000000
 740 #define SKH_WRB_TYPE_OFFSET 27
 741 #define BE_WRB_TYPE_OFFSET  28
 742
 743 #define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
 744                 (pwrb->dw[0] |= (wrb_type << type_offset))
 745
 746 /**
 747  * Pseudo amap definition in which each bit of the actual structure is defined
 748  * as a byte: used to calculate offset/shift/mask of each field
 749  */
 750 struct amap_iscsi_wrb {
 751         u8 lun[14];             /* DWORD 0 */
 752         u8 lt;                  /* DWORD 0 */
 753         u8 invld;               /* DWORD 0 */
 754         u8 wrb_idx[8];          /* DWORD 0 */
 755         u8 dsp;                 /* DWORD 0 */
 756         u8 dmsg;                /* DWORD 0 */
 757         u8 undr_run;            /* DWORD 0 */
 758         u8 over_run;            /* DWORD 0 */
 759         u8 type[4];             /* DWORD 0 */
 760         u8 ptr2nextwrb[8];      /* DWORD 1 */
 761         u8 r2t_exp_dtl[24];     /* DWORD 1 */
 762         u8 sgl_icd_idx[12];     /* DWORD 2 */
 763         u8 rsvd0[20];           /* DWORD 2 */
 764         u8 exp_data_sn[32];     /* DWORD 3 */
 765         u8 iscsi_bhs_addr_hi[32];       /* DWORD 4 */
 766         u8 iscsi_bhs_addr_lo[32];       /* DWORD 5 */
 767         u8 cmdsn_itt[32];       /* DWORD 6 */
 768         u8 dif_ref_tag[32];     /* DWORD 7 */
 769         u8 sge0_addr_hi[32];    /* DWORD 8 */
 770         u8 sge0_addr_lo[32];    /* DWORD 9  */
 771         u8 sge0_offset[22];     /* DWORD 10 */
 772         u8 pbs;                 /* DWORD 10 */
 773         u8 dif_mode[2];         /* DWORD 10 */
 774         u8 rsvd1[6];            /* DWORD 10 */
 775         u8 sge0_last;           /* DWORD 10 */
 776         u8 sge0_len[17];        /* DWORD 11 */
 777         u8 dif_meta_tag[14];    /* DWORD 11 */
 778         u8 sge0_in_ddr;         /* DWORD 11 */
 779         u8 sge1_addr_hi[32];    /* DWORD 12 */
 780         u8 sge1_addr_lo[32];    /* DWORD 13 */
 781         u8 sge1_r2t_offset[22]; /* DWORD 14 */
 782         u8 rsvd2[9];            /* DWORD 14 */
 783         u8 sge1_last;           /* DWORD 14 */
 784         u8 sge1_len[17];        /* DWORD 15 */
 785         u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
 786         u8 rsvd3[2];            /* DWORD 15 */
 787         u8 sge1_in_ddr;         /* DWORD 15 */
 788
 789 } __packed;
 790
 791 struct amap_iscsi_wrb_v2 {
 792         u8 r2t_exp_dtl[25]; /* DWORD 0 */
 793         u8 rsvd0[2];    /* DWORD 0*/
 794         u8 type[5];     /* DWORD 0 */
 795         u8 ptr2nextwrb[8];  /* DWORD 1 */
 796         u8 wrb_idx[8];      /* DWORD 1 */
 797         u8 lun[16];     /* DWORD 1 */
 798         u8 sgl_idx[16]; /* DWORD 2 */
 799         u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
 800         u8 exp_data_sn[32]; /* DWORD 3 */
 801         u8 iscsi_bhs_addr_hi[32];   /* DWORD 4 */
 802         u8 iscsi_bhs_addr_lo[32];   /* DWORD 5 */
 803         u8 cq_id[16];   /* DWORD 6 */
 804         u8 rsvd1[16];   /* DWORD 6 */
 805         u8 cmdsn_itt[32];   /* DWORD 7 */
 806         u8 sge0_addr_hi[32];    /* DWORD 8 */
 807         u8 sge0_addr_lo[32];    /* DWORD 9 */
 808         u8 sge0_offset[24]; /* DWORD 10 */
 809         u8 rsvd2[7];    /* DWORD 10 */
 810         u8 sge0_last;   /* DWORD 10 */
 811         u8 sge0_len[17];    /* DWORD 11 */
 812         u8 rsvd3[7];    /* DWORD 11 */
 813         u8 diff_enbl;   /* DWORD 11 */
 814         u8 u_run;       /* DWORD 11 */
 815         u8 o_run;       /* DWORD 11 */
 816         u8 invalid;     /* DWORD 11 */
 817         u8 dsp;         /* DWORD 11 */
 818         u8 dmsg;        /* DWORD 11 */
 819         u8 rsvd4;       /* DWORD 11 */
 820         u8 lt;          /* DWORD 11 */
 821         u8 sge1_addr_hi[32];    /* DWORD 12 */
 822         u8 sge1_addr_lo[32];    /* DWORD 13 */
 823         u8 sge1_r2t_offset[24]; /* DWORD 14 */
 824         u8 rsvd5[7];    /* DWORD 14 */
 825         u8 sge1_last;   /* DWORD 14 */
 826         u8 sge1_len[17];    /* DWORD 15 */
 827         u8 rsvd6[15];   /* DWORD 15 */
 828 } __packed;
 829
 830
 831 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
 832 void
 833 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
 834
 835 void beiscsi_process_all_cqs(struct work_struct *work);
 836 void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
 837                                      struct iscsi_task *task);
 838
 839 void hwi_ring_cq_db(struct beiscsi_hba *phba,
 840                      unsigned int id, unsigned int num_processed,
 841                      unsigned char rearm, unsigned char event);
 842 static inline bool beiscsi_error(struct beiscsi_hba *phba)
 843 {
 844         return phba->ue_detected || phba->fw_timeout;
 845 }
 846
 847 struct pdu_nop_out {
 848         u32 dw[12];
 849 };
 850
 851 /**
 852  * Pseudo amap definition in which each bit of the actual structure is defined
 853  * as a byte: used to calculate offset/shift/mask of each field
 854  */
 855 struct amap_pdu_nop_out {
 856         u8 opcode[6];           /* opcode 0x00 */
 857         u8 i_bit;               /* I Bit */
 858         u8 x_bit;               /* reserved; should be 0 */
 859         u8 fp_bit_filler1[7];
 860         u8 f_bit;               /* always 1 */
 861         u8 reserved1[16];
 862         u8 ahs_length[8];       /* no AHS */
 863         u8 data_len_hi[8];
 864         u8 data_len_lo[16];     /* DataSegmentLength */
 865         u8 lun[64];
 866         u8 itt[32];             /* initiator id for ping or 0xffffffff */
 867         u8 ttt[32];             /* target id for ping or 0xffffffff */
 868         u8 cmd_sn[32];
 869         u8 exp_stat_sn[32];
 870         u8 reserved5[128];
 871 };
 872
 873 #define PDUBASE_OPCODE_MASK     0x0000003F
 874 #define PDUBASE_DATALENHI_MASK  0x0000FF00
 875 #define PDUBASE_DATALENLO_MASK  0xFFFF0000
 876
 877 struct pdu_base {
 878         u32 dw[16];
 879 } __packed;
 880
 881 /**
 882  * Pseudo amap definition in which each bit of the actual structure is defined
 883  * as a byte: used to calculate offset/shift/mask of each field
 884  */
 885 struct amap_pdu_base {
 886         u8 opcode[6];
 887         u8 i_bit;               /* immediate bit */
 888         u8 x_bit;               /* reserved, always 0 */
 889         u8 reserved1[24];       /* opcode-specific fields */
 890         u8 ahs_length[8];       /* length units is 4 byte words */
 891         u8 data_len_hi[8];
 892         u8 data_len_lo[16];     /* DatasegmentLength */
 893         u8 lun[64];             /* lun or opcode-specific fields */
 894         u8 itt[32];             /* initiator task tag */
 895         u8 reserved4[224];
 896 };
 897
 898 struct iscsi_target_context_update_wrb {
 899         u32 dw[16];
 900 } __packed;
 901
 902 /**
 903  * Pseudo amap definition in which each bit of the actual structure is defined
 904  * as a byte: used to calculate offset/shift/mask of each field
 905  */
 906 #define BE_TGT_CTX_UPDT_CMD 0x07
 907 struct amap_iscsi_target_context_update_wrb {
 908         u8 lun[14];             /* DWORD 0 */
 909         u8 lt;                  /* DWORD 0 */
 910         u8 invld;               /* DWORD 0 */
 911         u8 wrb_idx[8];          /* DWORD 0 */
 912         u8 dsp;                 /* DWORD 0 */
 913         u8 dmsg;                /* DWORD 0 */
 914         u8 undr_run;            /* DWORD 0 */
 915         u8 over_run;            /* DWORD 0 */
 916         u8 type[4];             /* DWORD 0 */
 917         u8 ptr2nextwrb[8];      /* DWORD 1 */
 918         u8 max_burst_length[19];        /* DWORD 1 */
 919         u8 rsvd0[5];            /* DWORD 1 */
 920         u8 rsvd1[15];           /* DWORD 2 */
 921         u8 max_send_data_segment_length[17];    /* DWORD 2 */
 922         u8 first_burst_length[14];      /* DWORD 3 */
 923         u8 rsvd2[2];            /* DWORD 3 */
 924         u8 tx_wrbindex_drv_msg[8];      /* DWORD 3 */
 925         u8 rsvd3[5];            /* DWORD 3 */
 926         u8 session_state[3];    /* DWORD 3 */
 927         u8 rsvd4[16];           /* DWORD 4 */
 928         u8 tx_jumbo;            /* DWORD 4 */
 929         u8 hde;                 /* DWORD 4 */
 930         u8 dde;                 /* DWORD 4 */
 931         u8 erl[2];              /* DWORD 4 */
 932         u8 domain_id[5];                /* DWORD 4 */
 933         u8 mode;                /* DWORD 4 */
 934         u8 imd;                 /* DWORD 4 */
 935         u8 ir2t;                /* DWORD 4 */
 936         u8 notpredblq[2];       /* DWORD 4 */
 937         u8 compltonack;         /* DWORD 4 */
 938         u8 stat_sn[32];         /* DWORD 5 */
 939         u8 pad_buffer_addr_hi[32];      /* DWORD 6 */
 940         u8 pad_buffer_addr_lo[32];      /* DWORD 7 */
 941         u8 pad_addr_hi[32];     /* DWORD 8 */
 942         u8 pad_addr_lo[32];     /* DWORD 9 */
 943         u8 rsvd5[32];           /* DWORD 10 */
 944         u8 rsvd6[32];           /* DWORD 11 */
 945         u8 rsvd7[32];           /* DWORD 12 */
 946         u8 rsvd8[32];           /* DWORD 13 */
 947         u8 rsvd9[32];           /* DWORD 14 */
 948         u8 rsvd10[32];          /* DWORD 15 */
 949
 950 } __packed;
 951
 952 #define BEISCSI_MAX_RECV_DATASEG_LEN    (64 * 1024)
 953 #define BEISCSI_MAX_CXNS    1
 954 struct amap_iscsi_target_context_update_wrb_v2 {
 955         u8 max_burst_length[24];    /* DWORD 0 */
 956         u8 rsvd0[3];    /* DWORD 0 */
 957         u8 type[5];     /* DWORD 0 */
 958         u8 ptr2nextwrb[8];  /* DWORD 1 */
 959         u8 wrb_idx[8];      /* DWORD 1 */
 960         u8 rsvd1[16];       /* DWORD 1 */
 961         u8 max_send_data_segment_length[24];    /* DWORD 2 */
 962         u8 rsvd2[8];    /* DWORD 2 */
 963         u8 first_burst_length[24]; /* DWORD 3 */
 964         u8 rsvd3[8]; /* DOWRD 3 */
 965         u8 max_r2t[16]; /* DWORD 4 */
 966         u8 rsvd4;       /* DWORD 4 */
 967         u8 hde;         /* DWORD 4 */
 968         u8 dde;         /* DWORD 4 */
 969         u8 erl[2];      /* DWORD 4 */
 970         u8 rsvd5[6];    /* DWORD 4 */
 971         u8 imd;         /* DWORD 4 */
 972         u8 ir2t;        /* DWORD 4 */
 973         u8 rsvd6[3];    /* DWORD 4 */
 974         u8 stat_sn[32];     /* DWORD 5 */
 975         u8 rsvd7[32];   /* DWORD 6 */
 976         u8 rsvd8[32];   /* DWORD 7 */
 977         u8 max_recv_dataseg_len[24];    /* DWORD 8 */
 978         u8 rsvd9[8]; /* DWORD 8 */
 979         u8 rsvd10[32];   /* DWORD 9 */
 980         u8 rsvd11[32];   /* DWORD 10 */
 981         u8 max_cxns[16]; /* DWORD 11 */
 982         u8 rsvd12[11]; /* DWORD  11*/
 983         u8 invld; /* DWORD 11 */
 984         u8 rsvd13;/* DWORD 11*/
 985         u8 dmsg; /* DWORD 11 */
 986         u8 data_seq_inorder; /* DWORD 11 */
 987         u8 pdu_seq_inorder; /* DWORD 11 */
 988         u8 rsvd14[32]; /*DWORD 12 */
 989         u8 rsvd15[32]; /* DWORD 13 */
 990         u8 rsvd16[32]; /* DWORD 14 */
 991         u8 rsvd17[32]; /* DWORD 15 */
 992 } __packed;
 993
 994
 995 struct be_ring {
 996         u32 pages;              /* queue size in pages */
 997         u32 id;                 /* queue id assigned by beklib */
 998         u32 num;                /* number of elements in queue */
 999         u32 cidx;               /* consumer index */
1000         u32 pidx;               /* producer index -- not used by most rings */
1001         u32 item_size;          /* size in bytes of one object */
1002         u8 ulp_num;     /* ULP to which CID binded */
1003         u16 register_set;
1004         u16 doorbell_format;
1005         u32 doorbell_offset;
1006
1007         void *va;               /* The virtual address of the ring.  This
1008                                  * should be last to allow 32 & 64 bit debugger
1009                                  * extensions to work.
1010                                  */
1011 };
1012
1013 struct hwi_controller {
1014         struct list_head io_sgl_list;
1015         struct list_head eh_sgl_list;
1016         struct sgl_handle *psgl_handle_base;
1017         unsigned int wrb_mem_index;
1018
1019         struct hwi_wrb_context *wrb_context;
1020         struct mcc_wrb *pmcc_wrb_base;
1021         struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
1022         struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
1023         struct hwi_context_memory *phwi_ctxt;
1024 };
1025
1026 enum hwh_type_enum {
1027         HWH_TYPE_IO = 1,
1028         HWH_TYPE_LOGOUT = 2,
1029         HWH_TYPE_TMF = 3,
1030         HWH_TYPE_NOP = 4,
1031         HWH_TYPE_IO_RD = 5,
1032         HWH_TYPE_LOGIN = 11,
1033         HWH_TYPE_INVALID = 0xFFFFFFFF
1034 };
1035
1036 struct wrb_handle {
1037         enum hwh_type_enum type;
1038         unsigned short wrb_index;
1039         unsigned short nxt_wrb_index;
1040
1041         struct iscsi_task *pio_handle;
1042         struct iscsi_wrb *pwrb;
1043 };
1044
1045 struct hwi_context_memory {
1046         /* Adaptive interrupt coalescing (AIC) info */
1047         u16 min_eqd;            /* in usecs */
1048         u16 max_eqd;            /* in usecs */
1049         u16 cur_eqd;            /* in usecs */
1050         struct be_eq_obj be_eq[MAX_CPUS];
1051         struct be_queue_info be_cq[MAX_CPUS - 1];
1052
1053         struct be_queue_info *be_wrbq;
1054         struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
1055         struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
1056         struct hwi_async_pdu_context *pasync_ctx[BEISCSI_ULP_COUNT];
1057 };
1058
1059 /* Logging related definitions */
1060 #define BEISCSI_LOG_INIT        0x0001  /* Initialization events */
1061 #define BEISCSI_LOG_MBOX        0x0002  /* Mailbox Events */
1062 #define BEISCSI_LOG_MISC        0x0004  /* Miscllaneous Events */
1063 #define BEISCSI_LOG_EH          0x0008  /* Error Handler */
1064 #define BEISCSI_LOG_IO          0x0010  /* IO Code Path */
1065 #define BEISCSI_LOG_CONFIG      0x0020  /* CONFIG Code Path */
1066 #define BEISCSI_LOG_ISCSI       0x0040  /* SCSI/iSCSI Protocol related Logs */
1067
1068 #define beiscsi_log(phba, level, mask, fmt, arg...) \
1069 do { \
1070         uint32_t log_value = phba->attr_log_enable; \
1071                 if (((mask) & log_value) || (level[1] <= '3')) \
1072                         shost_printk(level, phba->shost, \
1073                                      fmt, __LINE__, ##arg); \
1074 } while (0)
1075
1076 #endif