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[PARPORT] SUNBPP: Fix OOPS when debugging is enabled.
[linux/fpc-iii.git] / sound / pci / hda / hda_intel.c
blob1672cace1ae7d55592a1088a97511efe9761d4c0
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
4 *
5 * Copyright(c) 2004 Intel Corporation. All rights reserved.
6 *
7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
8 * PeiSen Hou <pshou@realtek.com.tw>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program; if not, write to the Free Software Foundation, Inc., 59
22 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 *
24 * CONTACTS:
25 *
26 * Matt Jared matt.jared@intel.com
27 * Andy Kopp andy.kopp@intel.com
28 * Dan Kogan dan.d.kogan@intel.com
29 *
30 * CHANGES:
31 *
32 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
33 *
34 */
35
36 #include <sound/driver.h>
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include "hda_codec.h"
50
51
52 static int index = SNDRV_DEFAULT_IDX1;
53 static char *id = SNDRV_DEFAULT_STR1;
54 static char *model;
55 static int position_fix;
56 static int probe_mask = -1;
57 static int single_cmd;
58 static int enable_msi;
59
60 module_param(index, int, 0444);
61 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
62 module_param(id, charp, 0444);
63 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
64 module_param(model, charp, 0444);
65 MODULE_PARM_DESC(model, "Use the given board model.");
66 module_param(position_fix, int, 0444);
67 MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
68 module_param(probe_mask, int, 0444);
69 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
70 module_param(single_cmd, bool, 0444);
71 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs (for debugging only).");
72 module_param(enable_msi, int, 0);
73 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
74
75
76 /* just for backward compatibility */
77 static int enable;
78 module_param(enable, bool, 0444);
79
80 MODULE_LICENSE("GPL");
81 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
82 "{Intel, ICH6M},"
83 "{Intel, ICH7},"
84 "{Intel, ESB2},"
85 "{Intel, ICH8},"
86 "{Intel, ICH9},"
87 "{ATI, SB450},"
88 "{ATI, SB600},"
89 "{ATI, RS600},"
90 "{ATI, RS690},"
91 "{VIA, VT8251},"
92 "{VIA, VT8237A},"
93 "{SiS, SIS966},"
94 "{ULI, M5461}}");
95 MODULE_DESCRIPTION("Intel HDA driver");
96
97 #define SFX "hda-intel: "
98
99 /*
100 * registers
101 */
102 #define ICH6_REG_GCAP 0x00
103 #define ICH6_REG_VMIN 0x02
104 #define ICH6_REG_VMAJ 0x03
105 #define ICH6_REG_OUTPAY 0x04
106 #define ICH6_REG_INPAY 0x06
107 #define ICH6_REG_GCTL 0x08
108 #define ICH6_REG_WAKEEN 0x0c
109 #define ICH6_REG_STATESTS 0x0e
110 #define ICH6_REG_GSTS 0x10
111 #define ICH6_REG_INTCTL 0x20
112 #define ICH6_REG_INTSTS 0x24
113 #define ICH6_REG_WALCLK 0x30
114 #define ICH6_REG_SYNC 0x34
115 #define ICH6_REG_CORBLBASE 0x40
116 #define ICH6_REG_CORBUBASE 0x44
117 #define ICH6_REG_CORBWP 0x48
118 #define ICH6_REG_CORBRP 0x4A
119 #define ICH6_REG_CORBCTL 0x4c
120 #define ICH6_REG_CORBSTS 0x4d
121 #define ICH6_REG_CORBSIZE 0x4e
122
123 #define ICH6_REG_RIRBLBASE 0x50
124 #define ICH6_REG_RIRBUBASE 0x54
125 #define ICH6_REG_RIRBWP 0x58
126 #define ICH6_REG_RINTCNT 0x5a
127 #define ICH6_REG_RIRBCTL 0x5c
128 #define ICH6_REG_RIRBSTS 0x5d
129 #define ICH6_REG_RIRBSIZE 0x5e
130
131 #define ICH6_REG_IC 0x60
132 #define ICH6_REG_IR 0x64
133 #define ICH6_REG_IRS 0x68
134 #define ICH6_IRS_VALID (1<<1)
135 #define ICH6_IRS_BUSY (1<<0)
136
137 #define ICH6_REG_DPLBASE 0x70
138 #define ICH6_REG_DPUBASE 0x74
139 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
140
141 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
142 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
143
144 /* stream register offsets from stream base */
145 #define ICH6_REG_SD_CTL 0x00
146 #define ICH6_REG_SD_STS 0x03
147 #define ICH6_REG_SD_LPIB 0x04
148 #define ICH6_REG_SD_CBL 0x08
149 #define ICH6_REG_SD_LVI 0x0c
150 #define ICH6_REG_SD_FIFOW 0x0e
151 #define ICH6_REG_SD_FIFOSIZE 0x10
152 #define ICH6_REG_SD_FORMAT 0x12
153 #define ICH6_REG_SD_BDLPL 0x18
154 #define ICH6_REG_SD_BDLPU 0x1c
155
156 /* PCI space */
157 #define ICH6_PCIREG_TCSEL 0x44
158
159 /*
160 * other constants
161 */
162
163 /* max number of SDs */
164 /* ICH, ATI and VIA have 4 playback and 4 capture */
165 #define ICH6_CAPTURE_INDEX 0
166 #define ICH6_NUM_CAPTURE 4
167 #define ICH6_PLAYBACK_INDEX 4
168 #define ICH6_NUM_PLAYBACK 4
169
170 /* ULI has 6 playback and 5 capture */
171 #define ULI_CAPTURE_INDEX 0
172 #define ULI_NUM_CAPTURE 5
173 #define ULI_PLAYBACK_INDEX 5
174 #define ULI_NUM_PLAYBACK 6
175
176 /* ATI HDMI has 1 playback and 0 capture */
177 #define ATIHDMI_CAPTURE_INDEX 0
178 #define ATIHDMI_NUM_CAPTURE 0
179 #define ATIHDMI_PLAYBACK_INDEX 0
180 #define ATIHDMI_NUM_PLAYBACK 1
181
182 /* this number is statically defined for simplicity */
183 #define MAX_AZX_DEV 16
184
185 /* max number of fragments - we may use more if allocating more pages for BDL */
186 #define BDL_SIZE PAGE_ALIGN(8192)
187 #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
188 /* max buffer size - no h/w limit, you can increase as you like */
189 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
190 /* max number of PCM devics per card */
191 #define AZX_MAX_AUDIO_PCMS 6
192 #define AZX_MAX_MODEM_PCMS 2
193 #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
194
195 /* RIRB int mask: overrun[2], response[0] */
196 #define RIRB_INT_RESPONSE 0x01
197 #define RIRB_INT_OVERRUN 0x04
198 #define RIRB_INT_MASK 0x05
199
200 /* STATESTS int mask: SD2,SD1,SD0 */
201 #define STATESTS_INT_MASK 0x07
202
203 /* SD_CTL bits */
204 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
205 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
206 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
207 #define SD_CTL_STREAM_TAG_SHIFT 20
208
209 /* SD_CTL and SD_STS */
210 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
211 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
212 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
213 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
214
215 /* SD_STS */
216 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
217
218 /* INTCTL and INTSTS */
219 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
220 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
221 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
222
223 /* GCTL unsolicited response enable bit */
224 #define ICH6_GCTL_UREN (1<<8)
225
226 /* GCTL reset bit */
227 #define ICH6_GCTL_RESET (1<<0)
228
229 /* CORB/RIRB control, read/write pointer */
230 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
231 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
232 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
233 /* below are so far hardcoded - should read registers in future */
234 #define ICH6_MAX_CORB_ENTRIES 256
235 #define ICH6_MAX_RIRB_ENTRIES 256
236
237 /* position fix mode */
238 enum {
239 POS_FIX_AUTO,
240 POS_FIX_NONE,
241 POS_FIX_POSBUF,
242 POS_FIX_FIFO,
243 };
244
245 /* Defines for ATI HD Audio support in SB450 south bridge */
246 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
247 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
248
249 /* Defines for Nvidia HDA support */
250 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
251 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
252
253 /*
254 */
255
256 struct azx_dev {
257 u32 *bdl; /* virtual address of the BDL */
258 dma_addr_t bdl_addr; /* physical address of the BDL */
259 u32 *posbuf; /* position buffer pointer */
260
261 unsigned int bufsize; /* size of the play buffer in bytes */
262 unsigned int fragsize; /* size of each period in bytes */
263 unsigned int frags; /* number for period in the play buffer */
264 unsigned int fifo_size; /* FIFO size */
265
266 void __iomem *sd_addr; /* stream descriptor pointer */
267
268 u32 sd_int_sta_mask; /* stream int status mask */
269
270 /* pcm support */
271 struct snd_pcm_substream *substream; /* assigned substream, set in PCM open */
272 unsigned int format_val; /* format value to be set in the controller and the codec */
273 unsigned char stream_tag; /* assigned stream */
274 unsigned char index; /* stream index */
275 /* for sanity check of position buffer */
276 unsigned int period_intr;
277
278 unsigned int opened :1;
279 unsigned int running :1;
280 };
281
282 /* CORB/RIRB */
283 struct azx_rb {
284 u32 *buf; /* CORB/RIRB buffer
285 * Each CORB entry is 4byte, RIRB is 8byte
286 */
287 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
288 /* for RIRB */
289 unsigned short rp, wp; /* read/write pointers */
290 int cmds; /* number of pending requests */
291 u32 res; /* last read value */
292 };
293
294 struct azx {
295 struct snd_card *card;
296 struct pci_dev *pci;
297
298 /* chip type specific */
299 int driver_type;
300 int playback_streams;
301 int playback_index_offset;
302 int capture_streams;
303 int capture_index_offset;
304 int num_streams;
305
306 /* pci resources */
307 unsigned long addr;
308 void __iomem *remap_addr;
309 int irq;
310
311 /* locks */
312 spinlock_t reg_lock;
313 struct mutex open_mutex;
314
315 /* streams (x num_streams) */
316 struct azx_dev *azx_dev;
317
318 /* PCM */
319 unsigned int pcm_devs;
320 struct snd_pcm *pcm[AZX_MAX_PCMS];
321
322 /* HD codec */
323 unsigned short codec_mask;
324 struct hda_bus *bus;
325
326 /* CORB/RIRB */
327 struct azx_rb corb;
328 struct azx_rb rirb;
329
330 /* BDL, CORB/RIRB and position buffers */
331 struct snd_dma_buffer bdl;
332 struct snd_dma_buffer rb;
333 struct snd_dma_buffer posbuf;
334
335 /* flags */
336 int position_fix;
337 unsigned int initialized :1;
338 unsigned int single_cmd :1;
339 unsigned int polling_mode :1;
340 unsigned int msi :1;
341 };
342
343 /* driver types */
344 enum {
345 AZX_DRIVER_ICH,
346 AZX_DRIVER_ATI,
347 AZX_DRIVER_ATIHDMI,
348 AZX_DRIVER_VIA,
349 AZX_DRIVER_SIS,
350 AZX_DRIVER_ULI,
351 AZX_DRIVER_NVIDIA,
352 };
353
354 static char *driver_short_names[] __devinitdata = {
355 [AZX_DRIVER_ICH] = "HDA Intel",
356 [AZX_DRIVER_ATI] = "HDA ATI SB",
357 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
358 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
359 [AZX_DRIVER_SIS] = "HDA SIS966",
360 [AZX_DRIVER_ULI] = "HDA ULI M5461",
361 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
362 };
363
364 /*
365 * macros for easy use
366 */
367 #define azx_writel(chip,reg,value) \
368 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
369 #define azx_readl(chip,reg) \
370 readl((chip)->remap_addr + ICH6_REG_##reg)
371 #define azx_writew(chip,reg,value) \
372 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
373 #define azx_readw(chip,reg) \
374 readw((chip)->remap_addr + ICH6_REG_##reg)
375 #define azx_writeb(chip,reg,value) \
376 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
377 #define azx_readb(chip,reg) \
378 readb((chip)->remap_addr + ICH6_REG_##reg)
379
380 #define azx_sd_writel(dev,reg,value) \
381 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
382 #define azx_sd_readl(dev,reg) \
383 readl((dev)->sd_addr + ICH6_REG_##reg)
384 #define azx_sd_writew(dev,reg,value) \
385 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
386 #define azx_sd_readw(dev,reg) \
387 readw((dev)->sd_addr + ICH6_REG_##reg)
388 #define azx_sd_writeb(dev,reg,value) \
389 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
390 #define azx_sd_readb(dev,reg) \
391 readb((dev)->sd_addr + ICH6_REG_##reg)
392
393 /* for pcm support */
394 #define get_azx_dev(substream) (substream->runtime->private_data)
395
396 /* Get the upper 32bit of the given dma_addr_t
397 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
398 */
399 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
400
401 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
402
403 /*
404 * Interface for HD codec
405 */
406
407 /*
408 * CORB / RIRB interface
409 */
410 static int azx_alloc_cmd_io(struct azx *chip)
411 {
412 int err;
413
414 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
415 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
416 PAGE_SIZE, &chip->rb);
417 if (err < 0) {
418 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
419 return err;
420 }
421 return 0;
422 }
423
424 static void azx_init_cmd_io(struct azx *chip)
425 {
426 /* CORB set up */
427 chip->corb.addr = chip->rb.addr;
428 chip->corb.buf = (u32 *)chip->rb.area;
429 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
430 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
431
432 /* set the corb size to 256 entries (ULI requires explicitly) */
433 azx_writeb(chip, CORBSIZE, 0x02);
434 /* set the corb write pointer to 0 */
435 azx_writew(chip, CORBWP, 0);
436 /* reset the corb hw read pointer */
437 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
438 /* enable corb dma */
439 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
440
441 /* RIRB set up */
442 chip->rirb.addr = chip->rb.addr + 2048;
443 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
444 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
445 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
446
447 /* set the rirb size to 256 entries (ULI requires explicitly) */
448 azx_writeb(chip, RIRBSIZE, 0x02);
449 /* reset the rirb hw write pointer */
450 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
451 /* set N=1, get RIRB response interrupt for new entry */
452 azx_writew(chip, RINTCNT, 1);
453 /* enable rirb dma and response irq */
454 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
455 chip->rirb.rp = chip->rirb.cmds = 0;
456 }
457
458 static void azx_free_cmd_io(struct azx *chip)
459 {
460 /* disable ringbuffer DMAs */
461 azx_writeb(chip, RIRBCTL, 0);
462 azx_writeb(chip, CORBCTL, 0);
463 }
464
465 /* send a command */
466 static int azx_corb_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
467 unsigned int verb, unsigned int para)
468 {
469 struct azx *chip = codec->bus->private_data;
470 unsigned int wp;
471 u32 val;
472
473 val = (u32)(codec->addr & 0x0f) << 28;
474 val |= (u32)direct << 27;
475 val |= (u32)nid << 20;
476 val |= verb << 8;
477 val |= para;
478
479 /* add command to corb */
480 wp = azx_readb(chip, CORBWP);
481 wp++;
482 wp %= ICH6_MAX_CORB_ENTRIES;
483
484 spin_lock_irq(&chip->reg_lock);
485 chip->rirb.cmds++;
486 chip->corb.buf[wp] = cpu_to_le32(val);
487 azx_writel(chip, CORBWP, wp);
488 spin_unlock_irq(&chip->reg_lock);
489
490 return 0;
491 }
492
493 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
494
495 /* retrieve RIRB entry - called from interrupt handler */
496 static void azx_update_rirb(struct azx *chip)
497 {
498 unsigned int rp, wp;
499 u32 res, res_ex;
500
501 wp = azx_readb(chip, RIRBWP);
502 if (wp == chip->rirb.wp)
503 return;
504 chip->rirb.wp = wp;
505
506 while (chip->rirb.rp != wp) {
507 chip->rirb.rp++;
508 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
509
510 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
511 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
512 res = le32_to_cpu(chip->rirb.buf[rp]);
513 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
514 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
515 else if (chip->rirb.cmds) {
516 chip->rirb.cmds--;
517 chip->rirb.res = res;
518 }
519 }
520 }
521
522 /* receive a response */
523 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
524 {
525 struct azx *chip = codec->bus->private_data;
526 unsigned long timeout;
527
528 again:
529 timeout = jiffies + msecs_to_jiffies(1000);
530 do {
531 if (chip->polling_mode) {
532 spin_lock_irq(&chip->reg_lock);
533 azx_update_rirb(chip);
534 spin_unlock_irq(&chip->reg_lock);
535 }
536 if (! chip->rirb.cmds)
537 return chip->rirb.res; /* the last value */
538 schedule_timeout_interruptible(1);
539 } while (time_after_eq(timeout, jiffies));
540
541 if (chip->msi) {
542 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
543 "disabling MSI...\n");
544 free_irq(chip->irq, chip);
545 chip->irq = -1;
546 pci_disable_msi(chip->pci);
547 chip->msi = 0;
548 if (azx_acquire_irq(chip, 1) < 0)
549 return -1;
550 goto again;
551 }
552
553 if (!chip->polling_mode) {
554 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
555 "switching to polling mode...\n");
556 chip->polling_mode = 1;
557 goto again;
558 }
559
560 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
561 "switching to single_cmd mode...\n");
562 chip->rirb.rp = azx_readb(chip, RIRBWP);
563 chip->rirb.cmds = 0;
564 /* switch to single_cmd mode */
565 chip->single_cmd = 1;
566 azx_free_cmd_io(chip);
567 return -1;
568 }
569
570 /*
571 * Use the single immediate command instead of CORB/RIRB for simplicity
572 *
573 * Note: according to Intel, this is not preferred use. The command was
574 * intended for the BIOS only, and may get confused with unsolicited
575 * responses. So, we shouldn't use it for normal operation from the
576 * driver.
577 * I left the codes, however, for debugging/testing purposes.
578 */
579
580 /* send a command */
581 static int azx_single_send_cmd(struct hda_codec *codec, hda_nid_t nid,
582 int direct, unsigned int verb,
583 unsigned int para)
584 {
585 struct azx *chip = codec->bus->private_data;
586 u32 val;
587 int timeout = 50;
588
589 val = (u32)(codec->addr & 0x0f) << 28;
590 val |= (u32)direct << 27;
591 val |= (u32)nid << 20;
592 val |= verb << 8;
593 val |= para;
594
595 while (timeout--) {
596 /* check ICB busy bit */
597 if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) {
598 /* Clear IRV valid bit */
599 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID);
600 azx_writel(chip, IC, val);
601 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY);
602 return 0;
603 }
604 udelay(1);
605 }
606 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val);
607 return -EIO;
608 }
609
610 /* receive a response */
611 static unsigned int azx_single_get_response(struct hda_codec *codec)
612 {
613 struct azx *chip = codec->bus->private_data;
614 int timeout = 50;
615
616 while (timeout--) {
617 /* check IRV busy bit */
618 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
619 return azx_readl(chip, IR);
620 udelay(1);
621 }
622 snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS));
623 return (unsigned int)-1;
624 }
625
626 /*
627 * The below are the main callbacks from hda_codec.
628 *
629 * They are just the skeleton to call sub-callbacks according to the
630 * current setting of chip->single_cmd.
631 */
632
633 /* send a command */
634 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
635 int direct, unsigned int verb,
636 unsigned int para)
637 {
638 struct azx *chip = codec->bus->private_data;
639 if (chip->single_cmd)
640 return azx_single_send_cmd(codec, nid, direct, verb, para);
641 else
642 return azx_corb_send_cmd(codec, nid, direct, verb, para);
643 }
644
645 /* get a response */
646 static unsigned int azx_get_response(struct hda_codec *codec)
647 {
648 struct azx *chip = codec->bus->private_data;
649 if (chip->single_cmd)
650 return azx_single_get_response(codec);
651 else
652 return azx_rirb_get_response(codec);
653 }
654
655
656 /* reset codec link */
657 static int azx_reset(struct azx *chip)
658 {
659 int count;
660
661 /* reset controller */
662 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
663
664 count = 50;
665 while (azx_readb(chip, GCTL) && --count)
666 msleep(1);
667
668 /* delay for >= 100us for codec PLL to settle per spec
669 * Rev 0.9 section 5.5.1
670 */
671 msleep(1);
672
673 /* Bring controller out of reset */
674 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
675
676 count = 50;
677 while (!azx_readb(chip, GCTL) && --count)
678 msleep(1);
679
680 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
681 msleep(1);
682
683 /* check to see if controller is ready */
684 if (!azx_readb(chip, GCTL)) {
685 snd_printd("azx_reset: controller not ready!\n");
686 return -EBUSY;
687 }
688
689 /* Accept unsolicited responses */
690 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
691
692 /* detect codecs */
693 if (!chip->codec_mask) {
694 chip->codec_mask = azx_readw(chip, STATESTS);
695 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
696 }
697
698 return 0;
699 }
700
701
702 /*
703 * Lowlevel interface
704 */
705
706 /* enable interrupts */
707 static void azx_int_enable(struct azx *chip)
708 {
709 /* enable controller CIE and GIE */
710 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
711 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
712 }
713
714 /* disable interrupts */
715 static void azx_int_disable(struct azx *chip)
716 {
717 int i;
718
719 /* disable interrupts in stream descriptor */
720 for (i = 0; i < chip->num_streams; i++) {
721 struct azx_dev *azx_dev = &chip->azx_dev[i];
722 azx_sd_writeb(azx_dev, SD_CTL,
723 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
724 }
725
726 /* disable SIE for all streams */
727 azx_writeb(chip, INTCTL, 0);
728
729 /* disable controller CIE and GIE */
730 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
731 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
732 }
733
734 /* clear interrupts */
735 static void azx_int_clear(struct azx *chip)
736 {
737 int i;
738
739 /* clear stream status */
740 for (i = 0; i < chip->num_streams; i++) {
741 struct azx_dev *azx_dev = &chip->azx_dev[i];
742 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
743 }
744
745 /* clear STATESTS */
746 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
747
748 /* clear rirb status */
749 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
750
751 /* clear int status */
752 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
753 }
754
755 /* start a stream */
756 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
757 {
758 /* enable SIE */
759 azx_writeb(chip, INTCTL,
760 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
761 /* set DMA start and interrupt mask */
762 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
763 SD_CTL_DMA_START | SD_INT_MASK);
764 }
765
766 /* stop a stream */
767 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
768 {
769 /* stop DMA */
770 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
771 ~(SD_CTL_DMA_START | SD_INT_MASK));
772 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
773 /* disable SIE */
774 azx_writeb(chip, INTCTL,
775 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
776 }
777
778
779 /*
780 * initialize the chip
781 */
782 static void azx_init_chip(struct azx *chip)
783 {
784 unsigned char reg;
785
786 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
787 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
788 * Ensuring these bits are 0 clears playback static on some HD Audio codecs
789 */
790 pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &reg);
791 pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, reg & 0xf8);
792
793 /* reset controller */
794 azx_reset(chip);
795
796 /* initialize interrupts */
797 azx_int_clear(chip);
798 azx_int_enable(chip);
799
800 /* initialize the codec command I/O */
801 if (!chip->single_cmd)
802 azx_init_cmd_io(chip);
803
804 /* program the position buffer */
805 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
806 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
807
808 switch (chip->driver_type) {
809 case AZX_DRIVER_ATI:
810 /* For ATI SB450 azalia HD audio, we need to enable snoop */
811 pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
812 &reg);
813 pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
814 (reg & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP);
815 break;
816 case AZX_DRIVER_NVIDIA:
817 /* For NVIDIA HDA, enable snoop */
818 pci_read_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR, &reg);
819 pci_write_config_byte(chip->pci,NVIDIA_HDA_TRANSREG_ADDR,
820 (reg & 0xf0) | NVIDIA_HDA_ENABLE_COHBITS);
821 break;
822 }
823 }
824
825
826 /*
827 * interrupt handler
828 */
829 static irqreturn_t azx_interrupt(int irq, void *dev_id)
830 {
831 struct azx *chip = dev_id;
832 struct azx_dev *azx_dev;
833 u32 status;
834 int i;
835
836 spin_lock(&chip->reg_lock);
837
838 status = azx_readl(chip, INTSTS);
839 if (status == 0) {
840 spin_unlock(&chip->reg_lock);
841 return IRQ_NONE;
842 }
843
844 for (i = 0; i < chip->num_streams; i++) {
845 azx_dev = &chip->azx_dev[i];
846 if (status & azx_dev->sd_int_sta_mask) {
847 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
848 if (azx_dev->substream && azx_dev->running) {
849 azx_dev->period_intr++;
850 spin_unlock(&chip->reg_lock);
851 snd_pcm_period_elapsed(azx_dev->substream);
852 spin_lock(&chip->reg_lock);
853 }
854 }
855 }
856
857 /* clear rirb int */
858 status = azx_readb(chip, RIRBSTS);
859 if (status & RIRB_INT_MASK) {
860 if (! chip->single_cmd && (status & RIRB_INT_RESPONSE))
861 azx_update_rirb(chip);
862 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
863 }
864
865 #if 0
866 /* clear state status int */
867 if (azx_readb(chip, STATESTS) & 0x04)
868 azx_writeb(chip, STATESTS, 0x04);
869 #endif
870 spin_unlock(&chip->reg_lock);
871
872 return IRQ_HANDLED;
873 }
874
875
876 /*
877 * set up BDL entries
878 */
879 static void azx_setup_periods(struct azx_dev *azx_dev)
880 {
881 u32 *bdl = azx_dev->bdl;
882 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
883 int idx;
884
885 /* reset BDL address */
886 azx_sd_writel(azx_dev, SD_BDLPL, 0);
887 azx_sd_writel(azx_dev, SD_BDLPU, 0);
888
889 /* program the initial BDL entries */
890 for (idx = 0; idx < azx_dev->frags; idx++) {
891 unsigned int off = idx << 2; /* 4 dword step */
892 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
893 /* program the address field of the BDL entry */
894 bdl[off] = cpu_to_le32((u32)addr);
895 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
896
897 /* program the size field of the BDL entry */
898 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
899
900 /* program the IOC to enable interrupt when buffer completes */
901 bdl[off+3] = cpu_to_le32(0x01);
902 }
903 }
904
905 /*
906 * set up the SD for streaming
907 */
908 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
909 {
910 unsigned char val;
911 int timeout;
912
913 /* make sure the run bit is zero for SD */
914 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);
915 /* reset stream */
916 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);
917 udelay(3);
918 timeout = 300;
919 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
920 --timeout)
921 ;
922 val &= ~SD_CTL_STREAM_RESET;
923 azx_sd_writeb(azx_dev, SD_CTL, val);
924 udelay(3);
925
926 timeout = 300;
927 /* waiting for hardware to report that the stream is out of reset */
928 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
929 --timeout)
930 ;
931
932 /* program the stream_tag */
933 azx_sd_writel(azx_dev, SD_CTL,
934 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) |
935 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
936
937 /* program the length of samples in cyclic buffer */
938 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
939
940 /* program the stream format */
941 /* this value needs to be the same as the one programmed */
942 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
943
944 /* program the stream LVI (last valid index) of the BDL */
945 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
946
947 /* program the BDL address */
948 /* lower BDL address */
949 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
950 /* upper BDL address */
951 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
952
953 /* enable the position buffer */
954 if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
955 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
956
957 /* set the interrupt enable bits in the descriptor control register */
958 azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
959
960 return 0;
961 }
962
963
964 /*
965 * Codec initialization
966 */
967
968 static unsigned int azx_max_codecs[] __devinitdata = {
969 [AZX_DRIVER_ICH] = 3,
970 [AZX_DRIVER_ATI] = 4,
971 [AZX_DRIVER_ATIHDMI] = 4,
972 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
973 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
974 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
975 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
976 };
977
978 static int __devinit azx_codec_create(struct azx *chip, const char *model)
979 {
980 struct hda_bus_template bus_temp;
981 int c, codecs, err;
982
983 memset(&bus_temp, 0, sizeof(bus_temp));
984 bus_temp.private_data = chip;
985 bus_temp.modelname = model;
986 bus_temp.pci = chip->pci;
987 bus_temp.ops.command = azx_send_cmd;
988 bus_temp.ops.get_response = azx_get_response;
989
990 if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0)
991 return err;
992
993 codecs = 0;
994 for (c = 0; c < azx_max_codecs[chip->driver_type]; c++) {
995 if ((chip->codec_mask & (1 << c)) & probe_mask) {
996 err = snd_hda_codec_new(chip->bus, c, NULL);
997 if (err < 0)
998 continue;
999 codecs++;
1000 }
1001 }
1002 if (! codecs) {
1003 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1004 return -ENXIO;
1005 }
1006
1007 return 0;
1008 }
1009
1010
1011 /*
1012 * PCM support
1013 */
1014
1015 /* assign a stream for the PCM */
1016 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1017 {
1018 int dev, i, nums;
1019 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1020 dev = chip->playback_index_offset;
1021 nums = chip->playback_streams;
1022 } else {
1023 dev = chip->capture_index_offset;
1024 nums = chip->capture_streams;
1025 }
1026 for (i = 0; i < nums; i++, dev++)
1027 if (! chip->azx_dev[dev].opened) {
1028 chip->azx_dev[dev].opened = 1;
1029 return &chip->azx_dev[dev];
1030 }
1031 return NULL;
1032 }
1033
1034 /* release the assigned stream */
1035 static inline void azx_release_device(struct azx_dev *azx_dev)
1036 {
1037 azx_dev->opened = 0;
1038 }
1039
1040 static struct snd_pcm_hardware azx_pcm_hw = {
1041 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1042 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1043 SNDRV_PCM_INFO_MMAP_VALID |
1044 /* No full-resume yet implemented */
1045 /* SNDRV_PCM_INFO_RESUME |*/
1046 SNDRV_PCM_INFO_PAUSE),
1047 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1048 .rates = SNDRV_PCM_RATE_48000,
1049 .rate_min = 48000,
1050 .rate_max = 48000,
1051 .channels_min = 2,
1052 .channels_max = 2,
1053 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1054 .period_bytes_min = 128,
1055 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1056 .periods_min = 2,
1057 .periods_max = AZX_MAX_FRAG,
1058 .fifo_size = 0,
1059 };
1060
1061 struct azx_pcm {
1062 struct azx *chip;
1063 struct hda_codec *codec;
1064 struct hda_pcm_stream *hinfo[2];
1065 };
1066
1067 static int azx_pcm_open(struct snd_pcm_substream *substream)
1068 {
1069 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1070 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1071 struct azx *chip = apcm->chip;
1072 struct azx_dev *azx_dev;
1073 struct snd_pcm_runtime *runtime = substream->runtime;
1074 unsigned long flags;
1075 int err;
1076
1077 mutex_lock(&chip->open_mutex);
1078 azx_dev = azx_assign_device(chip, substream->stream);
1079 if (azx_dev == NULL) {
1080 mutex_unlock(&chip->open_mutex);
1081 return -EBUSY;
1082 }
1083 runtime->hw = azx_pcm_hw;
1084 runtime->hw.channels_min = hinfo->channels_min;
1085 runtime->hw.channels_max = hinfo->channels_max;
1086 runtime->hw.formats = hinfo->formats;
1087 runtime->hw.rates = hinfo->rates;
1088 snd_pcm_limit_hw_rates(runtime);
1089 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1090 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1091 128);
1092 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1093 128);
1094 if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
1095 azx_release_device(azx_dev);
1096 mutex_unlock(&chip->open_mutex);
1097 return err;
1098 }
1099 spin_lock_irqsave(&chip->reg_lock, flags);
1100 azx_dev->substream = substream;
1101 azx_dev->running = 0;
1102 spin_unlock_irqrestore(&chip->reg_lock, flags);
1103
1104 runtime->private_data = azx_dev;
1105 mutex_unlock(&chip->open_mutex);
1106 return 0;
1107 }
1108
1109 static int azx_pcm_close(struct snd_pcm_substream *substream)
1110 {
1111 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1112 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1113 struct azx *chip = apcm->chip;
1114 struct azx_dev *azx_dev = get_azx_dev(substream);
1115 unsigned long flags;
1116
1117 mutex_lock(&chip->open_mutex);
1118 spin_lock_irqsave(&chip->reg_lock, flags);
1119 azx_dev->substream = NULL;
1120 azx_dev->running = 0;
1121 spin_unlock_irqrestore(&chip->reg_lock, flags);
1122 azx_release_device(azx_dev);
1123 hinfo->ops.close(hinfo, apcm->codec, substream);
1124 mutex_unlock(&chip->open_mutex);
1125 return 0;
1126 }
1127
1128 static int azx_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params)
1129 {
1130 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
1131 }
1132
1133 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1134 {
1135 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1136 struct azx_dev *azx_dev = get_azx_dev(substream);
1137 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1138
1139 /* reset BDL address */
1140 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1141 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1142 azx_sd_writel(azx_dev, SD_CTL, 0);
1143
1144 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1145
1146 return snd_pcm_lib_free_pages(substream);
1147 }
1148
1149 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1150 {
1151 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1152 struct azx *chip = apcm->chip;
1153 struct azx_dev *azx_dev = get_azx_dev(substream);
1154 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1155 struct snd_pcm_runtime *runtime = substream->runtime;
1156
1157 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1158 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1159 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1160 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1161 runtime->channels,
1162 runtime->format,
1163 hinfo->maxbps);
1164 if (! azx_dev->format_val) {
1165 snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n",
1166 runtime->rate, runtime->channels, runtime->format);
1167 return -EINVAL;
1168 }
1169
1170 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
1171 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1172 azx_setup_periods(azx_dev);
1173 azx_setup_controller(chip, azx_dev);
1174 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1175 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1176 else
1177 azx_dev->fifo_size = 0;
1178
1179 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1180 azx_dev->format_val, substream);
1181 }
1182
1183 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1184 {
1185 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1186 struct azx_dev *azx_dev = get_azx_dev(substream);
1187 struct azx *chip = apcm->chip;
1188 int err = 0;
1189
1190 spin_lock(&chip->reg_lock);
1191 switch (cmd) {
1192 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1193 case SNDRV_PCM_TRIGGER_RESUME:
1194 case SNDRV_PCM_TRIGGER_START:
1195 azx_stream_start(chip, azx_dev);
1196 azx_dev->running = 1;
1197 break;
1198 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1199 case SNDRV_PCM_TRIGGER_SUSPEND:
1200 case SNDRV_PCM_TRIGGER_STOP:
1201 azx_stream_stop(chip, azx_dev);
1202 azx_dev->running = 0;
1203 break;
1204 default:
1205 err = -EINVAL;
1206 }
1207 spin_unlock(&chip->reg_lock);
1208 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1209 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1210 cmd == SNDRV_PCM_TRIGGER_STOP) {
1211 int timeout = 5000;
1212 while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout)
1213 ;
1214 }
1215 return err;
1216 }
1217
1218 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1219 {
1220 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1221 struct azx *chip = apcm->chip;
1222 struct azx_dev *azx_dev = get_azx_dev(substream);
1223 unsigned int pos;
1224
1225 if (chip->position_fix == POS_FIX_POSBUF ||
1226 chip->position_fix == POS_FIX_AUTO) {
1227 /* use the position buffer */
1228 pos = le32_to_cpu(*azx_dev->posbuf);
1229 if (chip->position_fix == POS_FIX_AUTO &&
1230 azx_dev->period_intr == 1 && ! pos) {
1231 printk(KERN_WARNING
1232 "hda-intel: Invalid position buffer, "
1233 "using LPIB read method instead.\n");
1234 chip->position_fix = POS_FIX_NONE;
1235 goto read_lpib;
1236 }
1237 } else {
1238 read_lpib:
1239 /* read LPIB */
1240 pos = azx_sd_readl(azx_dev, SD_LPIB);
1241 if (chip->position_fix == POS_FIX_FIFO)
1242 pos += azx_dev->fifo_size;
1243 }
1244 if (pos >= azx_dev->bufsize)
1245 pos = 0;
1246 return bytes_to_frames(substream->runtime, pos);
1247 }
1248
1249 static struct snd_pcm_ops azx_pcm_ops = {
1250 .open = azx_pcm_open,
1251 .close = azx_pcm_close,
1252 .ioctl = snd_pcm_lib_ioctl,
1253 .hw_params = azx_pcm_hw_params,
1254 .hw_free = azx_pcm_hw_free,
1255 .prepare = azx_pcm_prepare,
1256 .trigger = azx_pcm_trigger,
1257 .pointer = azx_pcm_pointer,
1258 };
1259
1260 static void azx_pcm_free(struct snd_pcm *pcm)
1261 {
1262 kfree(pcm->private_data);
1263 }
1264
1265 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1266 struct hda_pcm *cpcm, int pcm_dev)
1267 {
1268 int err;
1269 struct snd_pcm *pcm;
1270 struct azx_pcm *apcm;
1271
1272 /* if no substreams are defined for both playback and capture,
1273 * it's just a placeholder. ignore it.
1274 */
1275 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1276 return 0;
1277
1278 snd_assert(cpcm->name, return -EINVAL);
1279
1280 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1281 cpcm->stream[0].substreams, cpcm->stream[1].substreams,
1282 &pcm);
1283 if (err < 0)
1284 return err;
1285 strcpy(pcm->name, cpcm->name);
1286 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1287 if (apcm == NULL)
1288 return -ENOMEM;
1289 apcm->chip = chip;
1290 apcm->codec = codec;
1291 apcm->hinfo[0] = &cpcm->stream[0];
1292 apcm->hinfo[1] = &cpcm->stream[1];
1293 pcm->private_data = apcm;
1294 pcm->private_free = azx_pcm_free;
1295 if (cpcm->stream[0].substreams)
1296 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1297 if (cpcm->stream[1].substreams)
1298 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1299 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1300 snd_dma_pci_data(chip->pci),
1301 1024 * 64, 1024 * 1024);
1302 chip->pcm[pcm_dev] = pcm;
1303 if (chip->pcm_devs < pcm_dev + 1)
1304 chip->pcm_devs = pcm_dev + 1;
1305
1306 return 0;
1307 }
1308
1309 static int __devinit azx_pcm_create(struct azx *chip)
1310 {
1311 struct list_head *p;
1312 struct hda_codec *codec;
1313 int c, err;
1314 int pcm_dev;
1315
1316 if ((err = snd_hda_build_pcms(chip->bus)) < 0)
1317 return err;
1318
1319 /* create audio PCMs */
1320 pcm_dev = 0;
1321 list_for_each(p, &chip->bus->codec_list) {
1322 codec = list_entry(p, struct hda_codec, list);
1323 for (c = 0; c < codec->num_pcms; c++) {
1324 if (codec->pcm_info[c].is_modem)
1325 continue; /* create later */
1326 if (pcm_dev >= AZX_MAX_AUDIO_PCMS) {
1327 snd_printk(KERN_ERR SFX "Too many audio PCMs\n");
1328 return -EINVAL;
1329 }
1330 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1331 if (err < 0)
1332 return err;
1333 pcm_dev++;
1334 }
1335 }
1336
1337 /* create modem PCMs */
1338 pcm_dev = AZX_MAX_AUDIO_PCMS;
1339 list_for_each(p, &chip->bus->codec_list) {
1340 codec = list_entry(p, struct hda_codec, list);
1341 for (c = 0; c < codec->num_pcms; c++) {
1342 if (! codec->pcm_info[c].is_modem)
1343 continue; /* already created */
1344 if (pcm_dev >= AZX_MAX_PCMS) {
1345 snd_printk(KERN_ERR SFX "Too many modem PCMs\n");
1346 return -EINVAL;
1347 }
1348 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1349 if (err < 0)
1350 return err;
1351 chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM;
1352 pcm_dev++;
1353 }
1354 }
1355 return 0;
1356 }
1357
1358 /*
1359 * mixer creation - all stuff is implemented in hda module
1360 */
1361 static int __devinit azx_mixer_create(struct azx *chip)
1362 {
1363 return snd_hda_build_controls(chip->bus);
1364 }
1365
1366
1367 /*
1368 * initialize SD streams
1369 */
1370 static int __devinit azx_init_stream(struct azx *chip)
1371 {
1372 int i;
1373
1374 /* initialize each stream (aka device)
1375 * assign the starting bdl address to each stream (device) and initialize
1376 */
1377 for (i = 0; i < chip->num_streams; i++) {
1378 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1379 struct azx_dev *azx_dev = &chip->azx_dev[i];
1380 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1381 azx_dev->bdl_addr = chip->bdl.addr + off;
1382 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1383 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1384 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1385 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1386 azx_dev->sd_int_sta_mask = 1 << i;
1387 /* stream tag: must be non-zero and unique */
1388 azx_dev->index = i;
1389 azx_dev->stream_tag = i + 1;
1390 }
1391
1392 return 0;
1393 }
1394
1395 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1396 {
1397 if (request_irq(chip->pci->irq, azx_interrupt,
1398 chip->msi ? 0 : IRQF_SHARED,
1399 "HDA Intel", chip)) {
1400 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1401 "disabling device\n", chip->pci->irq);
1402 if (do_disconnect)
1403 snd_card_disconnect(chip->card);
1404 return -1;
1405 }
1406 chip->irq = chip->pci->irq;
1407 pci_intx(chip->pci, !chip->msi);
1408 return 0;
1409 }
1410
1411
1412 #ifdef CONFIG_PM
1413 /*
1414 * power management
1415 */
1416 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1417 {
1418 struct snd_card *card = pci_get_drvdata(pci);
1419 struct azx *chip = card->private_data;
1420 int i;
1421
1422 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1423 for (i = 0; i < chip->pcm_devs; i++)
1424 snd_pcm_suspend_all(chip->pcm[i]);
1425 snd_hda_suspend(chip->bus, state);
1426 azx_free_cmd_io(chip);
1427 if (chip->irq >= 0) {
1428 synchronize_irq(chip->irq);
1429 free_irq(chip->irq, chip);
1430 chip->irq = -1;
1431 }
1432 if (chip->msi)
1433 pci_disable_msi(chip->pci);
1434 pci_disable_device(pci);
1435 pci_save_state(pci);
1436 pci_set_power_state(pci, pci_choose_state(pci, state));
1437 return 0;
1438 }
1439
1440 static int azx_resume(struct pci_dev *pci)
1441 {
1442 struct snd_card *card = pci_get_drvdata(pci);
1443 struct azx *chip = card->private_data;
1444
1445 pci_set_power_state(pci, PCI_D0);
1446 pci_restore_state(pci);
1447 if (pci_enable_device(pci) < 0) {
1448 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1449 "disabling device\n");
1450 snd_card_disconnect(card);
1451 return -EIO;
1452 }
1453 pci_set_master(pci);
1454 if (chip->msi)
1455 if (pci_enable_msi(pci) < 0)
1456 chip->msi = 0;
1457 if (azx_acquire_irq(chip, 1) < 0)
1458 return -EIO;
1459 azx_init_chip(chip);
1460 snd_hda_resume(chip->bus);
1461 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1462 return 0;
1463 }
1464 #endif /* CONFIG_PM */
1465
1466
1467 /*
1468 * destructor
1469 */
1470 static int azx_free(struct azx *chip)
1471 {
1472 if (chip->initialized) {
1473 int i;
1474
1475 for (i = 0; i < chip->num_streams; i++)
1476 azx_stream_stop(chip, &chip->azx_dev[i]);
1477
1478 /* disable interrupts */
1479 azx_int_disable(chip);
1480 azx_int_clear(chip);
1481
1482 /* disable CORB/RIRB */
1483 azx_free_cmd_io(chip);
1484
1485 /* disable position buffer */
1486 azx_writel(chip, DPLBASE, 0);
1487 azx_writel(chip, DPUBASE, 0);
1488 }
1489
1490 if (chip->irq >= 0) {
1491 synchronize_irq(chip->irq);
1492 free_irq(chip->irq, (void*)chip);
1493 }
1494 if (chip->msi)
1495 pci_disable_msi(chip->pci);
1496 if (chip->remap_addr)
1497 iounmap(chip->remap_addr);
1498
1499 if (chip->bdl.area)
1500 snd_dma_free_pages(&chip->bdl);
1501 if (chip->rb.area)
1502 snd_dma_free_pages(&chip->rb);
1503 if (chip->posbuf.area)
1504 snd_dma_free_pages(&chip->posbuf);
1505 pci_release_regions(chip->pci);
1506 pci_disable_device(chip->pci);
1507 kfree(chip->azx_dev);
1508 kfree(chip);
1509
1510 return 0;
1511 }
1512
1513 static int azx_dev_free(struct snd_device *device)
1514 {
1515 return azx_free(device->device_data);
1516 }
1517
1518 /*
1519 * white/black-listing for position_fix
1520 */
1521 static const struct snd_pci_quirk position_fix_list[] __devinitdata = {
1522 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1523 {}
1524 };
1525
1526 static int __devinit check_position_fix(struct azx *chip, int fix)
1527 {
1528 const struct snd_pci_quirk *q;
1529
1530 if (fix == POS_FIX_AUTO) {
1531 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1532 if (q) {
1533 snd_printdd(KERN_INFO
1534 "hda_intel: position_fix set to %d "
1535 "for device %04x:%04x\n",
1536 q->value, q->subvendor, q->subdevice);
1537 return q->value;
1538 }
1539 }
1540 return fix;
1541 }
1542
1543 /*
1544 * constructor
1545 */
1546 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1547 int driver_type,
1548 struct azx **rchip)
1549 {
1550 struct azx *chip;
1551 int err;
1552 static struct snd_device_ops ops = {
1553 .dev_free = azx_dev_free,
1554 };
1555
1556 *rchip = NULL;
1557
1558 err = pci_enable_device(pci);
1559 if (err < 0)
1560 return err;
1561
1562 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1563 if (!chip) {
1564 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1565 pci_disable_device(pci);
1566 return -ENOMEM;
1567 }
1568
1569 spin_lock_init(&chip->reg_lock);
1570 mutex_init(&chip->open_mutex);
1571 chip->card = card;
1572 chip->pci = pci;
1573 chip->irq = -1;
1574 chip->driver_type = driver_type;
1575 chip->msi = enable_msi;
1576
1577 chip->position_fix = check_position_fix(chip, position_fix);
1578
1579 chip->single_cmd = single_cmd;
1580
1581 #if BITS_PER_LONG != 64
1582 /* Fix up base address on ULI M5461 */
1583 if (chip->driver_type == AZX_DRIVER_ULI) {
1584 u16 tmp3;
1585 pci_read_config_word(pci, 0x40, &tmp3);
1586 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1587 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1588 }
1589 #endif
1590
1591 err = pci_request_regions(pci, "ICH HD audio");
1592 if (err < 0) {
1593 kfree(chip);
1594 pci_disable_device(pci);
1595 return err;
1596 }
1597
1598 chip->addr = pci_resource_start(pci, 0);
1599 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1600 if (chip->remap_addr == NULL) {
1601 snd_printk(KERN_ERR SFX "ioremap error\n");
1602 err = -ENXIO;
1603 goto errout;
1604 }
1605
1606 if (chip->msi)
1607 if (pci_enable_msi(pci) < 0)
1608 chip->msi = 0;
1609
1610 if (azx_acquire_irq(chip, 0) < 0) {
1611 err = -EBUSY;
1612 goto errout;
1613 }
1614
1615 pci_set_master(pci);
1616 synchronize_irq(chip->irq);
1617
1618 switch (chip->driver_type) {
1619 case AZX_DRIVER_ULI:
1620 chip->playback_streams = ULI_NUM_PLAYBACK;
1621 chip->capture_streams = ULI_NUM_CAPTURE;
1622 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1623 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1624 break;
1625 case AZX_DRIVER_ATIHDMI:
1626 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1627 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1628 chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX;
1629 chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX;
1630 break;
1631 default:
1632 chip->playback_streams = ICH6_NUM_PLAYBACK;
1633 chip->capture_streams = ICH6_NUM_CAPTURE;
1634 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1635 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1636 break;
1637 }
1638 chip->num_streams = chip->playback_streams + chip->capture_streams;
1639 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), GFP_KERNEL);
1640 if (!chip->azx_dev) {
1641 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1642 goto errout;
1643 }
1644
1645 /* allocate memory for the BDL for each stream */
1646 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1647 BDL_SIZE, &chip->bdl)) < 0) {
1648 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1649 goto errout;
1650 }
1651 /* allocate memory for the position buffer */
1652 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1653 chip->num_streams * 8, &chip->posbuf)) < 0) {
1654 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1655 goto errout;
1656 }
1657 /* allocate CORB/RIRB */
1658 if (! chip->single_cmd)
1659 if ((err = azx_alloc_cmd_io(chip)) < 0)
1660 goto errout;
1661
1662 /* initialize streams */
1663 azx_init_stream(chip);
1664
1665 /* initialize chip */
1666 azx_init_chip(chip);
1667
1668 chip->initialized = 1;
1669
1670 /* codec detection */
1671 if (!chip->codec_mask) {
1672 snd_printk(KERN_ERR SFX "no codecs found!\n");
1673 err = -ENODEV;
1674 goto errout;
1675 }
1676
1677 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) {
1678 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1679 goto errout;
1680 }
1681
1682 strcpy(card->driver, "HDA-Intel");
1683 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1684 sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq);
1685
1686 *rchip = chip;
1687 return 0;
1688
1689 errout:
1690 azx_free(chip);
1691 return err;
1692 }
1693
1694 static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1695 {
1696 struct snd_card *card;
1697 struct azx *chip;
1698 int err;
1699
1700 card = snd_card_new(index, id, THIS_MODULE, 0);
1701 if (!card) {
1702 snd_printk(KERN_ERR SFX "Error creating card!\n");
1703 return -ENOMEM;
1704 }
1705
1706 err = azx_create(card, pci, pci_id->driver_data, &chip);
1707 if (err < 0) {
1708 snd_card_free(card);
1709 return err;
1710 }
1711 card->private_data = chip;
1712
1713 /* create codec instances */
1714 if ((err = azx_codec_create(chip, model)) < 0) {
1715 snd_card_free(card);
1716 return err;
1717 }
1718
1719 /* create PCM streams */
1720 if ((err = azx_pcm_create(chip)) < 0) {
1721 snd_card_free(card);
1722 return err;
1723 }
1724
1725 /* create mixer controls */
1726 if ((err = azx_mixer_create(chip)) < 0) {
1727 snd_card_free(card);
1728 return err;
1729 }
1730
1731 snd_card_set_dev(card, &pci->dev);
1732
1733 if ((err = snd_card_register(card)) < 0) {
1734 snd_card_free(card);
1735 return err;
1736 }
1737
1738 pci_set_drvdata(pci, card);
1739
1740 return err;
1741 }
1742
1743 static void __devexit azx_remove(struct pci_dev *pci)
1744 {
1745 snd_card_free(pci_get_drvdata(pci));
1746 pci_set_drvdata(pci, NULL);
1747 }
1748
1749 /* PCI IDs */
1750 static struct pci_device_id azx_ids[] = {
1751 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
1752 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
1753 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
1754 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
1755 { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1756 { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1757 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
1758 { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
1759 { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
1760 { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */
1761 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
1762 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
1763 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
1764 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */
1765 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */
1766 { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
1767 { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
1768 { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
1769 { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
1770 { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
1771 { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
1772 { 0, }
1773 };
1774 MODULE_DEVICE_TABLE(pci, azx_ids);
1775
1776 /* pci_driver definition */
1777 static struct pci_driver driver = {
1778 .name = "HDA Intel",
1779 .id_table = azx_ids,
1780 .probe = azx_probe,
1781 .remove = __devexit_p(azx_remove),
1782 #ifdef CONFIG_PM
1783 .suspend = azx_suspend,
1784 .resume = azx_resume,
1785 #endif
1786 };
1787
1788 static int __init alsa_card_azx_init(void)
1789 {
1790 return pci_register_driver(&driver);
1791 }
1792
1793 static void __exit alsa_card_azx_exit(void)
1794 {
1795 pci_unregister_driver(&driver);
1796 }
1797
1798 module_init(alsa_card_azx_init)
1799 module_exit(alsa_card_azx_exit)
Linux with added FPC-III support