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vfs: remove unused wrapper block_page_mkwrite()
[linux/fpc-iii.git] / arch / arm / common / edma.c
blob873dbfcc7dc9db9278e0727a20c30f53df4db1bf
1 /*
2 * EDMA3 support for DaVinci
3 *
4 * Copyright (C) 2006-2009 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20 #include <linux/err.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/io.h>
27 #include <linux/slab.h>
28 #include <linux/edma.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/of_address.h>
31 #include <linux/of_device.h>
32 #include <linux/of_dma.h>
33 #include <linux/of_irq.h>
34 #include <linux/pm_runtime.h>
35
36 #include <linux/platform_data/edma.h>
37
38 /* Offsets matching "struct edmacc_param" */
39 #define PARM_OPT 0x00
40 #define PARM_SRC 0x04
41 #define PARM_A_B_CNT 0x08
42 #define PARM_DST 0x0c
43 #define PARM_SRC_DST_BIDX 0x10
44 #define PARM_LINK_BCNTRLD 0x14
45 #define PARM_SRC_DST_CIDX 0x18
46 #define PARM_CCNT 0x1c
47
48 #define PARM_SIZE 0x20
49
50 /* Offsets for EDMA CC global channel registers and their shadows */
51 #define SH_ER 0x00 /* 64 bits */
52 #define SH_ECR 0x08 /* 64 bits */
53 #define SH_ESR 0x10 /* 64 bits */
54 #define SH_CER 0x18 /* 64 bits */
55 #define SH_EER 0x20 /* 64 bits */
56 #define SH_EECR 0x28 /* 64 bits */
57 #define SH_EESR 0x30 /* 64 bits */
58 #define SH_SER 0x38 /* 64 bits */
59 #define SH_SECR 0x40 /* 64 bits */
60 #define SH_IER 0x50 /* 64 bits */
61 #define SH_IECR 0x58 /* 64 bits */
62 #define SH_IESR 0x60 /* 64 bits */
63 #define SH_IPR 0x68 /* 64 bits */
64 #define SH_ICR 0x70 /* 64 bits */
65 #define SH_IEVAL 0x78
66 #define SH_QER 0x80
67 #define SH_QEER 0x84
68 #define SH_QEECR 0x88
69 #define SH_QEESR 0x8c
70 #define SH_QSER 0x90
71 #define SH_QSECR 0x94
72 #define SH_SIZE 0x200
73
74 /* Offsets for EDMA CC global registers */
75 #define EDMA_REV 0x0000
76 #define EDMA_CCCFG 0x0004
77 #define EDMA_QCHMAP 0x0200 /* 8 registers */
78 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
79 #define EDMA_QDMAQNUM 0x0260
80 #define EDMA_QUETCMAP 0x0280
81 #define EDMA_QUEPRI 0x0284
82 #define EDMA_EMR 0x0300 /* 64 bits */
83 #define EDMA_EMCR 0x0308 /* 64 bits */
84 #define EDMA_QEMR 0x0310
85 #define EDMA_QEMCR 0x0314
86 #define EDMA_CCERR 0x0318
87 #define EDMA_CCERRCLR 0x031c
88 #define EDMA_EEVAL 0x0320
89 #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
90 #define EDMA_QRAE 0x0380 /* 4 registers */
91 #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
92 #define EDMA_QSTAT 0x0600 /* 2 registers */
93 #define EDMA_QWMTHRA 0x0620
94 #define EDMA_QWMTHRB 0x0624
95 #define EDMA_CCSTAT 0x0640
96
97 #define EDMA_M 0x1000 /* global channel registers */
98 #define EDMA_ECR 0x1008
99 #define EDMA_ECRH 0x100C
100 #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
101 #define EDMA_PARM 0x4000 /* 128 param entries */
102
103 #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
104
105 #define EDMA_DCHMAP 0x0100 /* 64 registers */
106
107 /* CCCFG register */
108 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
109 #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
110 #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
111 #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
112 #define CHMAP_EXIST BIT(24)
113
114 #define EDMA_MAX_DMACH 64
115 #define EDMA_MAX_PARAMENTRY 512
116
117 /*****************************************************************************/
118
119 static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
120
121 static inline unsigned int edma_read(unsigned ctlr, int offset)
122 {
123 return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
124 }
125
126 static inline void edma_write(unsigned ctlr, int offset, int val)
127 {
128 __raw_writel(val, edmacc_regs_base[ctlr] + offset);
129 }
130 static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
131 unsigned or)
132 {
133 unsigned val = edma_read(ctlr, offset);
134 val &= and;
135 val |= or;
136 edma_write(ctlr, offset, val);
137 }
138 static inline void edma_and(unsigned ctlr, int offset, unsigned and)
139 {
140 unsigned val = edma_read(ctlr, offset);
141 val &= and;
142 edma_write(ctlr, offset, val);
143 }
144 static inline void edma_or(unsigned ctlr, int offset, unsigned or)
145 {
146 unsigned val = edma_read(ctlr, offset);
147 val |= or;
148 edma_write(ctlr, offset, val);
149 }
150 static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
151 {
152 return edma_read(ctlr, offset + (i << 2));
153 }
154 static inline void edma_write_array(unsigned ctlr, int offset, int i,
155 unsigned val)
156 {
157 edma_write(ctlr, offset + (i << 2), val);
158 }
159 static inline void edma_modify_array(unsigned ctlr, int offset, int i,
160 unsigned and, unsigned or)
161 {
162 edma_modify(ctlr, offset + (i << 2), and, or);
163 }
164 static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
165 {
166 edma_or(ctlr, offset + (i << 2), or);
167 }
168 static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
169 unsigned or)
170 {
171 edma_or(ctlr, offset + ((i*2 + j) << 2), or);
172 }
173 static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
174 unsigned val)
175 {
176 edma_write(ctlr, offset + ((i*2 + j) << 2), val);
177 }
178 static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
179 {
180 return edma_read(ctlr, EDMA_SHADOW0 + offset);
181 }
182 static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
183 int i)
184 {
185 return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
186 }
187 static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
188 {
189 edma_write(ctlr, EDMA_SHADOW0 + offset, val);
190 }
191 static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
192 unsigned val)
193 {
194 edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
195 }
196 static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
197 int param_no)
198 {
199 return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
200 }
201 static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
202 unsigned val)
203 {
204 edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
205 }
206 static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
207 unsigned and, unsigned or)
208 {
209 edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
210 }
211 static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
212 unsigned and)
213 {
214 edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
215 }
216 static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
217 unsigned or)
218 {
219 edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
220 }
221
222 static inline void set_bits(int offset, int len, unsigned long *p)
223 {
224 for (; len > 0; len--)
225 set_bit(offset + (len - 1), p);
226 }
227
228 static inline void clear_bits(int offset, int len, unsigned long *p)
229 {
230 for (; len > 0; len--)
231 clear_bit(offset + (len - 1), p);
232 }
233
234 /*****************************************************************************/
235
236 /* actual number of DMA channels and slots on this silicon */
237 struct edma {
238 /* how many dma resources of each type */
239 unsigned num_channels;
240 unsigned num_region;
241 unsigned num_slots;
242 unsigned num_tc;
243 enum dma_event_q default_queue;
244
245 /* list of channels with no even trigger; terminated by "-1" */
246 const s8 *noevent;
247
248 struct edma_soc_info *info;
249
250 /* The edma_inuse bit for each PaRAM slot is clear unless the
251 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
252 */
253 DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
254
255 /* The edma_unused bit for each channel is clear unless
256 * it is not being used on this platform. It uses a bit
257 * of SOC-specific initialization code.
258 */
259 DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
260
261 unsigned irq_res_start;
262 unsigned irq_res_end;
263
264 struct dma_interrupt_data {
265 void (*callback)(unsigned channel, unsigned short ch_status,
266 void *data);
267 void *data;
268 } intr_data[EDMA_MAX_DMACH];
269 };
270
271 static struct edma *edma_cc[EDMA_MAX_CC];
272 static int arch_num_cc;
273
274 /* dummy param set used to (re)initialize parameter RAM slots */
275 static const struct edmacc_param dummy_paramset = {
276 .link_bcntrld = 0xffff,
277 .ccnt = 1,
278 };
279
280 static const struct of_device_id edma_of_ids[] = {
281 { .compatible = "ti,edma3", },
282 {}
283 };
284
285 /*****************************************************************************/
286
287 static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
288 enum dma_event_q queue_no)
289 {
290 int bit = (ch_no & 0x7) * 4;
291
292 /* default to low priority queue */
293 if (queue_no == EVENTQ_DEFAULT)
294 queue_no = edma_cc[ctlr]->default_queue;
295
296 queue_no &= 7;
297 edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
298 ~(0x7 << bit), queue_no << bit);
299 }
300
301 static void assign_priority_to_queue(unsigned ctlr, int queue_no,
302 int priority)
303 {
304 int bit = queue_no * 4;
305 edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
306 ((priority & 0x7) << bit));
307 }
308
309 /**
310 * map_dmach_param - Maps channel number to param entry number
311 *
312 * This maps the dma channel number to param entry numberter. In
313 * other words using the DMA channel mapping registers a param entry
314 * can be mapped to any channel
315 *
316 * Callers are responsible for ensuring the channel mapping logic is
317 * included in that particular EDMA variant (Eg : dm646x)
318 *
319 */
320 static void map_dmach_param(unsigned ctlr)
321 {
322 int i;
323 for (i = 0; i < EDMA_MAX_DMACH; i++)
324 edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
325 }
326
327 static inline void
328 setup_dma_interrupt(unsigned lch,
329 void (*callback)(unsigned channel, u16 ch_status, void *data),
330 void *data)
331 {
332 unsigned ctlr;
333
334 ctlr = EDMA_CTLR(lch);
335 lch = EDMA_CHAN_SLOT(lch);
336
337 if (!callback)
338 edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
339 BIT(lch & 0x1f));
340
341 edma_cc[ctlr]->intr_data[lch].callback = callback;
342 edma_cc[ctlr]->intr_data[lch].data = data;
343
344 if (callback) {
345 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
346 BIT(lch & 0x1f));
347 edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
348 BIT(lch & 0x1f));
349 }
350 }
351
352 static int irq2ctlr(int irq)
353 {
354 if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
355 return 0;
356 else if (irq >= edma_cc[1]->irq_res_start &&
357 irq <= edma_cc[1]->irq_res_end)
358 return 1;
359
360 return -1;
361 }
362
363 /******************************************************************************
364 *
365 * DMA interrupt handler
366 *
367 *****************************************************************************/
368 static irqreturn_t dma_irq_handler(int irq, void *data)
369 {
370 int ctlr;
371 u32 sh_ier;
372 u32 sh_ipr;
373 u32 bank;
374
375 ctlr = irq2ctlr(irq);
376 if (ctlr < 0)
377 return IRQ_NONE;
378
379 dev_dbg(data, "dma_irq_handler\n");
380
381 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
382 if (!sh_ipr) {
383 sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
384 if (!sh_ipr)
385 return IRQ_NONE;
386 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
387 bank = 1;
388 } else {
389 sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
390 bank = 0;
391 }
392
393 do {
394 u32 slot;
395 u32 channel;
396
397 dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
398
399 slot = __ffs(sh_ipr);
400 sh_ipr &= ~(BIT(slot));
401
402 if (sh_ier & BIT(slot)) {
403 channel = (bank << 5) | slot;
404 /* Clear the corresponding IPR bits */
405 edma_shadow0_write_array(ctlr, SH_ICR, bank,
406 BIT(slot));
407 if (edma_cc[ctlr]->intr_data[channel].callback)
408 edma_cc[ctlr]->intr_data[channel].callback(
409 channel, EDMA_DMA_COMPLETE,
410 edma_cc[ctlr]->intr_data[channel].data);
411 }
412 } while (sh_ipr);
413
414 edma_shadow0_write(ctlr, SH_IEVAL, 1);
415 return IRQ_HANDLED;
416 }
417
418 /******************************************************************************
419 *
420 * DMA error interrupt handler
421 *
422 *****************************************************************************/
423 static irqreturn_t dma_ccerr_handler(int irq, void *data)
424 {
425 int i;
426 int ctlr;
427 unsigned int cnt = 0;
428
429 ctlr = irq2ctlr(irq);
430 if (ctlr < 0)
431 return IRQ_NONE;
432
433 dev_dbg(data, "dma_ccerr_handler\n");
434
435 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
436 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
437 (edma_read(ctlr, EDMA_QEMR) == 0) &&
438 (edma_read(ctlr, EDMA_CCERR) == 0))
439 return IRQ_NONE;
440
441 while (1) {
442 int j = -1;
443 if (edma_read_array(ctlr, EDMA_EMR, 0))
444 j = 0;
445 else if (edma_read_array(ctlr, EDMA_EMR, 1))
446 j = 1;
447 if (j >= 0) {
448 dev_dbg(data, "EMR%d %08x\n", j,
449 edma_read_array(ctlr, EDMA_EMR, j));
450 for (i = 0; i < 32; i++) {
451 int k = (j << 5) + i;
452 if (edma_read_array(ctlr, EDMA_EMR, j) &
453 BIT(i)) {
454 /* Clear the corresponding EMR bits */
455 edma_write_array(ctlr, EDMA_EMCR, j,
456 BIT(i));
457 /* Clear any SER */
458 edma_shadow0_write_array(ctlr, SH_SECR,
459 j, BIT(i));
460 if (edma_cc[ctlr]->intr_data[k].
461 callback) {
462 edma_cc[ctlr]->intr_data[k].
463 callback(k,
464 EDMA_DMA_CC_ERROR,
465 edma_cc[ctlr]->intr_data
466 [k].data);
467 }
468 }
469 }
470 } else if (edma_read(ctlr, EDMA_QEMR)) {
471 dev_dbg(data, "QEMR %02x\n",
472 edma_read(ctlr, EDMA_QEMR));
473 for (i = 0; i < 8; i++) {
474 if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
475 /* Clear the corresponding IPR bits */
476 edma_write(ctlr, EDMA_QEMCR, BIT(i));
477 edma_shadow0_write(ctlr, SH_QSECR,
478 BIT(i));
479
480 /* NOTE: not reported!! */
481 }
482 }
483 } else if (edma_read(ctlr, EDMA_CCERR)) {
484 dev_dbg(data, "CCERR %08x\n",
485 edma_read(ctlr, EDMA_CCERR));
486 /* FIXME: CCERR.BIT(16) ignored! much better
487 * to just write CCERRCLR with CCERR value...
488 */
489 for (i = 0; i < 8; i++) {
490 if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
491 /* Clear the corresponding IPR bits */
492 edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
493
494 /* NOTE: not reported!! */
495 }
496 }
497 }
498 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
499 (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
500 (edma_read(ctlr, EDMA_QEMR) == 0) &&
501 (edma_read(ctlr, EDMA_CCERR) == 0))
502 break;
503 cnt++;
504 if (cnt > 10)
505 break;
506 }
507 edma_write(ctlr, EDMA_EEVAL, 1);
508 return IRQ_HANDLED;
509 }
510
511 static int reserve_contiguous_slots(int ctlr, unsigned int id,
512 unsigned int num_slots,
513 unsigned int start_slot)
514 {
515 int i, j;
516 unsigned int count = num_slots;
517 int stop_slot = start_slot;
518 DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
519
520 for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
521 j = EDMA_CHAN_SLOT(i);
522 if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
523 /* Record our current beginning slot */
524 if (count == num_slots)
525 stop_slot = i;
526
527 count--;
528 set_bit(j, tmp_inuse);
529
530 if (count == 0)
531 break;
532 } else {
533 clear_bit(j, tmp_inuse);
534
535 if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
536 stop_slot = i;
537 break;
538 } else {
539 count = num_slots;
540 }
541 }
542 }
543
544 /*
545 * We have to clear any bits that we set
546 * if we run out parameter RAM slots, i.e we do find a set
547 * of contiguous parameter RAM slots but do not find the exact number
548 * requested as we may reach the total number of parameter RAM slots
549 */
550 if (i == edma_cc[ctlr]->num_slots)
551 stop_slot = i;
552
553 j = start_slot;
554 for_each_set_bit_from(j, tmp_inuse, stop_slot)
555 clear_bit(j, edma_cc[ctlr]->edma_inuse);
556
557 if (count)
558 return -EBUSY;
559
560 for (j = i - num_slots + 1; j <= i; ++j)
561 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
562 &dummy_paramset, PARM_SIZE);
563
564 return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
565 }
566
567 static int prepare_unused_channel_list(struct device *dev, void *data)
568 {
569 struct platform_device *pdev = to_platform_device(dev);
570 int i, count, ctlr;
571 struct of_phandle_args dma_spec;
572
573 if (dev->of_node) {
574 count = of_property_count_strings(dev->of_node, "dma-names");
575 if (count < 0)
576 return 0;
577 for (i = 0; i < count; i++) {
578 if (of_parse_phandle_with_args(dev->of_node, "dmas",
579 "#dma-cells", i,
580 &dma_spec))
581 continue;
582
583 if (!of_match_node(edma_of_ids, dma_spec.np)) {
584 of_node_put(dma_spec.np);
585 continue;
586 }
587
588 clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
589 edma_cc[0]->edma_unused);
590 of_node_put(dma_spec.np);
591 }
592 return 0;
593 }
594
595 /* For non-OF case */
596 for (i = 0; i < pdev->num_resources; i++) {
597 if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
598 (int)pdev->resource[i].start >= 0) {
599 ctlr = EDMA_CTLR(pdev->resource[i].start);
600 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
601 edma_cc[ctlr]->edma_unused);
602 }
603 }
604
605 return 0;
606 }
607
608 /*-----------------------------------------------------------------------*/
609
610 static bool unused_chan_list_done;
611
612 /* Resource alloc/free: dma channels, parameter RAM slots */
613
614 /**
615 * edma_alloc_channel - allocate DMA channel and paired parameter RAM
616 * @channel: specific channel to allocate; negative for "any unmapped channel"
617 * @callback: optional; to be issued on DMA completion or errors
618 * @data: passed to callback
619 * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
620 * Controller (TC) executes requests using this channel. Use
621 * EVENTQ_DEFAULT unless you really need a high priority queue.
622 *
623 * This allocates a DMA channel and its associated parameter RAM slot.
624 * The parameter RAM is initialized to hold a dummy transfer.
625 *
626 * Normal use is to pass a specific channel number as @channel, to make
627 * use of hardware events mapped to that channel. When the channel will
628 * be used only for software triggering or event chaining, channels not
629 * mapped to hardware events (or mapped to unused events) are preferable.
630 *
631 * DMA transfers start from a channel using edma_start(), or by
632 * chaining. When the transfer described in that channel's parameter RAM
633 * slot completes, that slot's data may be reloaded through a link.
634 *
635 * DMA errors are only reported to the @callback associated with the
636 * channel driving that transfer, but transfer completion callbacks can
637 * be sent to another channel under control of the TCC field in
638 * the option word of the transfer's parameter RAM set. Drivers must not
639 * use DMA transfer completion callbacks for channels they did not allocate.
640 * (The same applies to TCC codes used in transfer chaining.)
641 *
642 * Returns the number of the channel, else negative errno.
643 */
644 int edma_alloc_channel(int channel,
645 void (*callback)(unsigned channel, u16 ch_status, void *data),
646 void *data,
647 enum dma_event_q eventq_no)
648 {
649 unsigned i, done = 0, ctlr = 0;
650 int ret = 0;
651
652 if (!unused_chan_list_done) {
653 /*
654 * Scan all the platform devices to find out the EDMA channels
655 * used and clear them in the unused list, making the rest
656 * available for ARM usage.
657 */
658 ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
659 prepare_unused_channel_list);
660 if (ret < 0)
661 return ret;
662
663 unused_chan_list_done = true;
664 }
665
666 if (channel >= 0) {
667 ctlr = EDMA_CTLR(channel);
668 channel = EDMA_CHAN_SLOT(channel);
669 }
670
671 if (channel < 0) {
672 for (i = 0; i < arch_num_cc; i++) {
673 channel = 0;
674 for (;;) {
675 channel = find_next_bit(edma_cc[i]->edma_unused,
676 edma_cc[i]->num_channels,
677 channel);
678 if (channel == edma_cc[i]->num_channels)
679 break;
680 if (!test_and_set_bit(channel,
681 edma_cc[i]->edma_inuse)) {
682 done = 1;
683 ctlr = i;
684 break;
685 }
686 channel++;
687 }
688 if (done)
689 break;
690 }
691 if (!done)
692 return -ENOMEM;
693 } else if (channel >= edma_cc[ctlr]->num_channels) {
694 return -EINVAL;
695 } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
696 return -EBUSY;
697 }
698
699 /* ensure access through shadow region 0 */
700 edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
701
702 /* ensure no events are pending */
703 edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
704 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
705 &dummy_paramset, PARM_SIZE);
706
707 if (callback)
708 setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
709 callback, data);
710
711 map_dmach_queue(ctlr, channel, eventq_no);
712
713 return EDMA_CTLR_CHAN(ctlr, channel);
714 }
715 EXPORT_SYMBOL(edma_alloc_channel);
716
717
718 /**
719 * edma_free_channel - deallocate DMA channel
720 * @channel: dma channel returned from edma_alloc_channel()
721 *
722 * This deallocates the DMA channel and associated parameter RAM slot
723 * allocated by edma_alloc_channel().
724 *
725 * Callers are responsible for ensuring the channel is inactive, and
726 * will not be reactivated by linking, chaining, or software calls to
727 * edma_start().
728 */
729 void edma_free_channel(unsigned channel)
730 {
731 unsigned ctlr;
732
733 ctlr = EDMA_CTLR(channel);
734 channel = EDMA_CHAN_SLOT(channel);
735
736 if (channel >= edma_cc[ctlr]->num_channels)
737 return;
738
739 setup_dma_interrupt(channel, NULL, NULL);
740 /* REVISIT should probably take out of shadow region 0 */
741
742 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
743 &dummy_paramset, PARM_SIZE);
744 clear_bit(channel, edma_cc[ctlr]->edma_inuse);
745 }
746 EXPORT_SYMBOL(edma_free_channel);
747
748 /**
749 * edma_alloc_slot - allocate DMA parameter RAM
750 * @slot: specific slot to allocate; negative for "any unused slot"
751 *
752 * This allocates a parameter RAM slot, initializing it to hold a
753 * dummy transfer. Slots allocated using this routine have not been
754 * mapped to a hardware DMA channel, and will normally be used by
755 * linking to them from a slot associated with a DMA channel.
756 *
757 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
758 * slots may be allocated on behalf of DSP firmware.
759 *
760 * Returns the number of the slot, else negative errno.
761 */
762 int edma_alloc_slot(unsigned ctlr, int slot)
763 {
764 if (!edma_cc[ctlr])
765 return -EINVAL;
766
767 if (slot >= 0)
768 slot = EDMA_CHAN_SLOT(slot);
769
770 if (slot < 0) {
771 slot = edma_cc[ctlr]->num_channels;
772 for (;;) {
773 slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
774 edma_cc[ctlr]->num_slots, slot);
775 if (slot == edma_cc[ctlr]->num_slots)
776 return -ENOMEM;
777 if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
778 break;
779 }
780 } else if (slot < edma_cc[ctlr]->num_channels ||
781 slot >= edma_cc[ctlr]->num_slots) {
782 return -EINVAL;
783 } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
784 return -EBUSY;
785 }
786
787 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
788 &dummy_paramset, PARM_SIZE);
789
790 return EDMA_CTLR_CHAN(ctlr, slot);
791 }
792 EXPORT_SYMBOL(edma_alloc_slot);
793
794 /**
795 * edma_free_slot - deallocate DMA parameter RAM
796 * @slot: parameter RAM slot returned from edma_alloc_slot()
797 *
798 * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
799 * Callers are responsible for ensuring the slot is inactive, and will
800 * not be activated.
801 */
802 void edma_free_slot(unsigned slot)
803 {
804 unsigned ctlr;
805
806 ctlr = EDMA_CTLR(slot);
807 slot = EDMA_CHAN_SLOT(slot);
808
809 if (slot < edma_cc[ctlr]->num_channels ||
810 slot >= edma_cc[ctlr]->num_slots)
811 return;
812
813 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
814 &dummy_paramset, PARM_SIZE);
815 clear_bit(slot, edma_cc[ctlr]->edma_inuse);
816 }
817 EXPORT_SYMBOL(edma_free_slot);
818
819
820 /**
821 * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
822 * The API will return the starting point of a set of
823 * contiguous parameter RAM slots that have been requested
824 *
825 * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
826 * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
827 * @count: number of contiguous Paramter RAM slots
828 * @slot - the start value of Parameter RAM slot that should be passed if id
829 * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
830 *
831 * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
832 * contiguous Parameter RAM slots from parameter RAM 64 in the case of
833 * DaVinci SOCs and 32 in the case of DA8xx SOCs.
834 *
835 * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
836 * set of contiguous parameter RAM slots from the "slot" that is passed as an
837 * argument to the API.
838 *
839 * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
840 * starts looking for a set of contiguous parameter RAMs from the "slot"
841 * that is passed as an argument to the API. On failure the API will try to
842 * find a set of contiguous Parameter RAM slots from the remaining Parameter
843 * RAM slots
844 */
845 int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
846 {
847 /*
848 * The start slot requested should be greater than
849 * the number of channels and lesser than the total number
850 * of slots
851 */
852 if ((id != EDMA_CONT_PARAMS_ANY) &&
853 (slot < edma_cc[ctlr]->num_channels ||
854 slot >= edma_cc[ctlr]->num_slots))
855 return -EINVAL;
856
857 /*
858 * The number of parameter RAM slots requested cannot be less than 1
859 * and cannot be more than the number of slots minus the number of
860 * channels
861 */
862 if (count < 1 || count >
863 (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
864 return -EINVAL;
865
866 switch (id) {
867 case EDMA_CONT_PARAMS_ANY:
868 return reserve_contiguous_slots(ctlr, id, count,
869 edma_cc[ctlr]->num_channels);
870 case EDMA_CONT_PARAMS_FIXED_EXACT:
871 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
872 return reserve_contiguous_slots(ctlr, id, count, slot);
873 default:
874 return -EINVAL;
875 }
876
877 }
878 EXPORT_SYMBOL(edma_alloc_cont_slots);
879
880 /**
881 * edma_free_cont_slots - deallocate DMA parameter RAM slots
882 * @slot: first parameter RAM of a set of parameter RAM slots to be freed
883 * @count: the number of contiguous parameter RAM slots to be freed
884 *
885 * This deallocates the parameter RAM slots allocated by
886 * edma_alloc_cont_slots.
887 * Callers/applications need to keep track of sets of contiguous
888 * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
889 * API.
890 * Callers are responsible for ensuring the slots are inactive, and will
891 * not be activated.
892 */
893 int edma_free_cont_slots(unsigned slot, int count)
894 {
895 unsigned ctlr, slot_to_free;
896 int i;
897
898 ctlr = EDMA_CTLR(slot);
899 slot = EDMA_CHAN_SLOT(slot);
900
901 if (slot < edma_cc[ctlr]->num_channels ||
902 slot >= edma_cc[ctlr]->num_slots ||
903 count < 1)
904 return -EINVAL;
905
906 for (i = slot; i < slot + count; ++i) {
907 ctlr = EDMA_CTLR(i);
908 slot_to_free = EDMA_CHAN_SLOT(i);
909
910 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
911 &dummy_paramset, PARM_SIZE);
912 clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
913 }
914
915 return 0;
916 }
917 EXPORT_SYMBOL(edma_free_cont_slots);
918
919 /*-----------------------------------------------------------------------*/
920
921 /* Parameter RAM operations (i) -- read/write partial slots */
922
923 /**
924 * edma_set_src - set initial DMA source address in parameter RAM slot
925 * @slot: parameter RAM slot being configured
926 * @src_port: physical address of source (memory, controller FIFO, etc)
927 * @addressMode: INCR, except in very rare cases
928 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
929 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
930 *
931 * Note that the source address is modified during the DMA transfer
932 * according to edma_set_src_index().
933 */
934 void edma_set_src(unsigned slot, dma_addr_t src_port,
935 enum address_mode mode, enum fifo_width width)
936 {
937 unsigned ctlr;
938
939 ctlr = EDMA_CTLR(slot);
940 slot = EDMA_CHAN_SLOT(slot);
941
942 if (slot < edma_cc[ctlr]->num_slots) {
943 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
944
945 if (mode) {
946 /* set SAM and program FWID */
947 i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
948 } else {
949 /* clear SAM */
950 i &= ~SAM;
951 }
952 edma_parm_write(ctlr, PARM_OPT, slot, i);
953
954 /* set the source port address
955 in source register of param structure */
956 edma_parm_write(ctlr, PARM_SRC, slot, src_port);
957 }
958 }
959 EXPORT_SYMBOL(edma_set_src);
960
961 /**
962 * edma_set_dest - set initial DMA destination address in parameter RAM slot
963 * @slot: parameter RAM slot being configured
964 * @dest_port: physical address of destination (memory, controller FIFO, etc)
965 * @addressMode: INCR, except in very rare cases
966 * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
967 * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
968 *
969 * Note that the destination address is modified during the DMA transfer
970 * according to edma_set_dest_index().
971 */
972 void edma_set_dest(unsigned slot, dma_addr_t dest_port,
973 enum address_mode mode, enum fifo_width width)
974 {
975 unsigned ctlr;
976
977 ctlr = EDMA_CTLR(slot);
978 slot = EDMA_CHAN_SLOT(slot);
979
980 if (slot < edma_cc[ctlr]->num_slots) {
981 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
982
983 if (mode) {
984 /* set DAM and program FWID */
985 i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
986 } else {
987 /* clear DAM */
988 i &= ~DAM;
989 }
990 edma_parm_write(ctlr, PARM_OPT, slot, i);
991 /* set the destination port address
992 in dest register of param structure */
993 edma_parm_write(ctlr, PARM_DST, slot, dest_port);
994 }
995 }
996 EXPORT_SYMBOL(edma_set_dest);
997
998 /**
999 * edma_get_position - returns the current transfer point
1000 * @slot: parameter RAM slot being examined
1001 * @dst: true selects the dest position, false the source
1002 *
1003 * Returns the position of the current active slot
1004 */
1005 dma_addr_t edma_get_position(unsigned slot, bool dst)
1006 {
1007 u32 offs, ctlr = EDMA_CTLR(slot);
1008
1009 slot = EDMA_CHAN_SLOT(slot);
1010
1011 offs = PARM_OFFSET(slot);
1012 offs += dst ? PARM_DST : PARM_SRC;
1013
1014 return edma_read(ctlr, offs);
1015 }
1016
1017 /**
1018 * edma_set_src_index - configure DMA source address indexing
1019 * @slot: parameter RAM slot being configured
1020 * @src_bidx: byte offset between source arrays in a frame
1021 * @src_cidx: byte offset between source frames in a block
1022 *
1023 * Offsets are specified to support either contiguous or discontiguous
1024 * memory transfers, or repeated access to a hardware register, as needed.
1025 * When accessing hardware registers, both offsets are normally zero.
1026 */
1027 void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
1028 {
1029 unsigned ctlr;
1030
1031 ctlr = EDMA_CTLR(slot);
1032 slot = EDMA_CHAN_SLOT(slot);
1033
1034 if (slot < edma_cc[ctlr]->num_slots) {
1035 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1036 0xffff0000, src_bidx);
1037 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1038 0xffff0000, src_cidx);
1039 }
1040 }
1041 EXPORT_SYMBOL(edma_set_src_index);
1042
1043 /**
1044 * edma_set_dest_index - configure DMA destination address indexing
1045 * @slot: parameter RAM slot being configured
1046 * @dest_bidx: byte offset between destination arrays in a frame
1047 * @dest_cidx: byte offset between destination frames in a block
1048 *
1049 * Offsets are specified to support either contiguous or discontiguous
1050 * memory transfers, or repeated access to a hardware register, as needed.
1051 * When accessing hardware registers, both offsets are normally zero.
1052 */
1053 void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
1054 {
1055 unsigned ctlr;
1056
1057 ctlr = EDMA_CTLR(slot);
1058 slot = EDMA_CHAN_SLOT(slot);
1059
1060 if (slot < edma_cc[ctlr]->num_slots) {
1061 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1062 0x0000ffff, dest_bidx << 16);
1063 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
1064 0x0000ffff, dest_cidx << 16);
1065 }
1066 }
1067 EXPORT_SYMBOL(edma_set_dest_index);
1068
1069 /**
1070 * edma_set_transfer_params - configure DMA transfer parameters
1071 * @slot: parameter RAM slot being configured
1072 * @acnt: how many bytes per array (at least one)
1073 * @bcnt: how many arrays per frame (at least one)
1074 * @ccnt: how many frames per block (at least one)
1075 * @bcnt_rld: used only for A-Synchronized transfers; this specifies
1076 * the value to reload into bcnt when it decrements to zero
1077 * @sync_mode: ASYNC or ABSYNC
1078 *
1079 * See the EDMA3 documentation to understand how to configure and link
1080 * transfers using the fields in PaRAM slots. If you are not doing it
1081 * all at once with edma_write_slot(), you will use this routine
1082 * plus two calls each for source and destination, setting the initial
1083 * address and saying how to index that address.
1084 *
1085 * An example of an A-Synchronized transfer is a serial link using a
1086 * single word shift register. In that case, @acnt would be equal to
1087 * that word size; the serial controller issues a DMA synchronization
1088 * event to transfer each word, and memory access by the DMA transfer
1089 * controller will be word-at-a-time.
1090 *
1091 * An example of an AB-Synchronized transfer is a device using a FIFO.
1092 * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
1093 * The controller with the FIFO issues DMA synchronization events when
1094 * the FIFO threshold is reached, and the DMA transfer controller will
1095 * transfer one frame to (or from) the FIFO. It will probably use
1096 * efficient burst modes to access memory.
1097 */
1098 void edma_set_transfer_params(unsigned slot,
1099 u16 acnt, u16 bcnt, u16 ccnt,
1100 u16 bcnt_rld, enum sync_dimension sync_mode)
1101 {
1102 unsigned ctlr;
1103
1104 ctlr = EDMA_CTLR(slot);
1105 slot = EDMA_CHAN_SLOT(slot);
1106
1107 if (slot < edma_cc[ctlr]->num_slots) {
1108 edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
1109 0x0000ffff, bcnt_rld << 16);
1110 if (sync_mode == ASYNC)
1111 edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
1112 else
1113 edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
1114 /* Set the acount, bcount, ccount registers */
1115 edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
1116 edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
1117 }
1118 }
1119 EXPORT_SYMBOL(edma_set_transfer_params);
1120
1121 /**
1122 * edma_link - link one parameter RAM slot to another
1123 * @from: parameter RAM slot originating the link
1124 * @to: parameter RAM slot which is the link target
1125 *
1126 * The originating slot should not be part of any active DMA transfer.
1127 */
1128 void edma_link(unsigned from, unsigned to)
1129 {
1130 unsigned ctlr_from, ctlr_to;
1131
1132 ctlr_from = EDMA_CTLR(from);
1133 from = EDMA_CHAN_SLOT(from);
1134 ctlr_to = EDMA_CTLR(to);
1135 to = EDMA_CHAN_SLOT(to);
1136
1137 if (from >= edma_cc[ctlr_from]->num_slots)
1138 return;
1139 if (to >= edma_cc[ctlr_to]->num_slots)
1140 return;
1141 edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
1142 PARM_OFFSET(to));
1143 }
1144 EXPORT_SYMBOL(edma_link);
1145
1146 /**
1147 * edma_unlink - cut link from one parameter RAM slot
1148 * @from: parameter RAM slot originating the link
1149 *
1150 * The originating slot should not be part of any active DMA transfer.
1151 * Its link is set to 0xffff.
1152 */
1153 void edma_unlink(unsigned from)
1154 {
1155 unsigned ctlr;
1156
1157 ctlr = EDMA_CTLR(from);
1158 from = EDMA_CHAN_SLOT(from);
1159
1160 if (from >= edma_cc[ctlr]->num_slots)
1161 return;
1162 edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
1163 }
1164 EXPORT_SYMBOL(edma_unlink);
1165
1166 /*-----------------------------------------------------------------------*/
1167
1168 /* Parameter RAM operations (ii) -- read/write whole parameter sets */
1169
1170 /**
1171 * edma_write_slot - write parameter RAM data for slot
1172 * @slot: number of parameter RAM slot being modified
1173 * @param: data to be written into parameter RAM slot
1174 *
1175 * Use this to assign all parameters of a transfer at once. This
1176 * allows more efficient setup of transfers than issuing multiple
1177 * calls to set up those parameters in small pieces, and provides
1178 * complete control over all transfer options.
1179 */
1180 void edma_write_slot(unsigned slot, const struct edmacc_param *param)
1181 {
1182 unsigned ctlr;
1183
1184 ctlr = EDMA_CTLR(slot);
1185 slot = EDMA_CHAN_SLOT(slot);
1186
1187 if (slot >= edma_cc[ctlr]->num_slots)
1188 return;
1189 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
1190 PARM_SIZE);
1191 }
1192 EXPORT_SYMBOL(edma_write_slot);
1193
1194 /**
1195 * edma_read_slot - read parameter RAM data from slot
1196 * @slot: number of parameter RAM slot being copied
1197 * @param: where to store copy of parameter RAM data
1198 *
1199 * Use this to read data from a parameter RAM slot, perhaps to
1200 * save them as a template for later reuse.
1201 */
1202 void edma_read_slot(unsigned slot, struct edmacc_param *param)
1203 {
1204 unsigned ctlr;
1205
1206 ctlr = EDMA_CTLR(slot);
1207 slot = EDMA_CHAN_SLOT(slot);
1208
1209 if (slot >= edma_cc[ctlr]->num_slots)
1210 return;
1211 memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
1212 PARM_SIZE);
1213 }
1214 EXPORT_SYMBOL(edma_read_slot);
1215
1216 /*-----------------------------------------------------------------------*/
1217
1218 /* Various EDMA channel control operations */
1219
1220 /**
1221 * edma_pause - pause dma on a channel
1222 * @channel: on which edma_start() has been called
1223 *
1224 * This temporarily disables EDMA hardware events on the specified channel,
1225 * preventing them from triggering new transfers on its behalf
1226 */
1227 void edma_pause(unsigned channel)
1228 {
1229 unsigned ctlr;
1230
1231 ctlr = EDMA_CTLR(channel);
1232 channel = EDMA_CHAN_SLOT(channel);
1233
1234 if (channel < edma_cc[ctlr]->num_channels) {
1235 unsigned int mask = BIT(channel & 0x1f);
1236
1237 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
1238 }
1239 }
1240 EXPORT_SYMBOL(edma_pause);
1241
1242 /**
1243 * edma_resume - resumes dma on a paused channel
1244 * @channel: on which edma_pause() has been called
1245 *
1246 * This re-enables EDMA hardware events on the specified channel.
1247 */
1248 void edma_resume(unsigned channel)
1249 {
1250 unsigned ctlr;
1251
1252 ctlr = EDMA_CTLR(channel);
1253 channel = EDMA_CHAN_SLOT(channel);
1254
1255 if (channel < edma_cc[ctlr]->num_channels) {
1256 unsigned int mask = BIT(channel & 0x1f);
1257
1258 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
1259 }
1260 }
1261 EXPORT_SYMBOL(edma_resume);
1262
1263 int edma_trigger_channel(unsigned channel)
1264 {
1265 unsigned ctlr;
1266 unsigned int mask;
1267
1268 ctlr = EDMA_CTLR(channel);
1269 channel = EDMA_CHAN_SLOT(channel);
1270 mask = BIT(channel & 0x1f);
1271
1272 edma_shadow0_write_array(ctlr, SH_ESR, (channel >> 5), mask);
1273
1274 pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
1275 edma_shadow0_read_array(ctlr, SH_ESR, (channel >> 5)));
1276 return 0;
1277 }
1278 EXPORT_SYMBOL(edma_trigger_channel);
1279
1280 /**
1281 * edma_start - start dma on a channel
1282 * @channel: channel being activated
1283 *
1284 * Channels with event associations will be triggered by their hardware
1285 * events, and channels without such associations will be triggered by
1286 * software. (At this writing there is no interface for using software
1287 * triggers except with channels that don't support hardware triggers.)
1288 *
1289 * Returns zero on success, else negative errno.
1290 */
1291 int edma_start(unsigned channel)
1292 {
1293 unsigned ctlr;
1294
1295 ctlr = EDMA_CTLR(channel);
1296 channel = EDMA_CHAN_SLOT(channel);
1297
1298 if (channel < edma_cc[ctlr]->num_channels) {
1299 int j = channel >> 5;
1300 unsigned int mask = BIT(channel & 0x1f);
1301
1302 /* EDMA channels without event association */
1303 if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
1304 pr_debug("EDMA: ESR%d %08x\n", j,
1305 edma_shadow0_read_array(ctlr, SH_ESR, j));
1306 edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
1307 return 0;
1308 }
1309
1310 /* EDMA channel with event association */
1311 pr_debug("EDMA: ER%d %08x\n", j,
1312 edma_shadow0_read_array(ctlr, SH_ER, j));
1313 /* Clear any pending event or error */
1314 edma_write_array(ctlr, EDMA_ECR, j, mask);
1315 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1316 /* Clear any SER */
1317 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1318 edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
1319 pr_debug("EDMA: EER%d %08x\n", j,
1320 edma_shadow0_read_array(ctlr, SH_EER, j));
1321 return 0;
1322 }
1323
1324 return -EINVAL;
1325 }
1326 EXPORT_SYMBOL(edma_start);
1327
1328 /**
1329 * edma_stop - stops dma on the channel passed
1330 * @channel: channel being deactivated
1331 *
1332 * When @lch is a channel, any active transfer is paused and
1333 * all pending hardware events are cleared. The current transfer
1334 * may not be resumed, and the channel's Parameter RAM should be
1335 * reinitialized before being reused.
1336 */
1337 void edma_stop(unsigned channel)
1338 {
1339 unsigned ctlr;
1340
1341 ctlr = EDMA_CTLR(channel);
1342 channel = EDMA_CHAN_SLOT(channel);
1343
1344 if (channel < edma_cc[ctlr]->num_channels) {
1345 int j = channel >> 5;
1346 unsigned int mask = BIT(channel & 0x1f);
1347
1348 edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
1349 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1350 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1351 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1352
1353 /* clear possibly pending completion interrupt */
1354 edma_shadow0_write_array(ctlr, SH_ICR, j, mask);
1355
1356 pr_debug("EDMA: EER%d %08x\n", j,
1357 edma_shadow0_read_array(ctlr, SH_EER, j));
1358
1359 /* REVISIT: consider guarding against inappropriate event
1360 * chaining by overwriting with dummy_paramset.
1361 */
1362 }
1363 }
1364 EXPORT_SYMBOL(edma_stop);
1365
1366 /******************************************************************************
1367 *
1368 * It cleans ParamEntry qand bring back EDMA to initial state if media has
1369 * been removed before EDMA has finished.It is usedful for removable media.
1370 * Arguments:
1371 * ch_no - channel no
1372 *
1373 * Return: zero on success, or corresponding error no on failure
1374 *
1375 * FIXME this should not be needed ... edma_stop() should suffice.
1376 *
1377 *****************************************************************************/
1378
1379 void edma_clean_channel(unsigned channel)
1380 {
1381 unsigned ctlr;
1382
1383 ctlr = EDMA_CTLR(channel);
1384 channel = EDMA_CHAN_SLOT(channel);
1385
1386 if (channel < edma_cc[ctlr]->num_channels) {
1387 int j = (channel >> 5);
1388 unsigned int mask = BIT(channel & 0x1f);
1389
1390 pr_debug("EDMA: EMR%d %08x\n", j,
1391 edma_read_array(ctlr, EDMA_EMR, j));
1392 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1393 /* Clear the corresponding EMR bits */
1394 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1395 /* Clear any SER */
1396 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1397 edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
1398 }
1399 }
1400 EXPORT_SYMBOL(edma_clean_channel);
1401
1402 /*
1403 * edma_clear_event - clear an outstanding event on the DMA channel
1404 * Arguments:
1405 * channel - channel number
1406 */
1407 void edma_clear_event(unsigned channel)
1408 {
1409 unsigned ctlr;
1410
1411 ctlr = EDMA_CTLR(channel);
1412 channel = EDMA_CHAN_SLOT(channel);
1413
1414 if (channel >= edma_cc[ctlr]->num_channels)
1415 return;
1416 if (channel < 32)
1417 edma_write(ctlr, EDMA_ECR, BIT(channel));
1418 else
1419 edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
1420 }
1421 EXPORT_SYMBOL(edma_clear_event);
1422
1423 /*
1424 * edma_assign_channel_eventq - move given channel to desired eventq
1425 * Arguments:
1426 * channel - channel number
1427 * eventq_no - queue to move the channel
1428 *
1429 * Can be used to move a channel to a selected event queue.
1430 */
1431 void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no)
1432 {
1433 unsigned ctlr;
1434
1435 ctlr = EDMA_CTLR(channel);
1436 channel = EDMA_CHAN_SLOT(channel);
1437
1438 if (channel >= edma_cc[ctlr]->num_channels)
1439 return;
1440
1441 /* default to low priority queue */
1442 if (eventq_no == EVENTQ_DEFAULT)
1443 eventq_no = edma_cc[ctlr]->default_queue;
1444 if (eventq_no >= edma_cc[ctlr]->num_tc)
1445 return;
1446
1447 map_dmach_queue(ctlr, channel, eventq_no);
1448 }
1449 EXPORT_SYMBOL(edma_assign_channel_eventq);
1450
1451 static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1452 struct edma *edma_cc, int cc_id)
1453 {
1454 int i;
1455 u32 value, cccfg;
1456 s8 (*queue_priority_map)[2];
1457
1458 /* Decode the eDMA3 configuration from CCCFG register */
1459 cccfg = edma_read(cc_id, EDMA_CCCFG);
1460
1461 value = GET_NUM_REGN(cccfg);
1462 edma_cc->num_region = BIT(value);
1463
1464 value = GET_NUM_DMACH(cccfg);
1465 edma_cc->num_channels = BIT(value + 1);
1466
1467 value = GET_NUM_PAENTRY(cccfg);
1468 edma_cc->num_slots = BIT(value + 4);
1469
1470 value = GET_NUM_EVQUE(cccfg);
1471 edma_cc->num_tc = value + 1;
1472
1473 dev_dbg(dev, "eDMA3 CC%d HW configuration (cccfg: 0x%08x):\n", cc_id,
1474 cccfg);
1475 dev_dbg(dev, "num_region: %u\n", edma_cc->num_region);
1476 dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels);
1477 dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots);
1478 dev_dbg(dev, "num_tc: %u\n", edma_cc->num_tc);
1479
1480 /* Nothing need to be done if queue priority is provided */
1481 if (pdata->queue_priority_mapping)
1482 return 0;
1483
1484 /*
1485 * Configure TC/queue priority as follows:
1486 * Q0 - priority 0
1487 * Q1 - priority 1
1488 * Q2 - priority 2
1489 * ...
1490 * The meaning of priority numbers: 0 highest priority, 7 lowest
1491 * priority. So Q0 is the highest priority queue and the last queue has
1492 * the lowest priority.
1493 */
1494 queue_priority_map = devm_kzalloc(dev,
1495 (edma_cc->num_tc + 1) * sizeof(s8),
1496 GFP_KERNEL);
1497 if (!queue_priority_map)
1498 return -ENOMEM;
1499
1500 for (i = 0; i < edma_cc->num_tc; i++) {
1501 queue_priority_map[i][0] = i;
1502 queue_priority_map[i][1] = i;
1503 }
1504 queue_priority_map[i][0] = -1;
1505 queue_priority_map[i][1] = -1;
1506
1507 pdata->queue_priority_mapping = queue_priority_map;
1508 /* Default queue has the lowest priority */
1509 pdata->default_queue = i - 1;
1510
1511 return 0;
1512 }
1513
1514 #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
1515
1516 static int edma_xbar_event_map(struct device *dev, struct device_node *node,
1517 struct edma_soc_info *pdata, size_t sz)
1518 {
1519 const char pname[] = "ti,edma-xbar-event-map";
1520 struct resource res;
1521 void __iomem *xbar;
1522 s16 (*xbar_chans)[2];
1523 size_t nelm = sz / sizeof(s16);
1524 u32 shift, offset, mux;
1525 int ret, i;
1526
1527 xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL);
1528 if (!xbar_chans)
1529 return -ENOMEM;
1530
1531 ret = of_address_to_resource(node, 1, &res);
1532 if (ret)
1533 return -ENOMEM;
1534
1535 xbar = devm_ioremap(dev, res.start, resource_size(&res));
1536 if (!xbar)
1537 return -ENOMEM;
1538
1539 ret = of_property_read_u16_array(node, pname, (u16 *)xbar_chans, nelm);
1540 if (ret)
1541 return -EIO;
1542
1543 /* Invalidate last entry for the other user of this mess */
1544 nelm >>= 1;
1545 xbar_chans[nelm][0] = xbar_chans[nelm][1] = -1;
1546
1547 for (i = 0; i < nelm; i++) {
1548 shift = (xbar_chans[i][1] & 0x03) << 3;
1549 offset = xbar_chans[i][1] & 0xfffffffc;
1550 mux = readl(xbar + offset);
1551 mux &= ~(0xff << shift);
1552 mux |= xbar_chans[i][0] << shift;
1553 writel(mux, (xbar + offset));
1554 }
1555
1556 pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
1557 return 0;
1558 }
1559
1560 static int edma_of_parse_dt(struct device *dev,
1561 struct device_node *node,
1562 struct edma_soc_info *pdata)
1563 {
1564 int ret = 0;
1565 struct property *prop;
1566 size_t sz;
1567 struct edma_rsv_info *rsv_info;
1568
1569 rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
1570 if (!rsv_info)
1571 return -ENOMEM;
1572 pdata->rsv = rsv_info;
1573
1574 prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
1575 if (prop)
1576 ret = edma_xbar_event_map(dev, node, pdata, sz);
1577
1578 return ret;
1579 }
1580
1581 static struct of_dma_filter_info edma_filter_info = {
1582 .filter_fn = edma_filter_fn,
1583 };
1584
1585 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1586 struct device_node *node)
1587 {
1588 struct edma_soc_info *info;
1589 int ret;
1590
1591 info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
1592 if (!info)
1593 return ERR_PTR(-ENOMEM);
1594
1595 ret = edma_of_parse_dt(dev, node, info);
1596 if (ret)
1597 return ERR_PTR(ret);
1598
1599 dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
1600 dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap);
1601 of_dma_controller_register(dev->of_node, of_dma_simple_xlate,
1602 &edma_filter_info);
1603
1604 return info;
1605 }
1606 #else
1607 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1608 struct device_node *node)
1609 {
1610 return ERR_PTR(-ENOSYS);
1611 }
1612 #endif
1613
1614 static int edma_probe(struct platform_device *pdev)
1615 {
1616 struct edma_soc_info **info = pdev->dev.platform_data;
1617 struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL};
1618 s8 (*queue_priority_mapping)[2];
1619 int i, j, off, ln, found = 0;
1620 int status = -1;
1621 const s16 (*rsv_chans)[2];
1622 const s16 (*rsv_slots)[2];
1623 const s16 (*xbar_chans)[2];
1624 int irq[EDMA_MAX_CC] = {0, 0};
1625 int err_irq[EDMA_MAX_CC] = {0, 0};
1626 struct resource *r[EDMA_MAX_CC] = {NULL};
1627 struct resource res[EDMA_MAX_CC];
1628 char res_name[10];
1629 struct device_node *node = pdev->dev.of_node;
1630 struct device *dev = &pdev->dev;
1631 int ret;
1632 struct platform_device_info edma_dev_info = {
1633 .name = "edma-dma-engine",
1634 .dma_mask = DMA_BIT_MASK(32),
1635 .parent = &pdev->dev,
1636 };
1637
1638 if (node) {
1639 /* Check if this is a second instance registered */
1640 if (arch_num_cc) {
1641 dev_err(dev, "only one EDMA instance is supported via DT\n");
1642 return -ENODEV;
1643 }
1644
1645 ninfo[0] = edma_setup_info_from_dt(dev, node);
1646 if (IS_ERR(ninfo[0])) {
1647 dev_err(dev, "failed to get DT data\n");
1648 return PTR_ERR(ninfo[0]);
1649 }
1650
1651 info = ninfo;
1652 }
1653
1654 if (!info)
1655 return -ENODEV;
1656
1657 pm_runtime_enable(dev);
1658 ret = pm_runtime_get_sync(dev);
1659 if (ret < 0) {
1660 dev_err(dev, "pm_runtime_get_sync() failed\n");
1661 return ret;
1662 }
1663
1664 for (j = 0; j < EDMA_MAX_CC; j++) {
1665 if (!info[j]) {
1666 if (!found)
1667 return -ENODEV;
1668 break;
1669 }
1670 if (node) {
1671 ret = of_address_to_resource(node, j, &res[j]);
1672 if (!ret)
1673 r[j] = &res[j];
1674 } else {
1675 sprintf(res_name, "edma_cc%d", j);
1676 r[j] = platform_get_resource_byname(pdev,
1677 IORESOURCE_MEM,
1678 res_name);
1679 }
1680 if (!r[j]) {
1681 if (found)
1682 break;
1683 else
1684 return -ENODEV;
1685 } else {
1686 found = 1;
1687 }
1688
1689 edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]);
1690 if (IS_ERR(edmacc_regs_base[j]))
1691 return PTR_ERR(edmacc_regs_base[j]);
1692
1693 edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma),
1694 GFP_KERNEL);
1695 if (!edma_cc[j])
1696 return -ENOMEM;
1697
1698 /* Get eDMA3 configuration from IP */
1699 ret = edma_setup_from_hw(dev, info[j], edma_cc[j], j);
1700 if (ret)
1701 return ret;
1702
1703 edma_cc[j]->default_queue = info[j]->default_queue;
1704
1705 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
1706 edmacc_regs_base[j]);
1707
1708 for (i = 0; i < edma_cc[j]->num_slots; i++)
1709 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
1710 &dummy_paramset, PARM_SIZE);
1711
1712 /* Mark all channels as unused */
1713 memset(edma_cc[j]->edma_unused, 0xff,
1714 sizeof(edma_cc[j]->edma_unused));
1715
1716 if (info[j]->rsv) {
1717
1718 /* Clear the reserved channels in unused list */
1719 rsv_chans = info[j]->rsv->rsv_chans;
1720 if (rsv_chans) {
1721 for (i = 0; rsv_chans[i][0] != -1; i++) {
1722 off = rsv_chans[i][0];
1723 ln = rsv_chans[i][1];
1724 clear_bits(off, ln,
1725 edma_cc[j]->edma_unused);
1726 }
1727 }
1728
1729 /* Set the reserved slots in inuse list */
1730 rsv_slots = info[j]->rsv->rsv_slots;
1731 if (rsv_slots) {
1732 for (i = 0; rsv_slots[i][0] != -1; i++) {
1733 off = rsv_slots[i][0];
1734 ln = rsv_slots[i][1];
1735 set_bits(off, ln,
1736 edma_cc[j]->edma_inuse);
1737 }
1738 }
1739 }
1740
1741 /* Clear the xbar mapped channels in unused list */
1742 xbar_chans = info[j]->xbar_chans;
1743 if (xbar_chans) {
1744 for (i = 0; xbar_chans[i][1] != -1; i++) {
1745 off = xbar_chans[i][1];
1746 clear_bits(off, 1,
1747 edma_cc[j]->edma_unused);
1748 }
1749 }
1750
1751 if (node) {
1752 irq[j] = irq_of_parse_and_map(node, 0);
1753 err_irq[j] = irq_of_parse_and_map(node, 2);
1754 } else {
1755 char irq_name[10];
1756
1757 sprintf(irq_name, "edma%d", j);
1758 irq[j] = platform_get_irq_byname(pdev, irq_name);
1759
1760 sprintf(irq_name, "edma%d_err", j);
1761 err_irq[j] = platform_get_irq_byname(pdev, irq_name);
1762 }
1763 edma_cc[j]->irq_res_start = irq[j];
1764 edma_cc[j]->irq_res_end = err_irq[j];
1765
1766 status = devm_request_irq(dev, irq[j], dma_irq_handler, 0,
1767 "edma", dev);
1768 if (status < 0) {
1769 dev_dbg(&pdev->dev,
1770 "devm_request_irq %d failed --> %d\n",
1771 irq[j], status);
1772 return status;
1773 }
1774
1775 status = devm_request_irq(dev, err_irq[j], dma_ccerr_handler, 0,
1776 "edma_error", dev);
1777 if (status < 0) {
1778 dev_dbg(&pdev->dev,
1779 "devm_request_irq %d failed --> %d\n",
1780 err_irq[j], status);
1781 return status;
1782 }
1783
1784 for (i = 0; i < edma_cc[j]->num_channels; i++)
1785 map_dmach_queue(j, i, info[j]->default_queue);
1786
1787 queue_priority_mapping = info[j]->queue_priority_mapping;
1788
1789 /* Event queue priority mapping */
1790 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
1791 assign_priority_to_queue(j,
1792 queue_priority_mapping[i][0],
1793 queue_priority_mapping[i][1]);
1794
1795 /* Map the channel to param entry if channel mapping logic
1796 * exist
1797 */
1798 if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
1799 map_dmach_param(j);
1800
1801 for (i = 0; i < edma_cc[j]->num_region; i++) {
1802 edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
1803 edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
1804 edma_write_array(j, EDMA_QRAE, i, 0x0);
1805 }
1806 edma_cc[j]->info = info[j];
1807 arch_num_cc++;
1808
1809 edma_dev_info.id = j;
1810 platform_device_register_full(&edma_dev_info);
1811 }
1812
1813 return 0;
1814 }
1815
1816 #ifdef CONFIG_PM_SLEEP
1817 static int edma_pm_resume(struct device *dev)
1818 {
1819 int i, j;
1820
1821 for (j = 0; j < arch_num_cc; j++) {
1822 struct edma *cc = edma_cc[j];
1823
1824 s8 (*queue_priority_mapping)[2];
1825
1826 queue_priority_mapping = cc->info->queue_priority_mapping;
1827
1828 /* Event queue priority mapping */
1829 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
1830 assign_priority_to_queue(j,
1831 queue_priority_mapping[i][0],
1832 queue_priority_mapping[i][1]);
1833
1834 /*
1835 * Map the channel to param entry if channel mapping logic
1836 * exist
1837 */
1838 if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
1839 map_dmach_param(j);
1840
1841 for (i = 0; i < cc->num_channels; i++) {
1842 if (test_bit(i, cc->edma_inuse)) {
1843 /* ensure access through shadow region 0 */
1844 edma_or_array2(j, EDMA_DRAE, 0, i >> 5,
1845 BIT(i & 0x1f));
1846
1847 setup_dma_interrupt(i,
1848 cc->intr_data[i].callback,
1849 cc->intr_data[i].data);
1850 }
1851 }
1852 }
1853
1854 return 0;
1855 }
1856 #endif
1857
1858 static const struct dev_pm_ops edma_pm_ops = {
1859 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, edma_pm_resume)
1860 };
1861
1862 static struct platform_driver edma_driver = {
1863 .driver = {
1864 .name = "edma",
1865 .pm = &edma_pm_ops,
1866 .of_match_table = edma_of_ids,
1867 },
1868 .probe = edma_probe,
1869 };
1870
1871 static int __init edma_init(void)
1872 {
1873 return platform_driver_probe(&edma_driver, edma_probe);
1874 }
1875 arch_initcall(edma_init);
1876
Linux with added FPC-III support