arch/arm/mach-ks8695/time.c

   1 /*
   2  * arch/arm/mach-ks8695/time.c
   3  *
   4  * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
   5  * Copyright (C) 2006 Simtec Electronics
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/io.h>
  28 #include <linux/clockchips.h>
  29
  30 #include <asm/mach/time.h>
  31 #include <asm/system_misc.h>
  32
  33 #include <mach/regs-irq.h>
  34
  35 #include "generic.h"
  36
  37 #define KS8695_TMR_OFFSET       (0xF0000 + 0xE400)
  38 #define KS8695_TMR_VA           (KS8695_IO_VA + KS8695_TMR_OFFSET)
  39 #define KS8695_TMR_PA           (KS8695_IO_PA + KS8695_TMR_OFFSET)
  40
  41 /*
  42  * Timer registers
  43  */
  44 #define KS8695_TMCON            (0x00)          /* Timer Control Register */
  45 #define KS8695_T1TC             (0x04)          /* Timer 1 Timeout Count Register */
  46 #define KS8695_T0TC             (0x08)          /* Timer 0 Timeout Count Register */
  47 #define KS8695_T1PD             (0x0C)          /* Timer 1 Pulse Count Register */
  48 #define KS8695_T0PD             (0x10)          /* Timer 0 Pulse Count Register */
  49
  50 /* Timer Control Register */
  51 #define TMCON_T1EN              (1 << 1)        /* Timer 1 Enable */
  52 #define TMCON_T0EN              (1 << 0)        /* Timer 0 Enable */
  53
  54 /* Timer0 Timeout Counter Register */
  55 #define T0TC_WATCHDOG           (0xff)          /* Enable watchdog mode */
  56
  57 static int ks8695_set_periodic(struct clock_event_device *evt)
  58 {
  59         u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ);
  60         u32 half = DIV_ROUND_CLOSEST(rate, 2);
  61         u32 tmcon;
  62
  63         /* Disable timer 1 */
  64         tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
  65         tmcon &= ~TMCON_T1EN;
  66         writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
  67
  68         /* Both registers need to count down */
  69         writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
  70         writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
  71
  72         /* Re-enable timer1 */
  73         tmcon |= TMCON_T1EN;
  74         writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
  75         return 0;
  76 }
  77
  78 static int ks8695_set_next_event(unsigned long cycles,
  79                                  struct clock_event_device *evt)
  80
  81 {
  82         u32 half = DIV_ROUND_CLOSEST(cycles, 2);
  83         u32 tmcon;
  84
  85         /* Disable timer 1 */
  86         tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
  87         tmcon &= ~TMCON_T1EN;
  88         writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
  89
  90         /* Both registers need to count down */
  91         writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
  92         writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
  93
  94         /* Re-enable timer1 */
  95         tmcon |= TMCON_T1EN;
  96         writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
  97
  98         return 0;
  99 }
 100
 101 static struct clock_event_device clockevent_ks8695 = {
 102         .name                   = "ks8695_t1tc",
 103         /* Reasonably fast and accurate clock event */
 104         .rating                 = 300,
 105         .features               = CLOCK_EVT_FEAT_ONESHOT |
 106                                   CLOCK_EVT_FEAT_PERIODIC,
 107         .set_next_event         = ks8695_set_next_event,
 108         .set_state_periodic     = ks8695_set_periodic,
 109 };
 110
 111 /*
 112  * IRQ handler for the timer.
 113  */
 114 static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id)
 115 {
 116         struct clock_event_device *evt = &clockevent_ks8695;
 117
 118         evt->event_handler(evt);
 119         return IRQ_HANDLED;
 120 }
 121
 122 static struct irqaction ks8695_timer_irq = {
 123         .name           = "ks8695_tick",
 124         .flags          = IRQF_TIMER,
 125         .handler        = ks8695_timer_interrupt,
 126 };
 127
 128 static void ks8695_timer_setup(void)
 129 {
 130         unsigned long tmcon;
 131
 132         /* Disable timer 0 and 1 */
 133         tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
 134         tmcon &= ~TMCON_T0EN;
 135         tmcon &= ~TMCON_T1EN;
 136         writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
 137
 138         /*
 139          * Use timer 1 to fire IRQs on the timeline, minimum 2 cycles
 140          * (one on each counter) maximum 2*2^32, but the API will only
 141          * accept up to a 32bit full word (0xFFFFFFFFU).
 142          */
 143         clockevents_config_and_register(&clockevent_ks8695,
 144                                         KS8695_CLOCK_RATE, 2,
 145                                         0xFFFFFFFFU);
 146 }
 147
 148 void __init ks8695_timer_init(void)
 149 {
 150         ks8695_timer_setup();
 151
 152         /* Enable timer interrupts */
 153         setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq);
 154 }
 155
 156 void ks8695_restart(enum reboot_mode reboot_mode, const char *cmd)
 157 {
 158         unsigned int reg;
 159
 160         if (reboot_mode == REBOOT_SOFT)
 161                 soft_restart(0);
 162
 163         /* disable timer0 */
 164         reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
 165         writel_relaxed(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
 166
 167         /* enable watchdog mode */
 168         writel_relaxed((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
 169
 170         /* re-enable timer0 */
 171         writel_relaxed(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
 172 }