arch/arm/mach-zynq/pm.c

   1 /*
   2  * Zynq power management
   3  *
   4  *  Copyright (C) 2012 - 2014 Xilinx
   5  *
   6  *  Sören Brinkmann <soren.brinkmann@xilinx.com>
   7  *
   8  * This program is free software: you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation, either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/io.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_device.h>
  25 #include "common.h"
  26
  27 /* register offsets */
  28 #define DDRC_CTRL_REG1_OFFS             0x60
  29 #define DDRC_DRAM_PARAM_REG3_OFFS       0x20
  30
  31 /* bitfields */
  32 #define DDRC_CLOCKSTOP_MASK     BIT(23)
  33 #define DDRC_SELFREFRESH_MASK   BIT(12)
  34
  35 static void __iomem *ddrc_base;
  36
  37 /**
  38  * zynq_pm_ioremap() - Create IO mappings
  39  * @comp:       DT compatible string
  40  * Return: Pointer to the mapped memory or NULL.
  41  *
  42  * Remap the memory region for a compatible DT node.
  43  */
  44 static void __iomem *zynq_pm_ioremap(const char *comp)
  45 {
  46         struct device_node *np;
  47         void __iomem *base = NULL;
  48
  49         np = of_find_compatible_node(NULL, NULL, comp);
  50         if (np) {
  51                 base = of_iomap(np, 0);
  52                 of_node_put(np);
  53         } else {
  54                 pr_warn("%s: no compatible node found for '%s'\n", __func__,
  55                                 comp);
  56         }
  57
  58         return base;
  59 }
  60
  61 /**
  62  * zynq_pm_late_init() - Power management init
  63  *
  64  * Initialization of power management related features and infrastructure.
  65  */
  66 void __init zynq_pm_late_init(void)
  67 {
  68         u32 reg;
  69
  70         ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05");
  71         if (!ddrc_base) {
  72                 pr_warn("%s: Unable to map DDRC IO memory.\n", __func__);
  73         } else {
  74                 /*
  75                  * Enable DDRC clock stop feature. The HW takes care of
  76                  * entering/exiting the correct mode depending
  77                  * on activity state.
  78                  */
  79                 reg = readl(ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS);
  80                 reg |= DDRC_CLOCKSTOP_MASK;
  81                 writel(reg, ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS);
  82         }
  83 }