arch/arm/mach-zynq/slcr.c

   1 /*
   2  * Xilinx SLCR driver
   3  *
   4  * Copyright (c) 2011-2013 Xilinx Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  *
  11  * You should have received a copy of the GNU General Public
  12  * License along with this program; if not, write to the Free
  13  * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
  14  * 02139, USA.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/reboot.h>
  19 #include <linux/mfd/syscon.h>
  20 #include <linux/of_address.h>
  21 #include <linux/regmap.h>
  22 #include <linux/clk/zynq.h>
  23 #include "common.h"
  24
  25 /* register offsets */
  26 #define SLCR_UNLOCK_OFFSET              0x8   /* SCLR unlock register */
  27 #define SLCR_PS_RST_CTRL_OFFSET         0x200 /* PS Software Reset Control */
  28 #define SLCR_A9_CPU_RST_CTRL_OFFSET     0x244 /* CPU Software Reset Control */
  29 #define SLCR_REBOOT_STATUS_OFFSET       0x258 /* PS Reboot Status */
  30 #define SLCR_PSS_IDCODE                 0x530 /* PS IDCODE */
  31
  32 #define SLCR_UNLOCK_MAGIC               0xDF0D
  33 #define SLCR_A9_CPU_CLKSTOP             0x10
  34 #define SLCR_A9_CPU_RST                 0x1
  35 #define SLCR_PSS_IDCODE_DEVICE_SHIFT    12
  36 #define SLCR_PSS_IDCODE_DEVICE_MASK     0x1F
  37
  38 static void __iomem *zynq_slcr_base;
  39 static struct regmap *zynq_slcr_regmap;
  40
  41 /**
  42  * zynq_slcr_write - Write to a register in SLCR block
  43  *
  44  * @val:        Value to write to the register
  45  * @offset:     Register offset in SLCR block
  46  *
  47  * Return:      a negative value on error, 0 on success
  48  */
  49 static int zynq_slcr_write(u32 val, u32 offset)
  50 {
  51         return regmap_write(zynq_slcr_regmap, offset, val);
  52 }
  53
  54 /**
  55  * zynq_slcr_read - Read a register in SLCR block
  56  *
  57  * @val:        Pointer to value to be read from SLCR
  58  * @offset:     Register offset in SLCR block
  59  *
  60  * Return:      a negative value on error, 0 on success
  61  */
  62 static int zynq_slcr_read(u32 *val, u32 offset)
  63 {
  64         return regmap_read(zynq_slcr_regmap, offset, val);
  65 }
  66
  67 /**
  68  * zynq_slcr_unlock - Unlock SLCR registers
  69  *
  70  * Return:      a negative value on error, 0 on success
  71  */
  72 static inline int zynq_slcr_unlock(void)
  73 {
  74         zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET);
  75
  76         return 0;
  77 }
  78
  79 /**
  80  * zynq_slcr_get_device_id - Read device code id
  81  *
  82  * Return:      Device code id
  83  */
  84 u32 zynq_slcr_get_device_id(void)
  85 {
  86         u32 val;
  87
  88         zynq_slcr_read(&val, SLCR_PSS_IDCODE);
  89         val >>= SLCR_PSS_IDCODE_DEVICE_SHIFT;
  90         val &= SLCR_PSS_IDCODE_DEVICE_MASK;
  91
  92         return val;
  93 }
  94
  95 /**
  96  * zynq_slcr_system_restart - Restart the entire system.
  97  *
  98  * @nb:         Pointer to restart notifier block (unused)
  99  * @action:     Reboot mode (unused)
 100  * @data:       Restart handler private data (unused)
 101  *
 102  * Return:      0 always
 103  */
 104 static
 105 int zynq_slcr_system_restart(struct notifier_block *nb,
 106                              unsigned long action, void *data)
 107 {
 108         u32 reboot;
 109
 110         /*
 111          * Clear 0x0F000000 bits of reboot status register to workaround
 112          * the FSBL not loading the bitstream after soft-reboot
 113          * This is a temporary solution until we know more.
 114          */
 115         zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
 116         zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
 117         zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
 118         return 0;
 119 }
 120
 121 static struct notifier_block zynq_slcr_restart_nb = {
 122         .notifier_call  = zynq_slcr_system_restart,
 123         .priority       = 192,
 124 };
 125
 126 /**
 127  * zynq_slcr_cpu_start - Start cpu
 128  * @cpu:        cpu number
 129  */
 130 void zynq_slcr_cpu_start(int cpu)
 131 {
 132         u32 reg;
 133
 134         zynq_slcr_read(&reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
 135         reg &= ~(SLCR_A9_CPU_RST << cpu);
 136         zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
 137         reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
 138         zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
 139
 140         zynq_slcr_cpu_state_write(cpu, false);
 141 }
 142
 143 /**
 144  * zynq_slcr_cpu_stop - Stop cpu
 145  * @cpu:        cpu number
 146  */
 147 void zynq_slcr_cpu_stop(int cpu)
 148 {
 149         u32 reg;
 150
 151         zynq_slcr_read(&reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
 152         reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
 153         zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
 154 }
 155
 156 /**
 157  * zynq_slcr_cpu_state - Read/write cpu state
 158  * @cpu:        cpu number
 159  *
 160  * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
 161  * 0 means cpu is running, 1 cpu is going to die.
 162  *
 163  * Return: true if cpu is running, false if cpu is going to die
 164  */
 165 bool zynq_slcr_cpu_state_read(int cpu)
 166 {
 167         u32 state;
 168
 169         state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
 170         state &= 1 << (31 - cpu);
 171
 172         return !state;
 173 }
 174
 175 /**
 176  * zynq_slcr_cpu_state - Read/write cpu state
 177  * @cpu:        cpu number
 178  * @die:        cpu state - true if cpu is going to die
 179  *
 180  * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
 181  * 0 means cpu is running, 1 cpu is going to die.
 182  */
 183 void zynq_slcr_cpu_state_write(int cpu, bool die)
 184 {
 185         u32 state, mask;
 186
 187         state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
 188         mask = 1 << (31 - cpu);
 189         if (die)
 190                 state |= mask;
 191         else
 192                 state &= ~mask;
 193         writel(state, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
 194 }
 195
 196 /**
 197  * zynq_early_slcr_init - Early slcr init function
 198  *
 199  * Return:      0 on success, negative errno otherwise.
 200  *
 201  * Called very early during boot from platform code to unlock SLCR.
 202  */
 203 int __init zynq_early_slcr_init(void)
 204 {
 205         struct device_node *np;
 206
 207         np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
 208         if (!np) {
 209                 pr_err("%s: no slcr node found\n", __func__);
 210                 BUG();
 211         }
 212
 213         zynq_slcr_base = of_iomap(np, 0);
 214         if (!zynq_slcr_base) {
 215                 pr_err("%s: Unable to map I/O memory\n", __func__);
 216                 BUG();
 217         }
 218
 219         np->data = (__force void *)zynq_slcr_base;
 220
 221         zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
 222         if (IS_ERR(zynq_slcr_regmap)) {
 223                 pr_err("%s: failed to find zynq-slcr\n", __func__);
 224                 return -ENODEV;
 225         }
 226
 227         /* unlock the SLCR so that registers can be changed */
 228         zynq_slcr_unlock();
 229
 230         register_restart_handler(&zynq_slcr_restart_nb);
 231
 232         pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
 233
 234         of_node_put(np);
 235
 236         return 0;
 237 }