arch/x86/kernel/mmconf-fam10h_64.c

   1 /*
   2  * AMD Family 10h mmconfig enablement
   3  */
   4
   5 #include <linux/types.h>
   6 #include <linux/mm.h>
   7 #include <linux/string.h>
   8 #include <linux/pci.h>
   9 #include <linux/dmi.h>
  10 #include <linux/range.h>
  11
  12 #include <asm/pci-direct.h>
  13 #include <linux/sort.h>
  14 #include <asm/io.h>
  15 #include <asm/msr.h>
  16 #include <asm/acpi.h>
  17 #include <asm/mmconfig.h>
  18 #include <asm/pci_x86.h>
  19
  20 struct pci_hostbridge_probe {
  21         u32 bus;
  22         u32 slot;
  23         u32 vendor;
  24         u32 device;
  25 };
  26
  27 static u64 fam10h_pci_mmconf_base;
  28
  29 static struct pci_hostbridge_probe pci_probes[] = {
  30         { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
  31         { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
  32 };
  33
  34 static int cmp_range(const void *x1, const void *x2)
  35 {
  36         const struct range *r1 = x1;
  37         const struct range *r2 = x2;
  38         int start1, start2;
  39
  40         start1 = r1->start >> 32;
  41         start2 = r2->start >> 32;
  42
  43         return start1 - start2;
  44 }
  45
  46 #define MMCONF_UNIT (1ULL << FAM10H_MMIO_CONF_BASE_SHIFT)
  47 #define MMCONF_MASK (~(MMCONF_UNIT - 1))
  48 #define MMCONF_SIZE (MMCONF_UNIT << 8)
  49 /* need to avoid (0xfd<<32), (0xfe<<32), and (0xff<<32), ht used space */
  50 #define FAM10H_PCI_MMCONF_BASE (0xfcULL<<32)
  51 #define BASE_VALID(b) ((b) + MMCONF_SIZE <= (0xfdULL<<32) || (b) >= (1ULL<<40))
  52 static void get_fam10h_pci_mmconf_base(void)
  53 {
  54         int i;
  55         unsigned bus;
  56         unsigned slot;
  57         int found;
  58
  59         u64 val;
  60         u32 address;
  61         u64 tom2;
  62         u64 base = FAM10H_PCI_MMCONF_BASE;
  63
  64         int hi_mmio_num;
  65         struct range range[8];
  66
  67         /* only try to get setting from BSP */
  68         if (fam10h_pci_mmconf_base)
  69                 return;
  70
  71         if (!early_pci_allowed())
  72                 return;
  73
  74         found = 0;
  75         for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
  76                 u32 id;
  77                 u16 device;
  78                 u16 vendor;
  79
  80                 bus = pci_probes[i].bus;
  81                 slot = pci_probes[i].slot;
  82                 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
  83
  84                 vendor = id & 0xffff;
  85                 device = (id>>16) & 0xffff;
  86                 if (pci_probes[i].vendor == vendor &&
  87                     pci_probes[i].device == device) {
  88                         found = 1;
  89                         break;
  90                 }
  91         }
  92
  93         if (!found)
  94                 return;
  95
  96         /* SYS_CFG */
  97         address = MSR_K8_SYSCFG;
  98         rdmsrl(address, val);
  99
 100         /* TOP_MEM2 is not enabled? */
 101         if (!(val & (1<<21))) {
 102                 tom2 = 1ULL << 32;
 103         } else {
 104                 /* TOP_MEM2 */
 105                 address = MSR_K8_TOP_MEM2;
 106                 rdmsrl(address, val);
 107                 tom2 = max(val & 0xffffff800000ULL, 1ULL << 32);
 108         }
 109
 110         if (base <= tom2)
 111                 base = (tom2 + 2 * MMCONF_UNIT - 1) & MMCONF_MASK;
 112
 113         /*
 114          * need to check if the range is in the high mmio range that is
 115          * above 4G
 116          */
 117         hi_mmio_num = 0;
 118         for (i = 0; i < 8; i++) {
 119                 u32 reg;
 120                 u64 start;
 121                 u64 end;
 122                 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
 123                 if (!(reg & 3))
 124                         continue;
 125
 126                 start = (u64)(reg & 0xffffff00) << 8; /* 39:16 on 31:8*/
 127                 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
 128                 end = ((u64)(reg & 0xffffff00) << 8) | 0xffff; /* 39:16 on 31:8*/
 129
 130                 if (end < tom2)
 131                         continue;
 132
 133                 range[hi_mmio_num].start = start;
 134                 range[hi_mmio_num].end = end;
 135                 hi_mmio_num++;
 136         }
 137
 138         if (!hi_mmio_num)
 139                 goto out;
 140
 141         /* sort the range */
 142         sort(range, hi_mmio_num, sizeof(struct range), cmp_range, NULL);
 143
 144         if (range[hi_mmio_num - 1].end < base)
 145                 goto out;
 146         if (range[0].start > base + MMCONF_SIZE)
 147                 goto out;
 148
 149         /* need to find one window */
 150         base = (range[0].start & MMCONF_MASK) - MMCONF_UNIT;
 151         if ((base > tom2) && BASE_VALID(base))
 152                 goto out;
 153         base = (range[hi_mmio_num - 1].end + MMCONF_UNIT) & MMCONF_MASK;
 154         if (BASE_VALID(base))
 155                 goto out;
 156         /* need to find window between ranges */
 157         for (i = 1; i < hi_mmio_num; i++) {
 158                 base = (range[i - 1].end + MMCONF_UNIT) & MMCONF_MASK;
 159                 val = range[i].start & MMCONF_MASK;
 160                 if (val >= base + MMCONF_SIZE && BASE_VALID(base))
 161                         goto out;
 162         }
 163         return;
 164
 165 out:
 166         fam10h_pci_mmconf_base = base;
 167 }
 168
 169 void fam10h_check_enable_mmcfg(void)
 170 {
 171         u64 val;
 172         u32 address;
 173
 174         if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
 175                 return;
 176
 177         address = MSR_FAM10H_MMIO_CONF_BASE;
 178         rdmsrl(address, val);
 179
 180         /* try to make sure that AP's setting is identical to BSP setting */
 181         if (val & FAM10H_MMIO_CONF_ENABLE) {
 182                 unsigned busnbits;
 183                 busnbits = (val >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
 184                         FAM10H_MMIO_CONF_BUSRANGE_MASK;
 185
 186                 /* only trust the one handle 256 buses, if acpi=off */
 187                 if (!acpi_pci_disabled || busnbits >= 8) {
 188                         u64 base = val & MMCONF_MASK;
 189
 190                         if (!fam10h_pci_mmconf_base) {
 191                                 fam10h_pci_mmconf_base = base;
 192                                 return;
 193                         } else if (fam10h_pci_mmconf_base ==  base)
 194                                 return;
 195                 }
 196         }
 197
 198         /*
 199          * if it is not enabled, try to enable it and assume only one segment
 200          * with 256 buses
 201          */
 202         get_fam10h_pci_mmconf_base();
 203         if (!fam10h_pci_mmconf_base) {
 204                 pci_probe &= ~PCI_CHECK_ENABLE_AMD_MMCONF;
 205                 return;
 206         }
 207
 208         printk(KERN_INFO "Enable MMCONFIG on AMD Family 10h\n");
 209         val &= ~((FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT) |
 210              (FAM10H_MMIO_CONF_BUSRANGE_MASK<<FAM10H_MMIO_CONF_BUSRANGE_SHIFT));
 211         val |= fam10h_pci_mmconf_base | (8 << FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
 212                FAM10H_MMIO_CONF_ENABLE;
 213         wrmsrl(address, val);
 214 }
 215
 216 static int __init set_check_enable_amd_mmconf(const struct dmi_system_id *d)
 217 {
 218         pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
 219         return 0;
 220 }
 221
 222 static const struct dmi_system_id __initconst mmconf_dmi_table[] = {
 223         {
 224                 .callback = set_check_enable_amd_mmconf,
 225                 .ident = "Sun Microsystems Machine",
 226                 .matches = {
 227                         DMI_MATCH(DMI_SYS_VENDOR, "Sun Microsystems"),
 228                 },
 229         },
 230         {}
 231 };
 232
 233 /* Called from a non __init function, but only on the BSP. */
 234 void __ref check_enable_amd_mmconf_dmi(void)
 235 {
 236         dmi_check_system(mmconf_dmi_table);
 237 }