?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
usb: musb: drop unneeded musb_debug trickery
[linux/fpc-iii.git] / drivers / usb / musb / tusb6010.c
blob2f683a67ebb4b0dc95a760b946298bfbaf2f7f39
1 /*
2 * TUSB6010 USB 2.0 OTG Dual Role controller
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Notes:
12 * - Driver assumes that interface to external host (main CPU) is
13 * configured for NOR FLASH interface instead of VLYNQ serial
14 * interface.
15 */
16
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/init.h>
21 #include <linux/usb.h>
22 #include <linux/irq.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25
26 #include "musb_core.h"
27
28 struct tusb6010_glue {
29 struct device *dev;
30 struct platform_device *musb;
31 };
32
33 static void tusb_musb_set_vbus(struct musb *musb, int is_on);
34
35 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
36 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
37
38 /*
39 * Checks the revision. We need to use the DMA register as 3.0 does not
40 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
41 */
42 u8 tusb_get_revision(struct musb *musb)
43 {
44 void __iomem *tbase = musb->ctrl_base;
45 u32 die_id;
46 u8 rev;
47
48 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
49 if (TUSB_REV_MAJOR(rev) == 3) {
50 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
51 TUSB_DIDR1_HI));
52 if (die_id >= TUSB_DIDR1_HI_REV_31)
53 rev |= 1;
54 }
55
56 return rev;
57 }
58
59 static int tusb_print_revision(struct musb *musb)
60 {
61 void __iomem *tbase = musb->ctrl_base;
62 u8 rev;
63
64 rev = tusb_get_revision(musb);
65
66 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
67 "prcm",
68 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
69 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
70 "int",
71 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
72 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
73 "gpio",
74 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
75 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
76 "dma",
77 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
78 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
79 "dieid",
80 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
81 "rev",
82 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
83
84 return tusb_get_revision(musb);
85 }
86
87 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
88 | TUSB_PHY_OTG_CTRL_TESTM0)
89
90 /*
91 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
92 * Disables power detection in PHY for the duration of idle.
93 */
94 static void tusb_wbus_quirk(struct musb *musb, int enabled)
95 {
96 void __iomem *tbase = musb->ctrl_base;
97 static u32 phy_otg_ctrl, phy_otg_ena;
98 u32 tmp;
99
100 if (enabled) {
101 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
102 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
103 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
104 | phy_otg_ena | WBUS_QUIRK_MASK;
105 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
106 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
107 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
108 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
109 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
110 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
111 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
112 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
113 & TUSB_PHY_OTG_CTRL_TESTM2) {
114 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
115 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
116 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
117 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
118 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
119 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
120 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
121 phy_otg_ctrl = 0;
122 phy_otg_ena = 0;
123 }
124 }
125
126 /*
127 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
128 * so both loading and unloading FIFOs need explicit byte counts.
129 */
130
131 static inline void
132 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
133 {
134 u32 val;
135 int i;
136
137 if (len > 4) {
138 for (i = 0; i < (len >> 2); i++) {
139 memcpy(&val, buf, 4);
140 musb_writel(fifo, 0, val);
141 buf += 4;
142 }
143 len %= 4;
144 }
145 if (len > 0) {
146 /* Write the rest 1 - 3 bytes to FIFO */
147 memcpy(&val, buf, len);
148 musb_writel(fifo, 0, val);
149 }
150 }
151
152 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
153 void __iomem *buf, u16 len)
154 {
155 u32 val;
156 int i;
157
158 if (len > 4) {
159 for (i = 0; i < (len >> 2); i++) {
160 val = musb_readl(fifo, 0);
161 memcpy(buf, &val, 4);
162 buf += 4;
163 }
164 len %= 4;
165 }
166 if (len > 0) {
167 /* Read the rest 1 - 3 bytes from FIFO */
168 val = musb_readl(fifo, 0);
169 memcpy(buf, &val, len);
170 }
171 }
172
173 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
174 {
175 void __iomem *ep_conf = hw_ep->conf;
176 void __iomem *fifo = hw_ep->fifo;
177 u8 epnum = hw_ep->epnum;
178
179 prefetch(buf);
180
181 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
182 'T', epnum, fifo, len, buf);
183
184 if (epnum)
185 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
186 TUSB_EP_CONFIG_XFR_SIZE(len));
187 else
188 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
189 TUSB_EP0_CONFIG_XFR_SIZE(len));
190
191 if (likely((0x01 & (unsigned long) buf) == 0)) {
192
193 /* Best case is 32bit-aligned destination address */
194 if ((0x02 & (unsigned long) buf) == 0) {
195 if (len >= 4) {
196 writesl(fifo, buf, len >> 2);
197 buf += (len & ~0x03);
198 len &= 0x03;
199 }
200 } else {
201 if (len >= 2) {
202 u32 val;
203 int i;
204
205 /* Cannot use writesw, fifo is 32-bit */
206 for (i = 0; i < (len >> 2); i++) {
207 val = (u32)(*(u16 *)buf);
208 buf += 2;
209 val |= (*(u16 *)buf) << 16;
210 buf += 2;
211 musb_writel(fifo, 0, val);
212 }
213 len &= 0x03;
214 }
215 }
216 }
217
218 if (len > 0)
219 tusb_fifo_write_unaligned(fifo, buf, len);
220 }
221
222 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
223 {
224 void __iomem *ep_conf = hw_ep->conf;
225 void __iomem *fifo = hw_ep->fifo;
226 u8 epnum = hw_ep->epnum;
227
228 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
229 'R', epnum, fifo, len, buf);
230
231 if (epnum)
232 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
233 TUSB_EP_CONFIG_XFR_SIZE(len));
234 else
235 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
236
237 if (likely((0x01 & (unsigned long) buf) == 0)) {
238
239 /* Best case is 32bit-aligned destination address */
240 if ((0x02 & (unsigned long) buf) == 0) {
241 if (len >= 4) {
242 readsl(fifo, buf, len >> 2);
243 buf += (len & ~0x03);
244 len &= 0x03;
245 }
246 } else {
247 if (len >= 2) {
248 u32 val;
249 int i;
250
251 /* Cannot use readsw, fifo is 32-bit */
252 for (i = 0; i < (len >> 2); i++) {
253 val = musb_readl(fifo, 0);
254 *(u16 *)buf = (u16)(val & 0xffff);
255 buf += 2;
256 *(u16 *)buf = (u16)(val >> 16);
257 buf += 2;
258 }
259 len &= 0x03;
260 }
261 }
262 }
263
264 if (len > 0)
265 tusb_fifo_read_unaligned(fifo, buf, len);
266 }
267
268 static struct musb *the_musb;
269
270 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
271
272 /* This is used by gadget drivers, and OTG transceiver logic, allowing
273 * at most mA current to be drawn from VBUS during a Default-B session
274 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
275 * mode), or low power Default-B sessions, something else supplies power.
276 * Caller must take care of locking.
277 */
278 static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
279 {
280 struct musb *musb = the_musb;
281 void __iomem *tbase = musb->ctrl_base;
282 u32 reg;
283
284 /* tps65030 seems to consume max 100mA, with maybe 60mA available
285 * (measured on one board) for things other than tps and tusb.
286 *
287 * Boards sharing the CPU clock with CLKIN will need to prevent
288 * certain idle sleep states while the USB link is active.
289 *
290 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
291 * The actual current usage would be very board-specific. For now,
292 * it's simpler to just use an aggregate (also board-specific).
293 */
294 if (x->default_a || mA < (musb->min_power << 1))
295 mA = 0;
296
297 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
298 if (mA) {
299 musb->is_bus_powered = 1;
300 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
301 } else {
302 musb->is_bus_powered = 0;
303 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
304 }
305 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
306
307 dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
308 return 0;
309 }
310
311 #else
312 #define tusb_draw_power NULL
313 #endif
314
315 /* workaround for issue 13: change clock during chip idle
316 * (to be fixed in rev3 silicon) ... symptoms include disconnect
317 * or looping suspend/resume cycles
318 */
319 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
320 {
321 void __iomem *tbase = musb->ctrl_base;
322 u32 reg;
323
324 reg = musb_readl(tbase, TUSB_PRCM_CONF);
325 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
326
327 /* 0 = refclk (clkin, XI)
328 * 1 = PHY 60 MHz (internal PLL)
329 * 2 = not supported
330 * 3 = what?
331 */
332 if (mode > 0)
333 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
334
335 musb_writel(tbase, TUSB_PRCM_CONF, reg);
336
337 /* FIXME tusb6010_platform_retime(mode == 0); */
338 }
339
340 /*
341 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
342 * Other code ensures that we idle unless we're connected _and_ the
343 * USB link is not suspended ... and tells us the relevant wakeup
344 * events. SW_EN for voltage is handled separately.
345 */
346 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
347 {
348 void __iomem *tbase = musb->ctrl_base;
349 u32 reg;
350
351 if ((wakeup_enables & TUSB_PRCM_WBUS)
352 && (tusb_get_revision(musb) == TUSB_REV_30))
353 tusb_wbus_quirk(musb, 1);
354
355 tusb_set_clock_source(musb, 0);
356
357 wakeup_enables |= TUSB_PRCM_WNORCS;
358 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
359
360 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
361 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
362 * Presumably that's mostly to save power, hence WID is immaterial ...
363 */
364
365 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
366 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
367 if (is_host_active(musb)) {
368 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
369 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
370 } else {
371 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
372 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
373 }
374 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
375 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
376
377 dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
378 }
379
380 /*
381 * Updates cable VBUS status. Caller must take care of locking.
382 */
383 static int tusb_musb_vbus_status(struct musb *musb)
384 {
385 void __iomem *tbase = musb->ctrl_base;
386 u32 otg_stat, prcm_mngmt;
387 int ret = 0;
388
389 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
390 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
391
392 /* Temporarily enable VBUS detection if it was disabled for
393 * suspend mode. Unless it's enabled otg_stat and devctl will
394 * not show correct VBUS state.
395 */
396 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
397 u32 tmp = prcm_mngmt;
398 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
399 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
400 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
401 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
402 }
403
404 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
405 ret = 1;
406
407 return ret;
408 }
409
410 static struct timer_list musb_idle_timer;
411
412 static void musb_do_idle(unsigned long _musb)
413 {
414 struct musb *musb = (void *)_musb;
415 unsigned long flags;
416
417 spin_lock_irqsave(&musb->lock, flags);
418
419 switch (musb->xceiv->state) {
420 case OTG_STATE_A_WAIT_BCON:
421 if ((musb->a_wait_bcon != 0)
422 && (musb->idle_timeout == 0
423 || time_after(jiffies, musb->idle_timeout))) {
424 dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
425 otg_state_string(musb->xceiv->state));
426 }
427 /* FALLTHROUGH */
428 case OTG_STATE_A_IDLE:
429 tusb_musb_set_vbus(musb, 0);
430 default:
431 break;
432 }
433
434 if (!musb->is_active) {
435 u32 wakeups;
436
437 /* wait until khubd handles port change status */
438 if (is_host_active(musb) && (musb->port1_status >> 16))
439 goto done;
440
441 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
442 if (is_peripheral_enabled(musb) && !musb->gadget_driver)
443 wakeups = 0;
444 else {
445 wakeups = TUSB_PRCM_WHOSTDISCON
446 | TUSB_PRCM_WBUS
447 | TUSB_PRCM_WVBUS;
448 if (is_otg_enabled(musb))
449 wakeups |= TUSB_PRCM_WID;
450 }
451 #else
452 wakeups = TUSB_PRCM_WHOSTDISCON | TUSB_PRCM_WBUS;
453 #endif
454 tusb_allow_idle(musb, wakeups);
455 }
456 done:
457 spin_unlock_irqrestore(&musb->lock, flags);
458 }
459
460 /*
461 * Maybe put TUSB6010 into idle mode mode depending on USB link status,
462 * like "disconnected" or "suspended". We'll be woken out of it by
463 * connect, resume, or disconnect.
464 *
465 * Needs to be called as the last function everywhere where there is
466 * register access to TUSB6010 because of NOR flash wake-up.
467 * Caller should own controller spinlock.
468 *
469 * Delay because peripheral enables D+ pullup 3msec after SE0, and
470 * we don't want to treat that full speed J as a wakeup event.
471 * ... peripherals must draw only suspend current after 10 msec.
472 */
473 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
474 {
475 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
476 static unsigned long last_timer;
477
478 if (timeout == 0)
479 timeout = default_timeout;
480
481 /* Never idle if active, or when VBUS timeout is not set as host */
482 if (musb->is_active || ((musb->a_wait_bcon == 0)
483 && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
484 dev_dbg(musb->controller, "%s active, deleting timer\n",
485 otg_state_string(musb->xceiv->state));
486 del_timer(&musb_idle_timer);
487 last_timer = jiffies;
488 return;
489 }
490
491 if (time_after(last_timer, timeout)) {
492 if (!timer_pending(&musb_idle_timer))
493 last_timer = timeout;
494 else {
495 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
496 return;
497 }
498 }
499 last_timer = timeout;
500
501 dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
502 otg_state_string(musb->xceiv->state),
503 (unsigned long)jiffies_to_msecs(timeout - jiffies));
504 mod_timer(&musb_idle_timer, timeout);
505 }
506
507 /* ticks of 60 MHz clock */
508 #define DEVCLOCK 60000000
509 #define OTG_TIMER_MS(msecs) ((msecs) \
510 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
511 | TUSB_DEV_OTG_TIMER_ENABLE) \
512 : 0)
513
514 static void tusb_musb_set_vbus(struct musb *musb, int is_on)
515 {
516 void __iomem *tbase = musb->ctrl_base;
517 u32 conf, prcm, timer;
518 u8 devctl;
519
520 /* HDRC controls CPEN, but beware current surges during device
521 * connect. They can trigger transient overcurrent conditions
522 * that must be ignored.
523 */
524
525 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
526 conf = musb_readl(tbase, TUSB_DEV_CONF);
527 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
528
529 if (is_on) {
530 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
531 musb->xceiv->default_a = 1;
532 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
533 devctl |= MUSB_DEVCTL_SESSION;
534
535 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
536 MUSB_HST_MODE(musb);
537 } else {
538 u32 otg_stat;
539
540 timer = 0;
541
542 /* If ID pin is grounded, we want to be a_idle */
543 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
544 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
545 switch (musb->xceiv->state) {
546 case OTG_STATE_A_WAIT_VRISE:
547 case OTG_STATE_A_WAIT_BCON:
548 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
549 break;
550 case OTG_STATE_A_WAIT_VFALL:
551 musb->xceiv->state = OTG_STATE_A_IDLE;
552 break;
553 default:
554 musb->xceiv->state = OTG_STATE_A_IDLE;
555 }
556 musb->is_active = 0;
557 musb->xceiv->default_a = 1;
558 MUSB_HST_MODE(musb);
559 } else {
560 musb->is_active = 0;
561 musb->xceiv->default_a = 0;
562 musb->xceiv->state = OTG_STATE_B_IDLE;
563 MUSB_DEV_MODE(musb);
564 }
565
566 devctl &= ~MUSB_DEVCTL_SESSION;
567 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
568 }
569 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
570
571 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
572 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
573 musb_writel(tbase, TUSB_DEV_CONF, conf);
574 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
575
576 dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
577 otg_state_string(musb->xceiv->state),
578 musb_readb(musb->mregs, MUSB_DEVCTL),
579 musb_readl(tbase, TUSB_DEV_OTG_STAT),
580 conf, prcm);
581 }
582
583 /*
584 * Sets the mode to OTG, peripheral or host by changing the ID detection.
585 * Caller must take care of locking.
586 *
587 * Note that if a mini-A cable is plugged in the ID line will stay down as
588 * the weak ID pull-up is not able to pull the ID up.
589 *
590 * REVISIT: It would be possible to add support for changing between host
591 * and peripheral modes in non-OTG configurations by reconfiguring hardware
592 * and then setting musb->board_mode. For now, only support OTG mode.
593 */
594 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
595 {
596 void __iomem *tbase = musb->ctrl_base;
597 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
598
599 if (musb->board_mode != MUSB_OTG) {
600 ERR("Changing mode currently only supported in OTG mode\n");
601 return -EINVAL;
602 }
603
604 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
605 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
606 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
607 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
608
609 switch (musb_mode) {
610
611 #ifdef CONFIG_USB_MUSB_HDRC_HCD
612 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
613 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
614 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
615 dev_conf |= TUSB_DEV_CONF_ID_SEL;
616 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
617 break;
618 #endif
619
620 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
621 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
622 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
623 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
624 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
625 break;
626 #endif
627
628 #ifdef CONFIG_USB_MUSB_OTG
629 case MUSB_OTG: /* Use PHY ID detection */
630 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
631 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
632 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
633 break;
634 #endif
635
636 default:
637 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
638 return -EINVAL;
639 }
640
641 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
642 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
643 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
644 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
645 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
646
647 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
648 if ((musb_mode == MUSB_PERIPHERAL) &&
649 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
650 INFO("Cannot be peripheral with mini-A cable "
651 "otg_stat: %08x\n", otg_stat);
652
653 return 0;
654 }
655
656 static inline unsigned long
657 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
658 {
659 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
660 unsigned long idle_timeout = 0;
661
662 /* ID pin */
663 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
664 int default_a;
665
666 if (is_otg_enabled(musb))
667 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
668 else
669 default_a = is_host_enabled(musb);
670 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
671 musb->xceiv->default_a = default_a;
672 tusb_musb_set_vbus(musb, default_a);
673
674 /* Don't allow idling immediately */
675 if (default_a)
676 idle_timeout = jiffies + (HZ * 3);
677 }
678
679 /* VBUS state change */
680 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
681
682 /* B-dev state machine: no vbus ~= disconnect */
683 if ((is_otg_enabled(musb) && !musb->xceiv->default_a)
684 || !is_host_enabled(musb)) {
685 #ifdef CONFIG_USB_MUSB_HDRC_HCD
686 /* ? musb_root_disconnect(musb); */
687 musb->port1_status &=
688 ~(USB_PORT_STAT_CONNECTION
689 | USB_PORT_STAT_ENABLE
690 | USB_PORT_STAT_LOW_SPEED
691 | USB_PORT_STAT_HIGH_SPEED
692 | USB_PORT_STAT_TEST
693 );
694 #endif
695
696 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
697 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
698 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
699 /* INTR_DISCONNECT can hide... */
700 musb->xceiv->state = OTG_STATE_B_IDLE;
701 musb->int_usb |= MUSB_INTR_DISCONNECT;
702 }
703 musb->is_active = 0;
704 }
705 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
706 otg_state_string(musb->xceiv->state), otg_stat);
707 idle_timeout = jiffies + (1 * HZ);
708 schedule_work(&musb->irq_work);
709
710 } else /* A-dev state machine */ {
711 dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
712 otg_state_string(musb->xceiv->state), otg_stat);
713
714 switch (musb->xceiv->state) {
715 case OTG_STATE_A_IDLE:
716 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
717 musb_platform_set_vbus(musb, 1);
718
719 /* CONNECT can wake if a_wait_bcon is set */
720 if (musb->a_wait_bcon != 0)
721 musb->is_active = 0;
722 else
723 musb->is_active = 1;
724
725 /*
726 * OPT FS A TD.4.6 needs few seconds for
727 * A_WAIT_VRISE
728 */
729 idle_timeout = jiffies + (2 * HZ);
730
731 break;
732 case OTG_STATE_A_WAIT_VRISE:
733 /* ignore; A-session-valid < VBUS_VALID/2,
734 * we monitor this with the timer
735 */
736 break;
737 case OTG_STATE_A_WAIT_VFALL:
738 /* REVISIT this irq triggers during short
739 * spikes caused by enumeration ...
740 */
741 if (musb->vbuserr_retry) {
742 musb->vbuserr_retry--;
743 tusb_musb_set_vbus(musb, 1);
744 } else {
745 musb->vbuserr_retry
746 = VBUSERR_RETRY_COUNT;
747 tusb_musb_set_vbus(musb, 0);
748 }
749 break;
750 default:
751 break;
752 }
753 }
754 }
755
756 /* OTG timer expiration */
757 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
758 u8 devctl;
759
760 dev_dbg(musb->controller, "%s timer, %03x\n",
761 otg_state_string(musb->xceiv->state), otg_stat);
762
763 switch (musb->xceiv->state) {
764 case OTG_STATE_A_WAIT_VRISE:
765 /* VBUS has probably been valid for a while now,
766 * but may well have bounced out of range a bit
767 */
768 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
769 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
770 if ((devctl & MUSB_DEVCTL_VBUS)
771 != MUSB_DEVCTL_VBUS) {
772 dev_dbg(musb->controller, "devctl %02x\n", devctl);
773 break;
774 }
775 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
776 musb->is_active = 0;
777 idle_timeout = jiffies
778 + msecs_to_jiffies(musb->a_wait_bcon);
779 } else {
780 /* REVISIT report overcurrent to hub? */
781 ERR("vbus too slow, devctl %02x\n", devctl);
782 tusb_musb_set_vbus(musb, 0);
783 }
784 break;
785 case OTG_STATE_A_WAIT_BCON:
786 if (musb->a_wait_bcon != 0)
787 idle_timeout = jiffies
788 + msecs_to_jiffies(musb->a_wait_bcon);
789 break;
790 case OTG_STATE_A_SUSPEND:
791 break;
792 case OTG_STATE_B_WAIT_ACON:
793 break;
794 default:
795 break;
796 }
797 }
798 schedule_work(&musb->irq_work);
799
800 return idle_timeout;
801 }
802
803 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
804 {
805 struct musb *musb = __hci;
806 void __iomem *tbase = musb->ctrl_base;
807 unsigned long flags, idle_timeout = 0;
808 u32 int_mask, int_src;
809
810 spin_lock_irqsave(&musb->lock, flags);
811
812 /* Mask all interrupts to allow using both edge and level GPIO irq */
813 int_mask = musb_readl(tbase, TUSB_INT_MASK);
814 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
815
816 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
817 dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
818
819 musb->int_usb = (u8) int_src;
820
821 /* Acknowledge wake-up source interrupts */
822 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
823 u32 reg;
824 u32 i;
825
826 if (tusb_get_revision(musb) == TUSB_REV_30)
827 tusb_wbus_quirk(musb, 0);
828
829 /* there are issues re-locking the PLL on wakeup ... */
830
831 /* work around issue 8 */
832 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
833 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
834 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
835 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
836 if (reg == i)
837 break;
838 dev_dbg(musb->controller, "TUSB NOR not ready\n");
839 }
840
841 /* work around issue 13 (2nd half) */
842 tusb_set_clock_source(musb, 1);
843
844 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
845 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
846 if (reg & ~TUSB_PRCM_WNORCS) {
847 musb->is_active = 1;
848 schedule_work(&musb->irq_work);
849 }
850 dev_dbg(musb->controller, "wake %sactive %02x\n",
851 musb->is_active ? "" : "in", reg);
852
853 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
854 }
855
856 if (int_src & TUSB_INT_SRC_USB_IP_CONN)
857 del_timer(&musb_idle_timer);
858
859 /* OTG state change reports (annoyingly) not issued by Mentor core */
860 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
861 | TUSB_INT_SRC_OTG_TIMEOUT
862 | TUSB_INT_SRC_ID_STATUS_CHNG))
863 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
864
865 /* TX dma callback must be handled here, RX dma callback is
866 * handled in tusb_omap_dma_cb.
867 */
868 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
869 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
870 u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
871
872 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
873 real_dma_src = ~real_dma_src & dma_src;
874 if (tusb_dma_omap() && real_dma_src) {
875 int tx_source = (real_dma_src & 0xffff);
876 int i;
877
878 for (i = 1; i <= 15; i++) {
879 if (tx_source & (1 << i)) {
880 dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
881 musb_dma_completion(musb, i, 1);
882 }
883 }
884 }
885 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
886 }
887
888 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
889 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
890 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
891
892 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
893 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
894 musb->int_tx = (musb_src & 0xffff);
895 } else {
896 musb->int_rx = 0;
897 musb->int_tx = 0;
898 }
899
900 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
901 musb_interrupt(musb);
902
903 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
904 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
905 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
906
907 tusb_musb_try_idle(musb, idle_timeout);
908
909 musb_writel(tbase, TUSB_INT_MASK, int_mask);
910 spin_unlock_irqrestore(&musb->lock, flags);
911
912 return IRQ_HANDLED;
913 }
914
915 static int dma_off;
916
917 /*
918 * Enables TUSB6010. Caller must take care of locking.
919 * REVISIT:
920 * - Check what is unnecessary in MGC_HdrcStart()
921 */
922 static void tusb_musb_enable(struct musb *musb)
923 {
924 void __iomem *tbase = musb->ctrl_base;
925
926 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
927 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
928 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
929
930 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
931 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
932 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
933 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
934
935 /* Clear all subsystem interrups */
936 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
937 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
938 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
939
940 /* Acknowledge pending interrupt(s) */
941 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
942
943 /* Only 0 clock cycles for minimum interrupt de-assertion time and
944 * interrupt polarity active low seems to work reliably here */
945 musb_writel(tbase, TUSB_INT_CTRL_CONF,
946 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
947
948 irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
949
950 /* maybe force into the Default-A OTG state machine */
951 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
952 & TUSB_DEV_OTG_STAT_ID_STATUS))
953 musb_writel(tbase, TUSB_INT_SRC_SET,
954 TUSB_INT_SRC_ID_STATUS_CHNG);
955
956 if (is_dma_capable() && dma_off)
957 printk(KERN_WARNING "%s %s: dma not reactivated\n",
958 __FILE__, __func__);
959 else
960 dma_off = 1;
961 }
962
963 /*
964 * Disables TUSB6010. Caller must take care of locking.
965 */
966 static void tusb_musb_disable(struct musb *musb)
967 {
968 void __iomem *tbase = musb->ctrl_base;
969
970 /* FIXME stop DMA, IRQs, timers, ... */
971
972 /* disable all IRQs */
973 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
974 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
975 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
976 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
977
978 del_timer(&musb_idle_timer);
979
980 if (is_dma_capable() && !dma_off) {
981 printk(KERN_WARNING "%s %s: dma still active\n",
982 __FILE__, __func__);
983 dma_off = 1;
984 }
985 }
986
987 /*
988 * Sets up TUSB6010 CPU interface specific signals and registers
989 * Note: Settings optimized for OMAP24xx
990 */
991 static void tusb_setup_cpu_interface(struct musb *musb)
992 {
993 void __iomem *tbase = musb->ctrl_base;
994
995 /*
996 * Disable GPIO[5:0] pullups (used as output DMA requests)
997 * Don't disable GPIO[7:6] as they are needed for wake-up.
998 */
999 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
1000
1001 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
1002 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
1003
1004 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
1005 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
1006
1007 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
1008 * de-assertion time 2 system clocks p 62 */
1009 musb_writel(tbase, TUSB_DMA_REQ_CONF,
1010 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
1011 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
1012 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
1013
1014 /* Set 0 wait count for synchronous burst access */
1015 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1016 }
1017
1018 static int tusb_musb_start(struct musb *musb)
1019 {
1020 void __iomem *tbase = musb->ctrl_base;
1021 int ret = 0;
1022 unsigned long flags;
1023 u32 reg;
1024
1025 if (musb->board_set_power)
1026 ret = musb->board_set_power(1);
1027 if (ret != 0) {
1028 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1029 return ret;
1030 }
1031
1032 spin_lock_irqsave(&musb->lock, flags);
1033
1034 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1035 TUSB_PROD_TEST_RESET_VAL) {
1036 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1037 goto err;
1038 }
1039
1040 ret = tusb_print_revision(musb);
1041 if (ret < 2) {
1042 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1043 ret);
1044 goto err;
1045 }
1046
1047 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1048 * NOR FLASH interface is used */
1049 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1050
1051 /* Select PHY free running 60MHz as a system clock */
1052 tusb_set_clock_source(musb, 1);
1053
1054 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1055 * power saving, enable VBus detect and session end comparators,
1056 * enable IDpullup, enable VBus charging */
1057 musb_writel(tbase, TUSB_PRCM_MNGMT,
1058 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1059 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1060 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1061 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1062 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1063 tusb_setup_cpu_interface(musb);
1064
1065 /* simplify: always sense/pullup ID pins, as if in OTG mode */
1066 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1067 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1068 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1069
1070 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1071 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1072 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1073
1074 spin_unlock_irqrestore(&musb->lock, flags);
1075
1076 return 0;
1077
1078 err:
1079 spin_unlock_irqrestore(&musb->lock, flags);
1080
1081 if (musb->board_set_power)
1082 musb->board_set_power(0);
1083
1084 return -ENODEV;
1085 }
1086
1087 static int tusb_musb_init(struct musb *musb)
1088 {
1089 struct platform_device *pdev;
1090 struct resource *mem;
1091 void __iomem *sync = NULL;
1092 int ret;
1093
1094 usb_nop_xceiv_register();
1095 musb->xceiv = otg_get_transceiver();
1096 if (!musb->xceiv)
1097 return -ENODEV;
1098
1099 pdev = to_platform_device(musb->controller);
1100
1101 /* dma address for async dma */
1102 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1103 musb->async = mem->start;
1104
1105 /* dma address for sync dma */
1106 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1107 if (!mem) {
1108 pr_debug("no sync dma resource?\n");
1109 ret = -ENODEV;
1110 goto done;
1111 }
1112 musb->sync = mem->start;
1113
1114 sync = ioremap(mem->start, resource_size(mem));
1115 if (!sync) {
1116 pr_debug("ioremap for sync failed\n");
1117 ret = -ENOMEM;
1118 goto done;
1119 }
1120 musb->sync_va = sync;
1121
1122 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1123 * FIFOs at 0x600, TUSB at 0x800
1124 */
1125 musb->mregs += TUSB_BASE_OFFSET;
1126
1127 ret = tusb_musb_start(musb);
1128 if (ret) {
1129 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1130 ret);
1131 goto done;
1132 }
1133 musb->isr = tusb_musb_interrupt;
1134
1135 if (is_peripheral_enabled(musb)) {
1136 musb->xceiv->set_power = tusb_draw_power;
1137 the_musb = musb;
1138 }
1139
1140 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1141
1142 done:
1143 if (ret < 0) {
1144 if (sync)
1145 iounmap(sync);
1146
1147 otg_put_transceiver(musb->xceiv);
1148 usb_nop_xceiv_unregister();
1149 }
1150 return ret;
1151 }
1152
1153 static int tusb_musb_exit(struct musb *musb)
1154 {
1155 del_timer_sync(&musb_idle_timer);
1156 the_musb = NULL;
1157
1158 if (musb->board_set_power)
1159 musb->board_set_power(0);
1160
1161 iounmap(musb->sync_va);
1162
1163 otg_put_transceiver(musb->xceiv);
1164 usb_nop_xceiv_unregister();
1165 return 0;
1166 }
1167
1168 static const struct musb_platform_ops tusb_ops = {
1169 .init = tusb_musb_init,
1170 .exit = tusb_musb_exit,
1171
1172 .enable = tusb_musb_enable,
1173 .disable = tusb_musb_disable,
1174
1175 .set_mode = tusb_musb_set_mode,
1176 .try_idle = tusb_musb_try_idle,
1177
1178 .vbus_status = tusb_musb_vbus_status,
1179 .set_vbus = tusb_musb_set_vbus,
1180 };
1181
1182 static u64 tusb_dmamask = DMA_BIT_MASK(32);
1183
1184 static int __init tusb_probe(struct platform_device *pdev)
1185 {
1186 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
1187 struct platform_device *musb;
1188 struct tusb6010_glue *glue;
1189
1190 int ret = -ENOMEM;
1191
1192 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
1193 if (!glue) {
1194 dev_err(&pdev->dev, "failed to allocate glue context\n");
1195 goto err0;
1196 }
1197
1198 musb = platform_device_alloc("musb-hdrc", -1);
1199 if (!musb) {
1200 dev_err(&pdev->dev, "failed to allocate musb device\n");
1201 goto err1;
1202 }
1203
1204 musb->dev.parent = &pdev->dev;
1205 musb->dev.dma_mask = &tusb_dmamask;
1206 musb->dev.coherent_dma_mask = tusb_dmamask;
1207
1208 glue->dev = &pdev->dev;
1209 glue->musb = musb;
1210
1211 pdata->platform_ops = &tusb_ops;
1212
1213 platform_set_drvdata(pdev, glue);
1214
1215 ret = platform_device_add_resources(musb, pdev->resource,
1216 pdev->num_resources);
1217 if (ret) {
1218 dev_err(&pdev->dev, "failed to add resources\n");
1219 goto err2;
1220 }
1221
1222 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
1223 if (ret) {
1224 dev_err(&pdev->dev, "failed to add platform_data\n");
1225 goto err2;
1226 }
1227
1228 ret = platform_device_add(musb);
1229 if (ret) {
1230 dev_err(&pdev->dev, "failed to register musb device\n");
1231 goto err1;
1232 }
1233
1234 return 0;
1235
1236 err2:
1237 platform_device_put(musb);
1238
1239 err1:
1240 kfree(glue);
1241
1242 err0:
1243 return ret;
1244 }
1245
1246 static int __exit tusb_remove(struct platform_device *pdev)
1247 {
1248 struct tusb6010_glue *glue = platform_get_drvdata(pdev);
1249
1250 platform_device_del(glue->musb);
1251 platform_device_put(glue->musb);
1252 kfree(glue);
1253
1254 return 0;
1255 }
1256
1257 static struct platform_driver tusb_driver = {
1258 .remove = __exit_p(tusb_remove),
1259 .driver = {
1260 .name = "musb-tusb",
1261 },
1262 };
1263
1264 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1265 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1266 MODULE_LICENSE("GPL v2");
1267
1268 static int __init tusb_init(void)
1269 {
1270 return platform_driver_probe(&tusb_driver, tusb_probe);
1271 }
1272 subsys_initcall(tusb_init);
1273
1274 static void __exit tusb_exit(void)
1275 {
1276 platform_driver_unregister(&tusb_driver);
1277 }
1278 module_exit(tusb_exit);
Linux with added FPC-III support