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Btrfs: fix list transaction->pending_ordered corruption
[linux/fpc-iii.git] / sound / soc / codecs / wm8990.c
blob03e43e3f395e5472a0028b5b28ea091f01238b7e
1 /*
2 * wm8990.c -- WM8990 ALSA Soc Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/pm.h>
19 #include <linux/i2c.h>
20 #include <linux/regmap.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
28 #include <asm/div64.h>
29
30 #include "wm8990.h"
31
32 /* codec private data */
33 struct wm8990_priv {
34 struct regmap *regmap;
35 unsigned int sysclk;
36 unsigned int pcmclk;
37 };
38
39 static bool wm8990_volatile_register(struct device *dev, unsigned int reg)
40 {
41 switch (reg) {
42 case WM8990_RESET:
43 return 1;
44 default:
45 return 0;
46 }
47 }
48
49 static const struct reg_default wm8990_reg_defaults[] = {
50 { 1, 0x0000 }, /* R1 - Power Management (1) */
51 { 2, 0x6000 }, /* R2 - Power Management (2) */
52 { 3, 0x0000 }, /* R3 - Power Management (3) */
53 { 4, 0x4050 }, /* R4 - Audio Interface (1) */
54 { 5, 0x4000 }, /* R5 - Audio Interface (2) */
55 { 6, 0x01C8 }, /* R6 - Clocking (1) */
56 { 7, 0x0000 }, /* R7 - Clocking (2) */
57 { 8, 0x0040 }, /* R8 - Audio Interface (3) */
58 { 9, 0x0040 }, /* R9 - Audio Interface (4) */
59 { 10, 0x0004 }, /* R10 - DAC CTRL */
60 { 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */
61 { 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */
62 { 13, 0x0000 }, /* R13 - Digital Side Tone */
63 { 14, 0x0100 }, /* R14 - ADC CTRL */
64 { 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */
65 { 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */
66
67 { 18, 0x0000 }, /* R18 - GPIO CTRL 1 */
68 { 19, 0x1000 }, /* R19 - GPIO1 & GPIO2 */
69 { 20, 0x1010 }, /* R20 - GPIO3 & GPIO4 */
70 { 21, 0x1010 }, /* R21 - GPIO5 & GPIO6 */
71 { 22, 0x8000 }, /* R22 - GPIOCTRL 2 */
72 { 23, 0x0800 }, /* R23 - GPIO_POL */
73 { 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
74 { 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
75 { 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
76 { 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
77 { 28, 0x0000 }, /* R28 - Left Output Volume */
78 { 29, 0x0000 }, /* R29 - Right Output Volume */
79 { 30, 0x0066 }, /* R30 - Line Outputs Volume */
80 { 31, 0x0022 }, /* R31 - Out3/4 Volume */
81 { 32, 0x0079 }, /* R32 - Left OPGA Volume */
82 { 33, 0x0079 }, /* R33 - Right OPGA Volume */
83 { 34, 0x0003 }, /* R34 - Speaker Volume */
84 { 35, 0x0003 }, /* R35 - ClassD1 */
85
86 { 37, 0x0100 }, /* R37 - ClassD3 */
87 { 38, 0x0079 }, /* R38 - ClassD4 */
88 { 39, 0x0000 }, /* R39 - Input Mixer1 */
89 { 40, 0x0000 }, /* R40 - Input Mixer2 */
90 { 41, 0x0000 }, /* R41 - Input Mixer3 */
91 { 42, 0x0000 }, /* R42 - Input Mixer4 */
92 { 43, 0x0000 }, /* R43 - Input Mixer5 */
93 { 44, 0x0000 }, /* R44 - Input Mixer6 */
94 { 45, 0x0000 }, /* R45 - Output Mixer1 */
95 { 46, 0x0000 }, /* R46 - Output Mixer2 */
96 { 47, 0x0000 }, /* R47 - Output Mixer3 */
97 { 48, 0x0000 }, /* R48 - Output Mixer4 */
98 { 49, 0x0000 }, /* R49 - Output Mixer5 */
99 { 50, 0x0000 }, /* R50 - Output Mixer6 */
100 { 51, 0x0180 }, /* R51 - Out3/4 Mixer */
101 { 52, 0x0000 }, /* R52 - Line Mixer1 */
102 { 53, 0x0000 }, /* R53 - Line Mixer2 */
103 { 54, 0x0000 }, /* R54 - Speaker Mixer */
104 { 55, 0x0000 }, /* R55 - Additional Control */
105 { 56, 0x0000 }, /* R56 - AntiPOP1 */
106 { 57, 0x0000 }, /* R57 - AntiPOP2 */
107 { 58, 0x0000 }, /* R58 - MICBIAS */
108
109 { 60, 0x0008 }, /* R60 - PLL1 */
110 { 61, 0x0031 }, /* R61 - PLL2 */
111 { 62, 0x0026 }, /* R62 - PLL3 */
112 };
113
114 #define wm8990_reset(c) snd_soc_write(c, WM8990_RESET, 0)
115
116 static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0);
117
118 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
119
120 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0);
121
122 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
123
124 static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0);
125
126 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
127
128 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
129
130 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
131
132 static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
133 struct snd_ctl_elem_value *ucontrol)
134 {
135 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
136 struct soc_mixer_control *mc =
137 (struct soc_mixer_control *)kcontrol->private_value;
138 int reg = mc->reg;
139 int ret;
140 u16 val;
141
142 ret = snd_soc_put_volsw(kcontrol, ucontrol);
143 if (ret < 0)
144 return ret;
145
146 /* now hit the volume update bits (always bit 8) */
147 val = snd_soc_read(codec, reg);
148 return snd_soc_write(codec, reg, val | 0x0100);
149 }
150
151 #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
152 tlv_array) \
153 SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
154 snd_soc_get_volsw, wm899x_outpga_put_volsw_vu, tlv_array)
155
156
157 static const char *wm8990_digital_sidetone[] =
158 {"None", "Left ADC", "Right ADC", "Reserved"};
159
160 static SOC_ENUM_SINGLE_DECL(wm8990_left_digital_sidetone_enum,
161 WM8990_DIGITAL_SIDE_TONE,
162 WM8990_ADC_TO_DACL_SHIFT,
163 wm8990_digital_sidetone);
164
165 static SOC_ENUM_SINGLE_DECL(wm8990_right_digital_sidetone_enum,
166 WM8990_DIGITAL_SIDE_TONE,
167 WM8990_ADC_TO_DACR_SHIFT,
168 wm8990_digital_sidetone);
169
170 static const char *wm8990_adcmode[] =
171 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
172
173 static SOC_ENUM_SINGLE_DECL(wm8990_right_adcmode_enum,
174 WM8990_ADC_CTRL,
175 WM8990_ADC_HPF_CUT_SHIFT,
176 wm8990_adcmode);
177
178 static const struct snd_kcontrol_new wm8990_snd_controls[] = {
179 /* INMIXL */
180 SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0),
181 SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0),
182 /* INMIXR */
183 SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0),
184 SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0),
185
186 /* LOMIX */
187 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
188 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv),
189 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
190 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv),
191 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
192 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv),
193 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
194 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv),
195 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
196 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
197 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
198 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
199
200 /* ROMIX */
201 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
202 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv),
203 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
204 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv),
205 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
206 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv),
207 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
208 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv),
209 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
210 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv),
211 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
212 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv),
213
214 /* LOUT */
215 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME,
216 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv),
217 SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0),
218
219 /* ROUT */
220 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME,
221 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv),
222 SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0),
223
224 /* LOPGA */
225 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME,
226 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv),
227 SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME,
228 WM8990_LOPGAZC_BIT, 1, 0),
229
230 /* ROPGA */
231 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME,
232 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv),
233 SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME,
234 WM8990_ROPGAZC_BIT, 1, 0),
235
236 SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
237 WM8990_LONMUTE_BIT, 1, 0),
238 SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
239 WM8990_LOPMUTE_BIT, 1, 0),
240 SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
241 WM8990_LOATTN_BIT, 1, 0),
242 SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
243 WM8990_RONMUTE_BIT, 1, 0),
244 SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
245 WM8990_ROPMUTE_BIT, 1, 0),
246 SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
247 WM8990_ROATTN_BIT, 1, 0),
248
249 SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME,
250 WM8990_OUT3MUTE_BIT, 1, 0),
251 SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME,
252 WM8990_OUT3ATTN_BIT, 1, 0),
253
254 SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME,
255 WM8990_OUT4MUTE_BIT, 1, 0),
256 SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME,
257 WM8990_OUT4ATTN_BIT, 1, 0),
258
259 SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1,
260 WM8990_CDMODE_BIT, 1, 0),
261
262 SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME,
263 WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0),
264 SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3,
265 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0),
266 SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3,
267 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0),
268 SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4,
269 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv),
270 SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4,
271 WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0),
272
273 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
274 WM8990_LEFT_DAC_DIGITAL_VOLUME,
275 WM8990_DACL_VOL_SHIFT,
276 WM8990_DACL_VOL_MASK,
277 0,
278 out_dac_tlv),
279
280 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
281 WM8990_RIGHT_DAC_DIGITAL_VOLUME,
282 WM8990_DACR_VOL_SHIFT,
283 WM8990_DACR_VOL_MASK,
284 0,
285 out_dac_tlv),
286
287 SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum),
288 SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum),
289
290 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
291 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0,
292 out_sidetone_tlv),
293 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
294 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0,
295 out_sidetone_tlv),
296
297 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL,
298 WM8990_ADC_HPF_ENA_BIT, 1, 0),
299
300 SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum),
301
302 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
303 WM8990_LEFT_ADC_DIGITAL_VOLUME,
304 WM8990_ADCL_VOL_SHIFT,
305 WM8990_ADCL_VOL_MASK,
306 0,
307 in_adc_tlv),
308
309 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
310 WM8990_RIGHT_ADC_DIGITAL_VOLUME,
311 WM8990_ADCR_VOL_SHIFT,
312 WM8990_ADCR_VOL_MASK,
313 0,
314 in_adc_tlv),
315
316 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
317 WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
318 WM8990_LIN12VOL_SHIFT,
319 WM8990_LIN12VOL_MASK,
320 0,
321 in_pga_tlv),
322
323 SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
324 WM8990_LI12ZC_BIT, 1, 0),
325
326 SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
327 WM8990_LI12MUTE_BIT, 1, 0),
328
329 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
330 WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
331 WM8990_LIN34VOL_SHIFT,
332 WM8990_LIN34VOL_MASK,
333 0,
334 in_pga_tlv),
335
336 SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
337 WM8990_LI34ZC_BIT, 1, 0),
338
339 SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
340 WM8990_LI34MUTE_BIT, 1, 0),
341
342 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
343 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
344 WM8990_RIN12VOL_SHIFT,
345 WM8990_RIN12VOL_MASK,
346 0,
347 in_pga_tlv),
348
349 SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
350 WM8990_RI12ZC_BIT, 1, 0),
351
352 SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
353 WM8990_RI12MUTE_BIT, 1, 0),
354
355 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
356 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
357 WM8990_RIN34VOL_SHIFT,
358 WM8990_RIN34VOL_MASK,
359 0,
360 in_pga_tlv),
361
362 SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
363 WM8990_RI34ZC_BIT, 1, 0),
364
365 SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
366 WM8990_RI34MUTE_BIT, 1, 0),
367
368 };
369
370 /*
371 * _DAPM_ Controls
372 */
373
374 static int outmixer_event(struct snd_soc_dapm_widget *w,
375 struct snd_kcontrol *kcontrol, int event)
376 {
377 u32 reg_shift = kcontrol->private_value & 0xfff;
378 int ret = 0;
379 u16 reg;
380
381 switch (reg_shift) {
382 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
383 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER1);
384 if (reg & WM8990_LDLO) {
385 printk(KERN_WARNING
386 "Cannot set as Output Mixer 1 LDLO Set\n");
387 ret = -1;
388 }
389 break;
390 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
391 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER2);
392 if (reg & WM8990_RDRO) {
393 printk(KERN_WARNING
394 "Cannot set as Output Mixer 2 RDRO Set\n");
395 ret = -1;
396 }
397 break;
398 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
399 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER);
400 if (reg & WM8990_LDSPK) {
401 printk(KERN_WARNING
402 "Cannot set as Speaker Mixer LDSPK Set\n");
403 ret = -1;
404 }
405 break;
406 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
407 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER);
408 if (reg & WM8990_RDSPK) {
409 printk(KERN_WARNING
410 "Cannot set as Speaker Mixer RDSPK Set\n");
411 ret = -1;
412 }
413 break;
414 }
415
416 return ret;
417 }
418
419 /* INMIX dB values */
420 static const unsigned int in_mix_tlv[] = {
421 TLV_DB_RANGE_HEAD(1),
422 0, 7, TLV_DB_SCALE_ITEM(-1200, 600, 0),
423 };
424
425 /* Left In PGA Connections */
426 static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = {
427 SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0),
428 SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0),
429 };
430
431 static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = {
432 SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0),
433 SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0),
434 };
435
436 /* Right In PGA Connections */
437 static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = {
438 SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0),
439 SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0),
440 };
441
442 static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = {
443 SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0),
444 SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0),
445 };
446
447 /* INMIXL */
448 static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = {
449 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3,
450 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv),
451 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT,
452 7, 0, in_mix_tlv),
453 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
454 1, 0),
455 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
456 1, 0),
457 };
458
459 /* INMIXR */
460 static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = {
461 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4,
462 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv),
463 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT,
464 7, 0, in_mix_tlv),
465 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
466 1, 0),
467 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
468 1, 0),
469 };
470
471 /* AINLMUX */
472 static const char *wm8990_ainlmux[] =
473 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
474
475 static SOC_ENUM_SINGLE_DECL(wm8990_ainlmux_enum,
476 WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT,
477 wm8990_ainlmux);
478
479 static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls =
480 SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum);
481
482 /* DIFFINL */
483
484 /* AINRMUX */
485 static const char *wm8990_ainrmux[] =
486 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
487
488 static SOC_ENUM_SINGLE_DECL(wm8990_ainrmux_enum,
489 WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT,
490 wm8990_ainrmux);
491
492 static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls =
493 SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum);
494
495 /* RXVOICE */
496 static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = {
497 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT,
498 WM8990_LR4BVOL_MASK, 0, in_mix_tlv),
499 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT,
500 WM8990_RL4BVOL_MASK, 0, in_mix_tlv),
501 };
502
503 /* LOMIX */
504 static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = {
505 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
506 WM8990_LRBLO_BIT, 1, 0),
507 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
508 WM8990_LLBLO_BIT, 1, 0),
509 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
510 WM8990_LRI3LO_BIT, 1, 0),
511 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
512 WM8990_LLI3LO_BIT, 1, 0),
513 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
514 WM8990_LR12LO_BIT, 1, 0),
515 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
516 WM8990_LL12LO_BIT, 1, 0),
517 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1,
518 WM8990_LDLO_BIT, 1, 0),
519 };
520
521 /* ROMIX */
522 static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = {
523 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
524 WM8990_RLBRO_BIT, 1, 0),
525 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
526 WM8990_RRBRO_BIT, 1, 0),
527 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
528 WM8990_RLI3RO_BIT, 1, 0),
529 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
530 WM8990_RRI3RO_BIT, 1, 0),
531 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
532 WM8990_RL12RO_BIT, 1, 0),
533 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
534 WM8990_RR12RO_BIT, 1, 0),
535 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2,
536 WM8990_RDRO_BIT, 1, 0),
537 };
538
539 /* LONMIX */
540 static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = {
541 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
542 WM8990_LLOPGALON_BIT, 1, 0),
543 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1,
544 WM8990_LROPGALON_BIT, 1, 0),
545 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1,
546 WM8990_LOPLON_BIT, 1, 0),
547 };
548
549 /* LOPMIX */
550 static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = {
551 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1,
552 WM8990_LR12LOP_BIT, 1, 0),
553 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1,
554 WM8990_LL12LOP_BIT, 1, 0),
555 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
556 WM8990_LLOPGALOP_BIT, 1, 0),
557 };
558
559 /* RONMIX */
560 static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = {
561 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
562 WM8990_RROPGARON_BIT, 1, 0),
563 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2,
564 WM8990_RLOPGARON_BIT, 1, 0),
565 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2,
566 WM8990_ROPRON_BIT, 1, 0),
567 };
568
569 /* ROPMIX */
570 static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = {
571 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2,
572 WM8990_RL12ROP_BIT, 1, 0),
573 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2,
574 WM8990_RR12ROP_BIT, 1, 0),
575 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
576 WM8990_RROPGAROP_BIT, 1, 0),
577 };
578
579 /* OUT3MIX */
580 static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = {
581 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
582 WM8990_LI4O3_BIT, 1, 0),
583 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER,
584 WM8990_LPGAO3_BIT, 1, 0),
585 };
586
587 /* OUT4MIX */
588 static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = {
589 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER,
590 WM8990_RPGAO4_BIT, 1, 0),
591 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
592 WM8990_RI4O4_BIT, 1, 0),
593 };
594
595 /* SPKMIX */
596 static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = {
597 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
598 WM8990_LI2SPK_BIT, 1, 0),
599 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER,
600 WM8990_LB2SPK_BIT, 1, 0),
601 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER,
602 WM8990_LOPGASPK_BIT, 1, 0),
603 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER,
604 WM8990_LDSPK_BIT, 1, 0),
605 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER,
606 WM8990_RDSPK_BIT, 1, 0),
607 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER,
608 WM8990_ROPGASPK_BIT, 1, 0),
609 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER,
610 WM8990_RL12ROP_BIT, 1, 0),
611 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
612 WM8990_RI2SPK_BIT, 1, 0),
613 };
614
615 static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
616 /* Input Side */
617 /* Input Lines */
618 SND_SOC_DAPM_INPUT("LIN1"),
619 SND_SOC_DAPM_INPUT("LIN2"),
620 SND_SOC_DAPM_INPUT("LIN3"),
621 SND_SOC_DAPM_INPUT("LIN4/RXN"),
622 SND_SOC_DAPM_INPUT("RIN3"),
623 SND_SOC_DAPM_INPUT("RIN4/RXP"),
624 SND_SOC_DAPM_INPUT("RIN1"),
625 SND_SOC_DAPM_INPUT("RIN2"),
626 SND_SOC_DAPM_INPUT("Internal ADC Source"),
627
628 SND_SOC_DAPM_SUPPLY("INL", WM8990_POWER_MANAGEMENT_2, WM8990_AINL_ENA_BIT, 0,
629 NULL, 0),
630 SND_SOC_DAPM_SUPPLY("INR", WM8990_POWER_MANAGEMENT_2, WM8990_AINR_ENA_BIT, 0,
631 NULL, 0),
632
633 /* DACs */
634 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2,
635 WM8990_ADCL_ENA_BIT, 0),
636 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2,
637 WM8990_ADCR_ENA_BIT, 0),
638
639 /* Input PGAs */
640 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT,
641 0, &wm8990_dapm_lin12_pga_controls[0],
642 ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)),
643 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT,
644 0, &wm8990_dapm_lin34_pga_controls[0],
645 ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)),
646 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT,
647 0, &wm8990_dapm_rin12_pga_controls[0],
648 ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)),
649 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT,
650 0, &wm8990_dapm_rin34_pga_controls[0],
651 ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)),
652
653 /* INMIXL */
654 SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
655 &wm8990_dapm_inmixl_controls[0],
656 ARRAY_SIZE(wm8990_dapm_inmixl_controls)),
657
658 /* AINLMUX */
659 SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainlmux_controls),
660
661 /* INMIXR */
662 SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
663 &wm8990_dapm_inmixr_controls[0],
664 ARRAY_SIZE(wm8990_dapm_inmixr_controls)),
665
666 /* AINRMUX */
667 SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainrmux_controls),
668
669 /* Output Side */
670 /* DACs */
671 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3,
672 WM8990_DACL_ENA_BIT, 0),
673 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3,
674 WM8990_DACR_ENA_BIT, 0),
675
676 /* LOMIX */
677 SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT,
678 0, &wm8990_dapm_lomix_controls[0],
679 ARRAY_SIZE(wm8990_dapm_lomix_controls),
680 outmixer_event, SND_SOC_DAPM_PRE_REG),
681
682 /* LONMIX */
683 SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0,
684 &wm8990_dapm_lonmix_controls[0],
685 ARRAY_SIZE(wm8990_dapm_lonmix_controls)),
686
687 /* LOPMIX */
688 SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0,
689 &wm8990_dapm_lopmix_controls[0],
690 ARRAY_SIZE(wm8990_dapm_lopmix_controls)),
691
692 /* OUT3MIX */
693 SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0,
694 &wm8990_dapm_out3mix_controls[0],
695 ARRAY_SIZE(wm8990_dapm_out3mix_controls)),
696
697 /* SPKMIX */
698 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0,
699 &wm8990_dapm_spkmix_controls[0],
700 ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event,
701 SND_SOC_DAPM_PRE_REG),
702
703 /* OUT4MIX */
704 SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0,
705 &wm8990_dapm_out4mix_controls[0],
706 ARRAY_SIZE(wm8990_dapm_out4mix_controls)),
707
708 /* ROPMIX */
709 SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0,
710 &wm8990_dapm_ropmix_controls[0],
711 ARRAY_SIZE(wm8990_dapm_ropmix_controls)),
712
713 /* RONMIX */
714 SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0,
715 &wm8990_dapm_ronmix_controls[0],
716 ARRAY_SIZE(wm8990_dapm_ronmix_controls)),
717
718 /* ROMIX */
719 SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT,
720 0, &wm8990_dapm_romix_controls[0],
721 ARRAY_SIZE(wm8990_dapm_romix_controls),
722 outmixer_event, SND_SOC_DAPM_PRE_REG),
723
724 /* LOUT PGA */
725 SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0,
726 NULL, 0),
727
728 /* ROUT PGA */
729 SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0,
730 NULL, 0),
731
732 /* LOPGA */
733 SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0,
734 NULL, 0),
735
736 /* ROPGA */
737 SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0,
738 NULL, 0),
739
740 /* MICBIAS */
741 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8990_POWER_MANAGEMENT_1,
742 WM8990_MICBIAS_ENA_BIT, 0, NULL, 0),
743
744 SND_SOC_DAPM_OUTPUT("LON"),
745 SND_SOC_DAPM_OUTPUT("LOP"),
746 SND_SOC_DAPM_OUTPUT("OUT3"),
747 SND_SOC_DAPM_OUTPUT("LOUT"),
748 SND_SOC_DAPM_OUTPUT("SPKN"),
749 SND_SOC_DAPM_OUTPUT("SPKP"),
750 SND_SOC_DAPM_OUTPUT("ROUT"),
751 SND_SOC_DAPM_OUTPUT("OUT4"),
752 SND_SOC_DAPM_OUTPUT("ROP"),
753 SND_SOC_DAPM_OUTPUT("RON"),
754
755 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
756 };
757
758 static const struct snd_soc_dapm_route wm8990_dapm_routes[] = {
759 /* Make DACs turn on when playing even if not mixed into any outputs */
760 {"Internal DAC Sink", NULL, "Left DAC"},
761 {"Internal DAC Sink", NULL, "Right DAC"},
762
763 /* Make ADCs turn on when recording even if not mixed from any inputs */
764 {"Left ADC", NULL, "Internal ADC Source"},
765 {"Right ADC", NULL, "Internal ADC Source"},
766
767 {"AINLMUX", NULL, "INL"},
768 {"INMIXL", NULL, "INL"},
769 {"AINRMUX", NULL, "INR"},
770 {"INMIXR", NULL, "INR"},
771
772 /* Input Side */
773 /* LIN12 PGA */
774 {"LIN12 PGA", "LIN1 Switch", "LIN1"},
775 {"LIN12 PGA", "LIN2 Switch", "LIN2"},
776 /* LIN34 PGA */
777 {"LIN34 PGA", "LIN3 Switch", "LIN3"},
778 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
779 /* INMIXL */
780 {"INMIXL", "Record Left Volume", "LOMIX"},
781 {"INMIXL", "LIN2 Volume", "LIN2"},
782 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
783 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
784 /* AINLMUX */
785 {"AINLMUX", "INMIXL Mix", "INMIXL"},
786 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
787 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
788 {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"},
789 {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"},
790 /* ADC */
791 {"Left ADC", NULL, "AINLMUX"},
792
793 /* RIN12 PGA */
794 {"RIN12 PGA", "RIN1 Switch", "RIN1"},
795 {"RIN12 PGA", "RIN2 Switch", "RIN2"},
796 /* RIN34 PGA */
797 {"RIN34 PGA", "RIN3 Switch", "RIN3"},
798 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
799 /* INMIXL */
800 {"INMIXR", "Record Right Volume", "ROMIX"},
801 {"INMIXR", "RIN2 Volume", "RIN2"},
802 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
803 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
804 /* AINRMUX */
805 {"AINRMUX", "INMIXR Mix", "INMIXR"},
806 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
807 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
808 {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"},
809 {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"},
810 /* ADC */
811 {"Right ADC", NULL, "AINRMUX"},
812
813 /* LOMIX */
814 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
815 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
816 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
817 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
818 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
819 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
820 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
821
822 /* ROMIX */
823 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
824 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
825 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
826 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
827 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
828 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
829 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
830
831 /* SPKMIX */
832 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
833 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
834 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
835 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
836 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
837 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
838 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
839 {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"},
840
841 /* LONMIX */
842 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
843 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
844 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
845
846 /* LOPMIX */
847 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
848 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
849 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
850
851 /* OUT3MIX */
852 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
853 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
854
855 /* OUT4MIX */
856 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
857 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
858
859 /* RONMIX */
860 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
861 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
862 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
863
864 /* ROPMIX */
865 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
866 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
867 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
868
869 /* Out Mixer PGAs */
870 {"LOPGA", NULL, "LOMIX"},
871 {"ROPGA", NULL, "ROMIX"},
872
873 {"LOUT PGA", NULL, "LOMIX"},
874 {"ROUT PGA", NULL, "ROMIX"},
875
876 /* Output Pins */
877 {"LON", NULL, "LONMIX"},
878 {"LOP", NULL, "LOPMIX"},
879 {"OUT3", NULL, "OUT3MIX"},
880 {"LOUT", NULL, "LOUT PGA"},
881 {"SPKN", NULL, "SPKMIX"},
882 {"ROUT", NULL, "ROUT PGA"},
883 {"OUT4", NULL, "OUT4MIX"},
884 {"ROP", NULL, "ROPMIX"},
885 {"RON", NULL, "RONMIX"},
886 };
887
888 /* PLL divisors */
889 struct _pll_div {
890 u32 div2;
891 u32 n;
892 u32 k;
893 };
894
895 /* The size in bits of the pll divide multiplied by 10
896 * to allow rounding later */
897 #define FIXED_PLL_SIZE ((1 << 16) * 10)
898
899 static void pll_factors(struct _pll_div *pll_div, unsigned int target,
900 unsigned int source)
901 {
902 u64 Kpart;
903 unsigned int K, Ndiv, Nmod;
904
905
906 Ndiv = target / source;
907 if (Ndiv < 6) {
908 source >>= 1;
909 pll_div->div2 = 1;
910 Ndiv = target / source;
911 } else
912 pll_div->div2 = 0;
913
914 if ((Ndiv < 6) || (Ndiv > 12))
915 printk(KERN_WARNING
916 "WM8990 N value outwith recommended range! N = %u\n", Ndiv);
917
918 pll_div->n = Ndiv;
919 Nmod = target % source;
920 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
921
922 do_div(Kpart, source);
923
924 K = Kpart & 0xFFFFFFFF;
925
926 /* Check if we need to round */
927 if ((K % 10) >= 5)
928 K += 5;
929
930 /* Move down to proper range now rounding is done */
931 K /= 10;
932
933 pll_div->k = K;
934 }
935
936 static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
937 int source, unsigned int freq_in, unsigned int freq_out)
938 {
939 struct snd_soc_codec *codec = codec_dai->codec;
940 struct _pll_div pll_div;
941
942 if (freq_in && freq_out) {
943 pll_factors(&pll_div, freq_out * 4, freq_in);
944
945 /* Turn on PLL */
946 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
947 WM8990_PLL_ENA, WM8990_PLL_ENA);
948
949 /* sysclk comes from PLL */
950 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
951 WM8990_SYSCLK_SRC, WM8990_SYSCLK_SRC);
952
953 /* set up N , fractional mode and pre-divisor if necessary */
954 snd_soc_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM |
955 (pll_div.div2?WM8990_PRESCALE:0));
956 snd_soc_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8));
957 snd_soc_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
958 } else {
959 /* Turn off PLL */
960 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
961 WM8990_PLL_ENA, 0);
962 }
963 return 0;
964 }
965
966 /*
967 * Clock after PLL and dividers
968 */
969 static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai,
970 int clk_id, unsigned int freq, int dir)
971 {
972 struct snd_soc_codec *codec = codec_dai->codec;
973 struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec);
974
975 wm8990->sysclk = freq;
976 return 0;
977 }
978
979 /*
980 * Set's ADC and Voice DAC format.
981 */
982 static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
983 unsigned int fmt)
984 {
985 struct snd_soc_codec *codec = codec_dai->codec;
986 u16 audio1, audio3;
987
988 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
989 audio3 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_3);
990
991 /* set master/slave audio interface */
992 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
993 case SND_SOC_DAIFMT_CBS_CFS:
994 audio3 &= ~WM8990_AIF_MSTR1;
995 break;
996 case SND_SOC_DAIFMT_CBM_CFM:
997 audio3 |= WM8990_AIF_MSTR1;
998 break;
999 default:
1000 return -EINVAL;
1001 }
1002
1003 audio1 &= ~WM8990_AIF_FMT_MASK;
1004
1005 /* interface format */
1006 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1007 case SND_SOC_DAIFMT_I2S:
1008 audio1 |= WM8990_AIF_TMF_I2S;
1009 audio1 &= ~WM8990_AIF_LRCLK_INV;
1010 break;
1011 case SND_SOC_DAIFMT_RIGHT_J:
1012 audio1 |= WM8990_AIF_TMF_RIGHTJ;
1013 audio1 &= ~WM8990_AIF_LRCLK_INV;
1014 break;
1015 case SND_SOC_DAIFMT_LEFT_J:
1016 audio1 |= WM8990_AIF_TMF_LEFTJ;
1017 audio1 &= ~WM8990_AIF_LRCLK_INV;
1018 break;
1019 case SND_SOC_DAIFMT_DSP_A:
1020 audio1 |= WM8990_AIF_TMF_DSP;
1021 audio1 &= ~WM8990_AIF_LRCLK_INV;
1022 break;
1023 case SND_SOC_DAIFMT_DSP_B:
1024 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV;
1025 break;
1026 default:
1027 return -EINVAL;
1028 }
1029
1030 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1031 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_3, audio3);
1032 return 0;
1033 }
1034
1035 static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1036 int div_id, int div)
1037 {
1038 struct snd_soc_codec *codec = codec_dai->codec;
1039
1040 switch (div_id) {
1041 case WM8990_MCLK_DIV:
1042 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
1043 WM8990_MCLK_DIV_MASK, div);
1044 break;
1045 case WM8990_DACCLK_DIV:
1046 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
1047 WM8990_DAC_CLKDIV_MASK, div);
1048 break;
1049 case WM8990_ADCCLK_DIV:
1050 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
1051 WM8990_ADC_CLKDIV_MASK, div);
1052 break;
1053 case WM8990_BCLK_DIV:
1054 snd_soc_update_bits(codec, WM8990_CLOCKING_1,
1055 WM8990_BCLK_DIV_MASK, div);
1056 break;
1057 default:
1058 return -EINVAL;
1059 }
1060
1061 return 0;
1062 }
1063
1064 /*
1065 * Set PCM DAI bit size and sample rate.
1066 */
1067 static int wm8990_hw_params(struct snd_pcm_substream *substream,
1068 struct snd_pcm_hw_params *params,
1069 struct snd_soc_dai *dai)
1070 {
1071 struct snd_soc_codec *codec = dai->codec;
1072 u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
1073
1074 audio1 &= ~WM8990_AIF_WL_MASK;
1075 /* bit size */
1076 switch (params_width(params)) {
1077 case 16:
1078 break;
1079 case 20:
1080 audio1 |= WM8990_AIF_WL_20BITS;
1081 break;
1082 case 24:
1083 audio1 |= WM8990_AIF_WL_24BITS;
1084 break;
1085 case 32:
1086 audio1 |= WM8990_AIF_WL_32BITS;
1087 break;
1088 }
1089
1090 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1091 return 0;
1092 }
1093
1094 static int wm8990_mute(struct snd_soc_dai *dai, int mute)
1095 {
1096 struct snd_soc_codec *codec = dai->codec;
1097 u16 val;
1098
1099 val = snd_soc_read(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
1100
1101 if (mute)
1102 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1103 else
1104 snd_soc_write(codec, WM8990_DAC_CTRL, val);
1105
1106 return 0;
1107 }
1108
1109 static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1110 enum snd_soc_bias_level level)
1111 {
1112 struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec);
1113 int ret;
1114
1115 switch (level) {
1116 case SND_SOC_BIAS_ON:
1117 break;
1118
1119 case SND_SOC_BIAS_PREPARE:
1120 /* VMID=2*50k */
1121 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_1,
1122 WM8990_VMID_MODE_MASK, 0x2);
1123 break;
1124
1125 case SND_SOC_BIAS_STANDBY:
1126 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1127 ret = regcache_sync(wm8990->regmap);
1128 if (ret < 0) {
1129 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
1130 return ret;
1131 }
1132
1133 /* Enable all output discharge bits */
1134 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1135 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1136 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1137 WM8990_DIS_ROUT);
1138
1139 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1140 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1141 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1142 WM8990_VMIDTOG);
1143
1144 /* Delay to allow output caps to discharge */
1145 msleep(300);
1146
1147 /* Disable VMIDTOG */
1148 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1149 WM8990_BUFDCOPEN | WM8990_POBCTRL);
1150
1151 /* disable all output discharge bits */
1152 snd_soc_write(codec, WM8990_ANTIPOP1, 0);
1153
1154 /* Enable outputs */
1155 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00);
1156
1157 msleep(50);
1158
1159 /* Enable VMID at 2x50k */
1160 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02);
1161
1162 msleep(100);
1163
1164 /* Enable VREF */
1165 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1166
1167 msleep(600);
1168
1169 /* Enable BUFIOEN */
1170 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1171 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1172 WM8990_BUFIOEN);
1173
1174 /* Disable outputs */
1175 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3);
1176
1177 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1178 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN);
1179
1180 /* Enable workaround for ADC clocking issue. */
1181 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0x2);
1182 snd_soc_write(codec, WM8990_EXT_CTL1, 0xa003);
1183 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0);
1184 }
1185
1186 /* VMID=2*250k */
1187 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_1,
1188 WM8990_VMID_MODE_MASK, 0x4);
1189 break;
1190
1191 case SND_SOC_BIAS_OFF:
1192 /* Enable POBCTRL and SOFT_ST */
1193 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1194 WM8990_POBCTRL | WM8990_BUFIOEN);
1195
1196 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1197 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1198 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1199 WM8990_BUFIOEN);
1200
1201 /* mute DAC */
1202 snd_soc_update_bits(codec, WM8990_DAC_CTRL,
1203 WM8990_DAC_MUTE, WM8990_DAC_MUTE);
1204
1205 /* Enable any disabled outputs */
1206 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1207
1208 /* Disable VMID */
1209 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01);
1210
1211 msleep(300);
1212
1213 /* Enable all output discharge bits */
1214 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1215 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1216 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1217 WM8990_DIS_ROUT);
1218
1219 /* Disable VREF */
1220 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0);
1221
1222 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1223 snd_soc_write(codec, WM8990_ANTIPOP2, 0x0);
1224
1225 regcache_mark_dirty(wm8990->regmap);
1226 break;
1227 }
1228
1229 codec->dapm.bias_level = level;
1230 return 0;
1231 }
1232
1233 #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1234 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
1235 SNDRV_PCM_RATE_48000)
1236
1237 #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1238 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1239
1240 /*
1241 * The WM8990 supports 2 different and mutually exclusive DAI
1242 * configurations.
1243 *
1244 * 1. ADC/DAC on Primary Interface
1245 * 2. ADC on Primary Interface/DAC on secondary
1246 */
1247 static const struct snd_soc_dai_ops wm8990_dai_ops = {
1248 .hw_params = wm8990_hw_params,
1249 .digital_mute = wm8990_mute,
1250 .set_fmt = wm8990_set_dai_fmt,
1251 .set_clkdiv = wm8990_set_dai_clkdiv,
1252 .set_pll = wm8990_set_dai_pll,
1253 .set_sysclk = wm8990_set_dai_sysclk,
1254 };
1255
1256 static struct snd_soc_dai_driver wm8990_dai = {
1257 /* ADC/DAC on primary */
1258 .name = "wm8990-hifi",
1259 .playback = {
1260 .stream_name = "Playback",
1261 .channels_min = 1,
1262 .channels_max = 2,
1263 .rates = WM8990_RATES,
1264 .formats = WM8990_FORMATS,},
1265 .capture = {
1266 .stream_name = "Capture",
1267 .channels_min = 1,
1268 .channels_max = 2,
1269 .rates = WM8990_RATES,
1270 .formats = WM8990_FORMATS,},
1271 .ops = &wm8990_dai_ops,
1272 };
1273
1274 static int wm8990_suspend(struct snd_soc_codec *codec)
1275 {
1276 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1277 return 0;
1278 }
1279
1280 static int wm8990_resume(struct snd_soc_codec *codec)
1281 {
1282 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1283 return 0;
1284 }
1285
1286 /*
1287 * initialise the WM8990 driver
1288 * register the mixer and dsp interfaces with the kernel
1289 */
1290 static int wm8990_probe(struct snd_soc_codec *codec)
1291 {
1292 wm8990_reset(codec);
1293
1294 /* charge output caps */
1295 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1296
1297 snd_soc_update_bits(codec, WM8990_AUDIO_INTERFACE_4,
1298 WM8990_ALRCGPIO1, WM8990_ALRCGPIO1);
1299
1300 snd_soc_update_bits(codec, WM8990_GPIO1_GPIO2,
1301 WM8990_GPIO1_SEL_MASK, 1);
1302
1303 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
1304 WM8990_OPCLK_ENA, WM8990_OPCLK_ENA);
1305
1306 snd_soc_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1307 snd_soc_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1308
1309 return 0;
1310 }
1311
1312 /* power down chip */
1313 static int wm8990_remove(struct snd_soc_codec *codec)
1314 {
1315 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1316 return 0;
1317 }
1318
1319 static struct snd_soc_codec_driver soc_codec_dev_wm8990 = {
1320 .probe = wm8990_probe,
1321 .remove = wm8990_remove,
1322 .suspend = wm8990_suspend,
1323 .resume = wm8990_resume,
1324 .set_bias_level = wm8990_set_bias_level,
1325 .controls = wm8990_snd_controls,
1326 .num_controls = ARRAY_SIZE(wm8990_snd_controls),
1327 .dapm_widgets = wm8990_dapm_widgets,
1328 .num_dapm_widgets = ARRAY_SIZE(wm8990_dapm_widgets),
1329 .dapm_routes = wm8990_dapm_routes,
1330 .num_dapm_routes = ARRAY_SIZE(wm8990_dapm_routes),
1331 };
1332
1333 static const struct regmap_config wm8990_regmap = {
1334 .reg_bits = 8,
1335 .val_bits = 16,
1336
1337 .max_register = WM8990_PLL3,
1338 .volatile_reg = wm8990_volatile_register,
1339 .reg_defaults = wm8990_reg_defaults,
1340 .num_reg_defaults = ARRAY_SIZE(wm8990_reg_defaults),
1341 .cache_type = REGCACHE_RBTREE,
1342 };
1343
1344 static int wm8990_i2c_probe(struct i2c_client *i2c,
1345 const struct i2c_device_id *id)
1346 {
1347 struct wm8990_priv *wm8990;
1348 int ret;
1349
1350 wm8990 = devm_kzalloc(&i2c->dev, sizeof(struct wm8990_priv),
1351 GFP_KERNEL);
1352 if (wm8990 == NULL)
1353 return -ENOMEM;
1354
1355 i2c_set_clientdata(i2c, wm8990);
1356
1357 ret = snd_soc_register_codec(&i2c->dev,
1358 &soc_codec_dev_wm8990, &wm8990_dai, 1);
1359
1360 return ret;
1361 }
1362
1363 static int wm8990_i2c_remove(struct i2c_client *client)
1364 {
1365 snd_soc_unregister_codec(&client->dev);
1366
1367 return 0;
1368 }
1369
1370 static const struct i2c_device_id wm8990_i2c_id[] = {
1371 { "wm8990", 0 },
1372 { }
1373 };
1374 MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id);
1375
1376 static struct i2c_driver wm8990_i2c_driver = {
1377 .driver = {
1378 .name = "wm8990",
1379 .owner = THIS_MODULE,
1380 },
1381 .probe = wm8990_i2c_probe,
1382 .remove = wm8990_i2c_remove,
1383 .id_table = wm8990_i2c_id,
1384 };
1385
1386 module_i2c_driver(wm8990_i2c_driver);
1387
1388 MODULE_DESCRIPTION("ASoC WM8990 driver");
1389 MODULE_AUTHOR("Liam Girdwood");
1390 MODULE_LICENSE("GPL");
Linux with added FPC-III support