arch/arm/boot/dts/axm55xx.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * arch/arm/boot/dts/axm55xx.dtsi
   4  *
   5  * Copyright (C) 2013 LSI
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/lsi,axm5516-clks.h>
  10
  11 / {
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14         interrupt-parent = <&gic>;
  15
  16         aliases {
  17                 serial0   = &serial0;
  18                 serial1   = &serial1;
  19                 serial2   = &serial2;
  20                 serial3   = &serial3;
  21                 timer     = &timer0;
  22         };
  23
  24         clocks {
  25                 compatible = "simple-bus";
  26                 #address-cells = <2>;
  27                 #size-cells = <2>;
  28                 ranges;
  29
  30                 clk_ref0: clk_ref0 {
  31                         compatible = "fixed-clock";
  32                         #clock-cells = <0>;
  33                         clock-frequency = <125000000>;
  34                 };
  35
  36                 clk_ref1: clk_ref1 {
  37                         compatible = "fixed-clock";
  38                         #clock-cells = <0>;
  39                         clock-frequency = <125000000>;
  40                 };
  41
  42                 clk_ref2: clk_ref2 {
  43                         compatible = "fixed-clock";
  44                         #clock-cells = <0>;
  45                         clock-frequency = <125000000>;
  46                 };
  47
  48                 clks: clock-controller@2010020000 {
  49                         compatible = "lsi,axm5516-clks";
  50                         #clock-cells = <1>;
  51                         reg = <0x20 0x10020000 0 0x20000>;
  52                 };
  53         };
  54
  55         gic: interrupt-controller@2001001000 {
  56                 compatible = "arm,cortex-a15-gic";
  57                 #interrupt-cells = <3>;
  58                 #address-cells = <0>;
  59                 interrupt-controller;
  60                 reg = <0x20 0x01001000 0 0x1000>,
  61                       <0x20 0x01002000 0 0x2000>,
  62                       <0x20 0x01004000 0 0x2000>,
  63                       <0x20 0x01006000 0 0x2000>;
  64                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
  65                                 IRQ_TYPE_LEVEL_HIGH)>;
  66         };
  67
  68         timer {
  69                 compatible = "arm,armv7-timer";
  70                 interrupts =
  71                         <GIC_PPI 13
  72                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  73                         <GIC_PPI 14
  74                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  75                         <GIC_PPI 11
  76                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  77                         <GIC_PPI 10
  78                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  79         };
  80
  81
  82         pmu {
  83                 compatible = "arm,cortex-a15-pmu";
  84                 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
  85         };
  86
  87         soc {
  88                 compatible = "simple-bus";
  89                 device_type = "soc";
  90                 #address-cells = <2>;
  91                 #size-cells = <2>;
  92                 interrupt-parent = <&gic>;
  93                 ranges;
  94
  95                 syscon: syscon@2010030000 {
  96                         compatible = "lsi,axxia-syscon", "syscon";
  97                         reg = <0x20 0x10030000 0 0x2000>;
  98                 };
  99
 100                 reset: reset@2010031000 {
 101                         compatible = "lsi,axm55xx-reset";
 102                         syscon = <&syscon>;
 103                 };
 104
 105                 amba {
 106                         compatible = "simple-bus";
 107                         #address-cells = <2>;
 108                         #size-cells = <2>;
 109                         ranges;
 110
 111                         serial0: uart@2010080000 {
 112                                 compatible = "arm,pl011", "arm,primecell";
 113                                 reg = <0x20 0x10080000 0 0x1000>;
 114                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 115                                 clocks = <&clks AXXIA_CLK_PER>;
 116                                 clock-names = "apb_pclk";
 117                                 status = "disabled";
 118                         };
 119
 120                         serial1: uart@2010081000 {
 121                                 compatible = "arm,pl011", "arm,primecell";
 122                                 reg = <0x20 0x10081000 0 0x1000>;
 123                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 124                                 clocks = <&clks AXXIA_CLK_PER>;
 125                                 clock-names = "apb_pclk";
 126                                 status = "disabled";
 127                         };
 128
 129                         serial2: uart@2010082000 {
 130                                 compatible = "arm,pl011", "arm,primecell";
 131                                 reg = <0x20 0x10082000 0 0x1000>;
 132                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 133                                 clocks = <&clks AXXIA_CLK_PER>;
 134                                 clock-names = "apb_pclk";
 135                                 status = "disabled";
 136                         };
 137
 138                         serial3: uart@2010083000 {
 139                                 compatible = "arm,pl011", "arm,primecell";
 140                                 reg = <0x20 0x10083000 0 0x1000>;
 141                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 142                                 clocks = <&clks AXXIA_CLK_PER>;
 143                                 clock-names = "apb_pclk";
 144                                 status = "disabled";
 145                         };
 146
 147                         timer0: timer@2010091000 {
 148                                 compatible = "arm,sp804", "arm,primecell";
 149                                 reg = <0x20 0x10091000 0 0x1000>;
 150                                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 151                                              <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 152                                              <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 153                                              <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 154                                              <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 155                                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 156                                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 157                                              <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 158                                              <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 159                                 clocks = <&clks AXXIA_CLK_PER>;
 160                                 clock-names = "apb_pclk";
 161                                 status = "okay";
 162                         };
 163
 164                         gpio0: gpio@2010092000 {
 165                                 #gpio-cells = <2>;
 166                                 compatible = "arm,pl061", "arm,primecell";
 167                                 gpio-controller;
 168                                 reg = <0x20 0x10092000 0x00 0x1000>;
 169                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 170                                              <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 171                                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 172                                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 173                                              <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 174                                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 175                                              <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 176                                              <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 177                                 clocks = <&clks AXXIA_CLK_PER>;
 178                                 clock-names = "apb_pclk";
 179                                 status = "disabled";
 180                         };
 181
 182                         gpio1: gpio@2010093000 {
 183                                 #gpio-cells = <2>;
 184                                 compatible = "arm,pl061", "arm,primecell";
 185                                 gpio-controller;
 186                                 reg = <0x20 0x10093000 0x00 0x1000>;
 187                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 188                                 clocks = <&clks AXXIA_CLK_PER>;
 189                                 clock-names = "apb_pclk";
 190                                 status = "disabled";
 191                         };
 192                 };
 193         };
 194 };
 195
 196 /*
 197   Local Variables:
 198   mode: C
 199   End:
 200 */