| blob | 55d4dbf6f83a9a34826c675048265010083d038d |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SAMSUNG EXYNOS5420 SoC device tree source
4 *
5 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * SAMSUNG EXYNOS5420 SoC device nodes are listed in this file.
9 * EXYNOS5420 based board files can include this file and provide
10 * values for board specfic bindings.
11 */
13 #include "exynos54xx.dtsi"
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 / {
19 compatible = "samsung,exynos5420", "samsung,exynos5";
21 aliases {
22 mshc0 = &mmc_0;
23 mshc1 = &mmc_1;
24 mshc2 = &mmc_2;
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 pinctrl4 = &pinctrl_4;
30 i2c8 = &hsi2c_8;
31 i2c9 = &hsi2c_9;
32 i2c10 = &hsi2c_10;
33 gsc0 = &gsc_0;
34 gsc1 = &gsc_1;
35 spi0 = &spi_0;
36 spi1 = &spi_1;
37 spi2 = &spi_2;
38 };
40 /*
41 * The 'cpus' node is not present here but instead it is provided
42 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
43 */
45 cluster_a15_opp_table: opp_table0 {
46 compatible = "operating-points-v2";
47 opp-shared;
49 opp-1800000000 {
50 opp-hz = /bits/ 64 <1800000000>;
51 opp-microvolt = <1250000>;
52 clock-latency-ns = <140000>;
53 };
54 opp-1700000000 {
55 opp-hz = /bits/ 64 <1700000000>;
56 opp-microvolt = <1212500>;
57 clock-latency-ns = <140000>;
58 };
59 opp-1600000000 {
60 opp-hz = /bits/ 64 <1600000000>;
61 opp-microvolt = <1175000>;
62 clock-latency-ns = <140000>;
63 };
64 opp-1500000000 {
65 opp-hz = /bits/ 64 <1500000000>;
66 opp-microvolt = <1137500>;
67 clock-latency-ns = <140000>;
68 };
69 opp-1400000000 {
70 opp-hz = /bits/ 64 <1400000000>;
71 opp-microvolt = <1112500>;
72 clock-latency-ns = <140000>;
73 };
74 opp-1300000000 {
75 opp-hz = /bits/ 64 <1300000000>;
76 opp-microvolt = <1062500>;
77 clock-latency-ns = <140000>;
78 };
79 opp-1200000000 {
80 opp-hz = /bits/ 64 <1200000000>;
81 opp-microvolt = <1037500>;
82 clock-latency-ns = <140000>;
83 };
84 opp-1100000000 {
85 opp-hz = /bits/ 64 <1100000000>;
86 opp-microvolt = <1012500>;
87 clock-latency-ns = <140000>;
88 };
89 opp-1000000000 {
90 opp-hz = /bits/ 64 <1000000000>;
91 opp-microvolt = < 987500>;
92 clock-latency-ns = <140000>;
93 };
94 opp-900000000 {
95 opp-hz = /bits/ 64 <900000000>;
96 opp-microvolt = < 962500>;
97 clock-latency-ns = <140000>;
98 };
99 opp-800000000 {
100 opp-hz = /bits/ 64 <800000000>;
101 opp-microvolt = < 937500>;
102 clock-latency-ns = <140000>;
103 };
104 opp-700000000 {
105 opp-hz = /bits/ 64 <700000000>;
106 opp-microvolt = < 912500>;
107 clock-latency-ns = <140000>;
108 };
109 };
111 cluster_a7_opp_table: opp_table1 {
112 compatible = "operating-points-v2";
113 opp-shared;
115 opp-1300000000 {
116 opp-hz = /bits/ 64 <1300000000>;
117 opp-microvolt = <1275000>;
118 clock-latency-ns = <140000>;
119 };
120 opp-1200000000 {
121 opp-hz = /bits/ 64 <1200000000>;
122 opp-microvolt = <1212500>;
123 clock-latency-ns = <140000>;
124 };
125 opp-1100000000 {
126 opp-hz = /bits/ 64 <1100000000>;
127 opp-microvolt = <1162500>;
128 clock-latency-ns = <140000>;
129 };
130 opp-1000000000 {
131 opp-hz = /bits/ 64 <1000000000>;
132 opp-microvolt = <1112500>;
133 clock-latency-ns = <140000>;
134 };
135 opp-900000000 {
136 opp-hz = /bits/ 64 <900000000>;
137 opp-microvolt = <1062500>;
138 clock-latency-ns = <140000>;
139 };
140 opp-800000000 {
141 opp-hz = /bits/ 64 <800000000>;
142 opp-microvolt = <1025000>;
143 clock-latency-ns = <140000>;
144 };
145 opp-700000000 {
146 opp-hz = /bits/ 64 <700000000>;
147 opp-microvolt = <975000>;
148 clock-latency-ns = <140000>;
149 };
150 opp-600000000 {
151 opp-hz = /bits/ 64 <600000000>;
152 opp-microvolt = <937500>;
153 clock-latency-ns = <140000>;
154 };
155 };
157 soc: soc {
158 cci: cci@10d20000 {
159 compatible = "arm,cci-400";
160 #address-cells = <1>;
161 #size-cells = <1>;
162 reg = <0x10d20000 0x1000>;
163 ranges = <0x0 0x10d20000 0x6000>;
165 cci_control0: slave-if@4000 {
166 compatible = "arm,cci-400-ctrl-if";
167 interface-type = "ace";
168 reg = <0x4000 0x1000>;
169 };
170 cci_control1: slave-if@5000 {
171 compatible = "arm,cci-400-ctrl-if";
172 interface-type = "ace";
173 reg = <0x5000 0x1000>;
174 };
175 };
177 clock: clock-controller@10010000 {
178 compatible = "samsung,exynos5420-clock";
179 reg = <0x10010000 0x30000>;
180 #clock-cells = <1>;
181 };
183 clock_audss: audss-clock-controller@3810000 {
184 compatible = "samsung,exynos5420-audss-clock";
185 reg = <0x03810000 0x0C>;
186 #clock-cells = <1>;
187 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
188 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
189 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
190 power-domains = <&mau_pd>;
191 };
193 mfc: codec@11000000 {
194 compatible = "samsung,mfc-v7";
195 reg = <0x11000000 0x10000>;
196 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&clock CLK_MFC>;
198 clock-names = "mfc";
199 power-domains = <&mfc_pd>;
200 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
201 iommu-names = "left", "right";
202 };
204 mmc_0: mmc@12200000 {
205 compatible = "samsung,exynos5420-dw-mshc-smu";
206 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 reg = <0x12200000 0x2000>;
210 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
211 clock-names = "biu", "ciu";
212 fifo-depth = <0x40>;
213 status = "disabled";
214 };
216 mmc_1: mmc@12210000 {
217 compatible = "samsung,exynos5420-dw-mshc-smu";
218 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
219 #address-cells = <1>;
220 #size-cells = <0>;
221 reg = <0x12210000 0x2000>;
222 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
223 clock-names = "biu", "ciu";
224 fifo-depth = <0x40>;
225 status = "disabled";
226 };
228 mmc_2: mmc@12220000 {
229 compatible = "samsung,exynos5420-dw-mshc";
230 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233 reg = <0x12220000 0x1000>;
234 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
235 clock-names = "biu", "ciu";
236 fifo-depth = <0x40>;
237 status = "disabled";
238 };
240 nocp_mem0_0: nocp@10ca1000 {
241 compatible = "samsung,exynos5420-nocp";
242 reg = <0x10CA1000 0x200>;
243 status = "disabled";
244 };
246 nocp_mem0_1: nocp@10ca1400 {
247 compatible = "samsung,exynos5420-nocp";
248 reg = <0x10CA1400 0x200>;
249 status = "disabled";
250 };
252 nocp_mem1_0: nocp@10ca1800 {
253 compatible = "samsung,exynos5420-nocp";
254 reg = <0x10CA1800 0x200>;
255 status = "disabled";
256 };
258 nocp_mem1_1: nocp@10ca1c00 {
259 compatible = "samsung,exynos5420-nocp";
260 reg = <0x10CA1C00 0x200>;
261 status = "disabled";
262 };
264 nocp_g3d_0: nocp@11a51000 {
265 compatible = "samsung,exynos5420-nocp";
266 reg = <0x11A51000 0x200>;
267 status = "disabled";
268 };
270 nocp_g3d_1: nocp@11a51400 {
271 compatible = "samsung,exynos5420-nocp";
272 reg = <0x11A51400 0x200>;
273 status = "disabled";
274 };
276 gsc_pd: power-domain@10044000 {
277 compatible = "samsung,exynos4210-pd";
278 reg = <0x10044000 0x20>;
279 #power-domain-cells = <0>;
280 label = "GSC";
281 };
283 isp_pd: power-domain@10044020 {
284 compatible = "samsung,exynos4210-pd";
285 reg = <0x10044020 0x20>;
286 #power-domain-cells = <0>;
287 label = "ISP";
288 };
290 mfc_pd: power-domain@10044060 {
291 compatible = "samsung,exynos4210-pd";
292 reg = <0x10044060 0x20>;
293 #power-domain-cells = <0>;
294 label = "MFC";
295 };
297 msc_pd: power-domain@10044120 {
298 compatible = "samsung,exynos4210-pd";
299 reg = <0x10044120 0x20>;
300 #power-domain-cells = <0>;
301 label = "MSC";
302 };
304 disp_pd: power-domain@100440c0 {
305 compatible = "samsung,exynos4210-pd";
306 reg = <0x100440C0 0x20>;
307 #power-domain-cells = <0>;
308 label = "DISP";
309 };
311 mau_pd: power-domain@100440e0 {
312 compatible = "samsung,exynos4210-pd";
313 reg = <0x100440E0 0x20>;
314 #power-domain-cells = <0>;
315 label = "MAU";
316 };
318 pinctrl_0: pinctrl@13400000 {
319 compatible = "samsung,exynos5420-pinctrl";
320 reg = <0x13400000 0x1000>;
321 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
323 wakeup-interrupt-controller {
324 compatible = "samsung,exynos4210-wakeup-eint";
325 interrupt-parent = <&gic>;
326 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
327 };
328 };
330 pinctrl_1: pinctrl@13410000 {
331 compatible = "samsung,exynos5420-pinctrl";
332 reg = <0x13410000 0x1000>;
333 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
334 };
336 pinctrl_2: pinctrl@14000000 {
337 compatible = "samsung,exynos5420-pinctrl";
338 reg = <0x14000000 0x1000>;
339 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
340 };
342 pinctrl_3: pinctrl@14010000 {
343 compatible = "samsung,exynos5420-pinctrl";
344 reg = <0x14010000 0x1000>;
345 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
346 };
348 pinctrl_4: pinctrl@3860000 {
349 compatible = "samsung,exynos5420-pinctrl";
350 reg = <0x03860000 0x1000>;
351 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
352 power-domains = <&mau_pd>;
353 };
355 amba {
356 #address-cells = <1>;
357 #size-cells = <1>;
358 compatible = "simple-bus";
359 interrupt-parent = <&gic>;
360 ranges;
362 adma: adma@3880000 {
363 compatible = "arm,pl330", "arm,primecell";
364 reg = <0x03880000 0x1000>;
365 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&clock_audss EXYNOS_ADMA>;
367 clock-names = "apb_pclk";
368 #dma-cells = <1>;
369 #dma-channels = <6>;
370 #dma-requests = <16>;
371 power-domains = <&mau_pd>;
372 };
374 pdma0: pdma@121a0000 {
375 compatible = "arm,pl330", "arm,primecell";
376 reg = <0x121A0000 0x1000>;
377 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&clock CLK_PDMA0>;
379 clock-names = "apb_pclk";
380 #dma-cells = <1>;
381 #dma-channels = <8>;
382 #dma-requests = <32>;
383 };
385 pdma1: pdma@121b0000 {
386 compatible = "arm,pl330", "arm,primecell";
387 reg = <0x121B0000 0x1000>;
388 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&clock CLK_PDMA1>;
390 clock-names = "apb_pclk";
391 #dma-cells = <1>;
392 #dma-channels = <8>;
393 #dma-requests = <32>;
394 };
396 mdma0: mdma@10800000 {
397 compatible = "arm,pl330", "arm,primecell";
398 reg = <0x10800000 0x1000>;
399 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&clock CLK_MDMA0>;
401 clock-names = "apb_pclk";
402 #dma-cells = <1>;
403 #dma-channels = <8>;
404 #dma-requests = <1>;
405 };
407 mdma1: mdma@11c10000 {
408 compatible = "arm,pl330", "arm,primecell";
409 reg = <0x11C10000 0x1000>;
410 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&clock CLK_MDMA1>;
412 clock-names = "apb_pclk";
413 #dma-cells = <1>;
414 #dma-channels = <8>;
415 #dma-requests = <1>;
416 /*
417 * MDMA1 can support both secure and non-secure
418 * AXI transactions. When this is enabled in
419 * the kernel for boards that run in secure
420 * mode, we are getting imprecise external
421 * aborts causing the kernel to oops.
422 */
423 status = "disabled";
424 };
425 };
427 i2s0: i2s@3830000 {
428 compatible = "samsung,exynos5420-i2s";
429 reg = <0x03830000 0x100>;
430 dmas = <&adma 0
431 &adma 2
432 &adma 1>;
433 dma-names = "tx", "rx", "tx-sec";
434 clocks = <&clock_audss EXYNOS_I2S_BUS>,
435 <&clock_audss EXYNOS_I2S_BUS>,
436 <&clock_audss EXYNOS_SCLK_I2S>;
437 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
438 #clock-cells = <1>;
439 clock-output-names = "i2s_cdclk0";
440 #sound-dai-cells = <1>;
441 samsung,idma-addr = <0x03000000>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&i2s0_bus>;
444 power-domains = <&mau_pd>;
445 status = "disabled";
446 };
448 i2s1: i2s@12d60000 {
449 compatible = "samsung,exynos5420-i2s";
450 reg = <0x12D60000 0x100>;
451 dmas = <&pdma1 12
452 &pdma1 11>;
453 dma-names = "tx", "rx";
454 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
455 clock-names = "iis", "i2s_opclk0";
456 #clock-cells = <1>;
457 clock-output-names = "i2s_cdclk1";
458 #sound-dai-cells = <1>;
459 pinctrl-names = "default";
460 pinctrl-0 = <&i2s1_bus>;
461 status = "disabled";
462 };
464 i2s2: i2s@12d70000 {
465 compatible = "samsung,exynos5420-i2s";
466 reg = <0x12D70000 0x100>;
467 dmas = <&pdma0 12
468 &pdma0 11>;
469 dma-names = "tx", "rx";
470 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
471 clock-names = "iis", "i2s_opclk0";
472 #clock-cells = <1>;
473 clock-output-names = "i2s_cdclk2";
474 #sound-dai-cells = <1>;
475 pinctrl-names = "default";
476 pinctrl-0 = <&i2s2_bus>;
477 status = "disabled";
478 };
480 spi_0: spi@12d20000 {
481 compatible = "samsung,exynos4210-spi";
482 reg = <0x12d20000 0x100>;
483 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
484 dmas = <&pdma0 5
485 &pdma0 4>;
486 dma-names = "tx", "rx";
487 #address-cells = <1>;
488 #size-cells = <0>;
489 pinctrl-names = "default";
490 pinctrl-0 = <&spi0_bus>;
491 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
492 clock-names = "spi", "spi_busclk0";
493 status = "disabled";
494 };
496 spi_1: spi@12d30000 {
497 compatible = "samsung,exynos4210-spi";
498 reg = <0x12d30000 0x100>;
499 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
500 dmas = <&pdma1 5
501 &pdma1 4>;
502 dma-names = "tx", "rx";
503 #address-cells = <1>;
504 #size-cells = <0>;
505 pinctrl-names = "default";
506 pinctrl-0 = <&spi1_bus>;
507 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
508 clock-names = "spi", "spi_busclk0";
509 status = "disabled";
510 };
512 spi_2: spi@12d40000 {
513 compatible = "samsung,exynos4210-spi";
514 reg = <0x12d40000 0x100>;
515 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
516 dmas = <&pdma0 7
517 &pdma0 6>;
518 dma-names = "tx", "rx";
519 #address-cells = <1>;
520 #size-cells = <0>;
521 pinctrl-names = "default";
522 pinctrl-0 = <&spi2_bus>;
523 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
524 clock-names = "spi", "spi_busclk0";
525 status = "disabled";
526 };
528 dp_phy: dp-video-phy {
529 compatible = "samsung,exynos5420-dp-video-phy";
530 samsung,pmu-syscon = <&pmu_system_controller>;
531 #phy-cells = <0>;
532 };
534 mipi_phy: mipi-video-phy {
535 compatible = "samsung,s5pv210-mipi-video-phy";
536 syscon = <&pmu_system_controller>;
537 #phy-cells = <1>;
538 };
540 dsi@14500000 {
541 compatible = "samsung,exynos5410-mipi-dsi";
542 reg = <0x14500000 0x10000>;
543 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
544 phys = <&mipi_phy 1>;
545 phy-names = "dsim";
546 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
547 clock-names = "bus_clk", "pll_clk";
548 #address-cells = <1>;
549 #size-cells = <0>;
550 status = "disabled";
551 };
553 hsi2c_8: i2c@12e00000 {
554 compatible = "samsung,exynos5250-hsi2c";
555 reg = <0x12E00000 0x1000>;
556 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
557 #address-cells = <1>;
558 #size-cells = <0>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&i2c8_hs_bus>;
561 clocks = <&clock CLK_USI4>;
562 clock-names = "hsi2c";
563 status = "disabled";
564 };
566 hsi2c_9: i2c@12e10000 {
567 compatible = "samsung,exynos5250-hsi2c";
568 reg = <0x12E10000 0x1000>;
569 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
570 #address-cells = <1>;
571 #size-cells = <0>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&i2c9_hs_bus>;
574 clocks = <&clock CLK_USI5>;
575 clock-names = "hsi2c";
576 status = "disabled";
577 };
579 hsi2c_10: i2c@12e20000 {
580 compatible = "samsung,exynos5250-hsi2c";
581 reg = <0x12E20000 0x1000>;
582 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
583 #address-cells = <1>;
584 #size-cells = <0>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&i2c10_hs_bus>;
587 clocks = <&clock CLK_USI6>;
588 clock-names = "hsi2c";
589 status = "disabled";
590 };
592 hdmi: hdmi@14530000 {
593 compatible = "samsung,exynos5420-hdmi";
594 reg = <0x14530000 0x70000>;
595 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
597 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
598 <&clock CLK_MOUT_HDMI>;
599 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
600 "sclk_hdmiphy", "mout_hdmi";
601 phy = <&hdmiphy>;
602 samsung,syscon-phandle = <&pmu_system_controller>;
603 status = "disabled";
604 power-domains = <&disp_pd>;
605 #sound-dai-cells = <0>;
606 };
608 hdmiphy: hdmiphy@145d0000 {
609 reg = <0x145D0000 0x20>;
610 };
612 hdmicec: cec@101b0000 {
613 compatible = "samsung,s5p-cec";
614 reg = <0x101B0000 0x200>;
615 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&clock CLK_HDMI_CEC>;
617 clock-names = "hdmicec";
618 samsung,syscon-phandle = <&pmu_system_controller>;
619 hdmi-phandle = <&hdmi>;
620 pinctrl-names = "default";
621 pinctrl-0 = <&hdmi_cec>;
622 status = "disabled";
623 };
625 mixer: mixer@14450000 {
626 compatible = "samsung,exynos5420-mixer";
627 reg = <0x14450000 0x10000>;
628 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
630 <&clock CLK_SCLK_HDMI>;
631 clock-names = "mixer", "hdmi", "sclk_hdmi";
632 power-domains = <&disp_pd>;
633 iommus = <&sysmmu_tv>;
634 status = "disabled";
635 };
637 rotator: rotator@11c00000 {
638 compatible = "samsung,exynos5250-rotator";
639 reg = <0x11C00000 0x64>;
640 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&clock CLK_ROTATOR>;
642 clock-names = "rotator";
643 iommus = <&sysmmu_rotator>;
644 };
646 gsc_0: video-scaler@13e00000 {
647 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
648 reg = <0x13e00000 0x1000>;
649 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
650 clocks = <&clock CLK_GSCL0>;
651 clock-names = "gscl";
652 power-domains = <&gsc_pd>;
653 iommus = <&sysmmu_gscl0>;
654 };
656 gsc_1: video-scaler@13e10000 {
657 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
658 reg = <0x13e10000 0x1000>;
659 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&clock CLK_GSCL1>;
661 clock-names = "gscl";
662 power-domains = <&gsc_pd>;
663 iommus = <&sysmmu_gscl1>;
664 };
666 scaler_0: scaler@12800000 {
667 compatible = "samsung,exynos5420-scaler";
668 reg = <0x12800000 0x1294>;
669 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&clock CLK_MSCL0>;
671 clock-names = "mscl";
672 power-domains = <&msc_pd>;
673 iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>;
674 };
676 scaler_1: scaler@12810000 {
677 compatible = "samsung,exynos5420-scaler";
678 reg = <0x12810000 0x1294>;
679 interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&clock CLK_MSCL1>;
681 clock-names = "mscl";
682 power-domains = <&msc_pd>;
683 iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>;
684 };
686 scaler_2: scaler@12820000 {
687 compatible = "samsung,exynos5420-scaler";
688 reg = <0x12820000 0x1294>;
689 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&clock CLK_MSCL2>;
691 clock-names = "mscl";
692 power-domains = <&msc_pd>;
693 iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>;
694 };
696 jpeg_0: jpeg@11f50000 {
697 compatible = "samsung,exynos5420-jpeg";
698 reg = <0x11F50000 0x1000>;
699 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
700 clock-names = "jpeg";
701 clocks = <&clock CLK_JPEG>;
702 iommus = <&sysmmu_jpeg0>;
703 };
705 jpeg_1: jpeg@11f60000 {
706 compatible = "samsung,exynos5420-jpeg";
707 reg = <0x11F60000 0x1000>;
708 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
709 clock-names = "jpeg";
710 clocks = <&clock CLK_JPEG2>;
711 iommus = <&sysmmu_jpeg1>;
712 };
714 pmu_system_controller: system-controller@10040000 {
715 compatible = "samsung,exynos5420-pmu", "syscon";
716 reg = <0x10040000 0x5000>;
717 clock-names = "clkout16";
718 clocks = <&clock CLK_FIN_PLL>;
719 #clock-cells = <1>;
720 interrupt-controller;
721 #interrupt-cells = <3>;
722 interrupt-parent = <&gic>;
723 };
725 tmu_cpu0: tmu@10060000 {
726 compatible = "samsung,exynos5420-tmu";
727 reg = <0x10060000 0x100>;
728 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&clock CLK_TMU>;
730 clock-names = "tmu_apbif";
731 #thermal-sensor-cells = <0>;
732 };
734 tmu_cpu1: tmu@10064000 {
735 compatible = "samsung,exynos5420-tmu";
736 reg = <0x10064000 0x100>;
737 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
738 clocks = <&clock CLK_TMU>;
739 clock-names = "tmu_apbif";
740 #thermal-sensor-cells = <0>;
741 };
743 tmu_cpu2: tmu@10068000 {
744 compatible = "samsung,exynos5420-tmu-ext-triminfo";
745 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
746 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
748 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
749 #thermal-sensor-cells = <0>;
750 };
752 tmu_cpu3: tmu@1006c000 {
753 compatible = "samsung,exynos5420-tmu-ext-triminfo";
754 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
755 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
757 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
758 #thermal-sensor-cells = <0>;
759 };
761 tmu_gpu: tmu@100a0000 {
762 compatible = "samsung,exynos5420-tmu-ext-triminfo";
763 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
764 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
766 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
767 #thermal-sensor-cells = <0>;
768 };
770 sysmmu_g2dr: sysmmu@10a60000 {
771 compatible = "samsung,exynos-sysmmu";
772 reg = <0x10A60000 0x1000>;
773 interrupt-parent = <&combiner>;
774 interrupts = <24 5>;
775 clock-names = "sysmmu", "master";
776 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
777 #iommu-cells = <0>;
778 };
780 sysmmu_g2dw: sysmmu@10a70000 {
781 compatible = "samsung,exynos-sysmmu";
782 reg = <0x10A70000 0x1000>;
783 interrupt-parent = <&combiner>;
784 interrupts = <22 2>;
785 clock-names = "sysmmu", "master";
786 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
787 #iommu-cells = <0>;
788 };
790 sysmmu_tv: sysmmu@14650000 {
791 compatible = "samsung,exynos-sysmmu";
792 reg = <0x14650000 0x1000>;
793 interrupt-parent = <&combiner>;
794 interrupts = <7 4>;
795 clock-names = "sysmmu", "master";
796 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
797 power-domains = <&disp_pd>;
798 #iommu-cells = <0>;
799 };
801 sysmmu_gscl0: sysmmu@13e80000 {
802 compatible = "samsung,exynos-sysmmu";
803 reg = <0x13E80000 0x1000>;
804 interrupt-parent = <&combiner>;
805 interrupts = <2 0>;
806 clock-names = "sysmmu", "master";
807 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
808 power-domains = <&gsc_pd>;
809 #iommu-cells = <0>;
810 };
812 sysmmu_gscl1: sysmmu@13e90000 {
813 compatible = "samsung,exynos-sysmmu";
814 reg = <0x13E90000 0x1000>;
815 interrupt-parent = <&combiner>;
816 interrupts = <2 2>;
817 clock-names = "sysmmu", "master";
818 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
819 power-domains = <&gsc_pd>;
820 #iommu-cells = <0>;
821 };
823 sysmmu_scaler0r: sysmmu@12880000 {
824 compatible = "samsung,exynos-sysmmu";
825 reg = <0x12880000 0x1000>;
826 interrupt-parent = <&combiner>;
827 interrupts = <22 4>;
828 clock-names = "sysmmu", "master";
829 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
830 power-domains = <&msc_pd>;
831 #iommu-cells = <0>;
832 };
834 sysmmu_scaler1r: sysmmu@12890000 {
835 compatible = "samsung,exynos-sysmmu";
836 reg = <0x12890000 0x1000>;
837 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
838 clock-names = "sysmmu", "master";
839 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
840 power-domains = <&msc_pd>;
841 #iommu-cells = <0>;
842 };
844 sysmmu_scaler2r: sysmmu@128a0000 {
845 compatible = "samsung,exynos-sysmmu";
846 reg = <0x128A0000 0x1000>;
847 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
848 clock-names = "sysmmu", "master";
849 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
850 power-domains = <&msc_pd>;
851 #iommu-cells = <0>;
852 };
854 sysmmu_scaler0w: sysmmu@128c0000 {
855 compatible = "samsung,exynos-sysmmu";
856 reg = <0x128C0000 0x1000>;
857 interrupt-parent = <&combiner>;
858 interrupts = <27 2>;
859 clock-names = "sysmmu", "master";
860 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
861 power-domains = <&msc_pd>;
862 #iommu-cells = <0>;
863 };
865 sysmmu_scaler1w: sysmmu@128d0000 {
866 compatible = "samsung,exynos-sysmmu";
867 reg = <0x128D0000 0x1000>;
868 interrupt-parent = <&combiner>;
869 interrupts = <22 6>;
870 clock-names = "sysmmu", "master";
871 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
872 power-domains = <&msc_pd>;
873 #iommu-cells = <0>;
874 };
876 sysmmu_scaler2w: sysmmu@128e0000 {
877 compatible = "samsung,exynos-sysmmu";
878 reg = <0x128E0000 0x1000>;
879 interrupt-parent = <&combiner>;
880 interrupts = <19 6>;
881 clock-names = "sysmmu", "master";
882 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
883 power-domains = <&msc_pd>;
884 #iommu-cells = <0>;
885 };
887 sysmmu_rotator: sysmmu@11d40000 {
888 compatible = "samsung,exynos-sysmmu";
889 reg = <0x11D40000 0x1000>;
890 interrupt-parent = <&combiner>;
891 interrupts = <4 0>;
892 clock-names = "sysmmu", "master";
893 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
894 #iommu-cells = <0>;
895 };
897 sysmmu_jpeg0: sysmmu@11f10000 {
898 compatible = "samsung,exynos-sysmmu";
899 reg = <0x11F10000 0x1000>;
900 interrupt-parent = <&combiner>;
901 interrupts = <4 2>;
902 clock-names = "sysmmu", "master";
903 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
904 #iommu-cells = <0>;
905 };
907 sysmmu_jpeg1: sysmmu@11f20000 {
908 compatible = "samsung,exynos-sysmmu";
909 reg = <0x11F20000 0x1000>;
910 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
911 clock-names = "sysmmu", "master";
912 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
913 #iommu-cells = <0>;
914 };
916 sysmmu_mfc_l: sysmmu@11200000 {
917 compatible = "samsung,exynos-sysmmu";
918 reg = <0x11200000 0x1000>;
919 interrupt-parent = <&combiner>;
920 interrupts = <6 2>;
921 clock-names = "sysmmu", "master";
922 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
923 power-domains = <&mfc_pd>;
924 #iommu-cells = <0>;
925 };
927 sysmmu_mfc_r: sysmmu@11210000 {
928 compatible = "samsung,exynos-sysmmu";
929 reg = <0x11210000 0x1000>;
930 interrupt-parent = <&combiner>;
931 interrupts = <8 5>;
932 clock-names = "sysmmu", "master";
933 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
934 power-domains = <&mfc_pd>;
935 #iommu-cells = <0>;
936 };
938 sysmmu_fimd1_0: sysmmu@14640000 {
939 compatible = "samsung,exynos-sysmmu";
940 reg = <0x14640000 0x1000>;
941 interrupt-parent = <&combiner>;
942 interrupts = <3 2>;
943 clock-names = "sysmmu", "master";
944 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
945 power-domains = <&disp_pd>;
946 #iommu-cells = <0>;
947 };
949 sysmmu_fimd1_1: sysmmu@14680000 {
950 compatible = "samsung,exynos-sysmmu";
951 reg = <0x14680000 0x1000>;
952 interrupt-parent = <&combiner>;
953 interrupts = <3 0>;
954 clock-names = "sysmmu", "master";
955 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
956 power-domains = <&disp_pd>;
957 #iommu-cells = <0>;
958 };
960 bus_wcore: bus_wcore {
961 compatible = "samsung,exynos-bus";
962 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
963 clock-names = "bus";
964 operating-points-v2 = <&bus_wcore_opp_table>;
965 status = "disabled";
966 };
968 bus_noc: bus_noc {
969 compatible = "samsung,exynos-bus";
970 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
971 clock-names = "bus";
972 operating-points-v2 = <&bus_noc_opp_table>;
973 status = "disabled";
974 };
976 bus_fsys_apb: bus_fsys_apb {
977 compatible = "samsung,exynos-bus";
978 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
979 clock-names = "bus";
980 operating-points-v2 = <&bus_fsys_apb_opp_table>;
981 status = "disabled";
982 };
984 bus_fsys: bus_fsys {
985 compatible = "samsung,exynos-bus";
986 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
987 clock-names = "bus";
988 operating-points-v2 = <&bus_fsys_apb_opp_table>;
989 status = "disabled";
990 };
992 bus_fsys2: bus_fsys2 {
993 compatible = "samsung,exynos-bus";
994 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
995 clock-names = "bus";
996 operating-points-v2 = <&bus_fsys2_opp_table>;
997 status = "disabled";
998 };
1000 bus_mfc: bus_mfc {
1001 compatible = "samsung,exynos-bus";
1002 clocks = <&clock CLK_DOUT_ACLK333>;
1003 clock-names = "bus";
1004 operating-points-v2 = <&bus_mfc_opp_table>;
1005 status = "disabled";
1006 };
1008 bus_gen: bus_gen {
1009 compatible = "samsung,exynos-bus";
1010 clocks = <&clock CLK_DOUT_ACLK266>;
1011 clock-names = "bus";
1012 operating-points-v2 = <&bus_gen_opp_table>;
1013 status = "disabled";
1014 };
1016 bus_peri: bus_peri {
1017 compatible = "samsung,exynos-bus";
1018 clocks = <&clock CLK_DOUT_ACLK66>;
1019 clock-names = "bus";
1020 operating-points-v2 = <&bus_peri_opp_table>;
1021 status = "disabled";
1022 };
1024 bus_g2d: bus_g2d {
1025 compatible = "samsung,exynos-bus";
1026 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1027 clock-names = "bus";
1028 operating-points-v2 = <&bus_g2d_opp_table>;
1029 status = "disabled";
1030 };
1032 bus_g2d_acp: bus_g2d_acp {
1033 compatible = "samsung,exynos-bus";
1034 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1035 clock-names = "bus";
1036 operating-points-v2 = <&bus_g2d_acp_opp_table>;
1037 status = "disabled";
1038 };
1040 bus_jpeg: bus_jpeg {
1041 compatible = "samsung,exynos-bus";
1042 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1043 clock-names = "bus";
1044 operating-points-v2 = <&bus_jpeg_opp_table>;
1045 status = "disabled";
1046 };
1048 bus_jpeg_apb: bus_jpeg_apb {
1049 compatible = "samsung,exynos-bus";
1050 clocks = <&clock CLK_DOUT_ACLK166>;
1051 clock-names = "bus";
1052 operating-points-v2 = <&bus_jpeg_apb_opp_table>;
1053 status = "disabled";
1054 };
1056 bus_disp1_fimd: bus_disp1_fimd {
1057 compatible = "samsung,exynos-bus";
1058 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1059 clock-names = "bus";
1060 operating-points-v2 = <&bus_disp1_fimd_opp_table>;
1061 status = "disabled";
1062 };
1064 bus_disp1: bus_disp1 {
1065 compatible = "samsung,exynos-bus";
1066 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1067 clock-names = "bus";
1068 operating-points-v2 = <&bus_disp1_opp_table>;
1069 status = "disabled";
1070 };
1072 bus_gscl_scaler: bus_gscl_scaler {
1073 compatible = "samsung,exynos-bus";
1074 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1075 clock-names = "bus";
1076 operating-points-v2 = <&bus_gscl_opp_table>;
1077 status = "disabled";
1078 };
1080 bus_mscl: bus_mscl {
1081 compatible = "samsung,exynos-bus";
1082 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1083 clock-names = "bus";
1084 operating-points-v2 = <&bus_mscl_opp_table>;
1085 status = "disabled";
1086 };
1088 bus_wcore_opp_table: opp_table2 {
1089 compatible = "operating-points-v2";
1091 opp00 {
1092 opp-hz = /bits/ 64 <84000000>;
1093 opp-microvolt = <925000>;
1094 };
1095 opp01 {
1096 opp-hz = /bits/ 64 <111000000>;
1097 opp-microvolt = <950000>;
1098 };
1099 opp02 {
1100 opp-hz = /bits/ 64 <222000000>;
1101 opp-microvolt = <950000>;
1102 };
1103 opp03 {
1104 opp-hz = /bits/ 64 <333000000>;
1105 opp-microvolt = <950000>;
1106 };
1107 opp04 {
1108 opp-hz = /bits/ 64 <400000000>;
1109 opp-microvolt = <987500>;
1110 };
1111 };
1113 bus_noc_opp_table: opp_table3 {
1114 compatible = "operating-points-v2";
1116 opp00 {
1117 opp-hz = /bits/ 64 <67000000>;
1118 };
1119 opp01 {
1120 opp-hz = /bits/ 64 <75000000>;
1121 };
1122 opp02 {
1123 opp-hz = /bits/ 64 <86000000>;
1124 };
1125 opp03 {
1126 opp-hz = /bits/ 64 <100000000>;
1127 };
1128 };
1130 bus_fsys_apb_opp_table: opp_table4 {
1131 compatible = "operating-points-v2";
1132 opp-shared;
1134 opp00 {
1135 opp-hz = /bits/ 64 <100000000>;
1136 };
1137 opp01 {
1138 opp-hz = /bits/ 64 <200000000>;
1139 };
1140 };
1142 bus_fsys2_opp_table: opp_table5 {
1143 compatible = "operating-points-v2";
1145 opp00 {
1146 opp-hz = /bits/ 64 <75000000>;
1147 };
1148 opp01 {
1149 opp-hz = /bits/ 64 <100000000>;
1150 };
1151 opp02 {
1152 opp-hz = /bits/ 64 <150000000>;
1153 };
1154 };
1156 bus_mfc_opp_table: opp_table6 {
1157 compatible = "operating-points-v2";
1159 opp00 {
1160 opp-hz = /bits/ 64 <96000000>;
1161 };
1162 opp01 {
1163 opp-hz = /bits/ 64 <111000000>;
1164 };
1165 opp02 {
1166 opp-hz = /bits/ 64 <167000000>;
1167 };
1168 opp03 {
1169 opp-hz = /bits/ 64 <222000000>;
1170 };
1171 opp04 {
1172 opp-hz = /bits/ 64 <333000000>;
1173 };
1174 };
1176 bus_gen_opp_table: opp_table7 {
1177 compatible = "operating-points-v2";
1179 opp00 {
1180 opp-hz = /bits/ 64 <89000000>;
1181 };
1182 opp01 {
1183 opp-hz = /bits/ 64 <133000000>;
1184 };
1185 opp02 {
1186 opp-hz = /bits/ 64 <178000000>;
1187 };
1188 opp03 {
1189 opp-hz = /bits/ 64 <267000000>;
1190 };
1191 };
1193 bus_peri_opp_table: opp_table8 {
1194 compatible = "operating-points-v2";
1196 opp00 {
1197 opp-hz = /bits/ 64 <67000000>;
1198 };
1199 };
1201 bus_g2d_opp_table: opp_table9 {
1202 compatible = "operating-points-v2";
1204 opp00 {
1205 opp-hz = /bits/ 64 <84000000>;
1206 };
1207 opp01 {
1208 opp-hz = /bits/ 64 <167000000>;
1209 };
1210 opp02 {
1211 opp-hz = /bits/ 64 <222000000>;
1212 };
1213 opp03 {
1214 opp-hz = /bits/ 64 <300000000>;
1215 };
1216 opp04 {
1217 opp-hz = /bits/ 64 <333000000>;
1218 };
1219 };
1221 bus_g2d_acp_opp_table: opp_table10 {
1222 compatible = "operating-points-v2";
1224 opp00 {
1225 opp-hz = /bits/ 64 <67000000>;
1226 };
1227 opp01 {
1228 opp-hz = /bits/ 64 <133000000>;
1229 };
1230 opp02 {
1231 opp-hz = /bits/ 64 <178000000>;
1232 };
1233 opp03 {
1234 opp-hz = /bits/ 64 <267000000>;
1235 };
1236 };
1238 bus_jpeg_opp_table: opp_table11 {
1239 compatible = "operating-points-v2";
1241 opp00 {
1242 opp-hz = /bits/ 64 <75000000>;
1243 };
1244 opp01 {
1245 opp-hz = /bits/ 64 <150000000>;
1246 };
1247 opp02 {
1248 opp-hz = /bits/ 64 <200000000>;
1249 };
1250 opp03 {
1251 opp-hz = /bits/ 64 <300000000>;
1252 };
1253 };
1255 bus_jpeg_apb_opp_table: opp_table12 {
1256 compatible = "operating-points-v2";
1258 opp00 {
1259 opp-hz = /bits/ 64 <84000000>;
1260 };
1261 opp01 {
1262 opp-hz = /bits/ 64 <111000000>;
1263 };
1264 opp02 {
1265 opp-hz = /bits/ 64 <134000000>;
1266 };
1267 opp03 {
1268 opp-hz = /bits/ 64 <167000000>;
1269 };
1270 };
1272 bus_disp1_fimd_opp_table: opp_table13 {
1273 compatible = "operating-points-v2";
1275 opp00 {
1276 opp-hz = /bits/ 64 <120000000>;
1277 };
1278 opp01 {
1279 opp-hz = /bits/ 64 <200000000>;
1280 };
1281 };
1283 bus_disp1_opp_table: opp_table14 {
1284 compatible = "operating-points-v2";
1286 opp00 {
1287 opp-hz = /bits/ 64 <120000000>;
1288 };
1289 opp01 {
1290 opp-hz = /bits/ 64 <200000000>;
1291 };
1292 opp02 {
1293 opp-hz = /bits/ 64 <300000000>;
1294 };
1295 };
1297 bus_gscl_opp_table: opp_table15 {
1298 compatible = "operating-points-v2";
1300 opp00 {
1301 opp-hz = /bits/ 64 <150000000>;
1302 };
1303 opp01 {
1304 opp-hz = /bits/ 64 <200000000>;
1305 };
1306 opp02 {
1307 opp-hz = /bits/ 64 <300000000>;
1308 };
1309 };
1311 bus_mscl_opp_table: opp_table16 {
1312 compatible = "operating-points-v2";
1314 opp00 {
1315 opp-hz = /bits/ 64 <84000000>;
1316 };
1317 opp01 {
1318 opp-hz = /bits/ 64 <167000000>;
1319 };
1320 opp02 {
1321 opp-hz = /bits/ 64 <222000000>;
1322 };
1323 opp03 {
1324 opp-hz = /bits/ 64 <333000000>;
1325 };
1326 opp04 {
1327 opp-hz = /bits/ 64 <400000000>;
1328 };
1329 };
1330 };
1332 thermal-zones {
1333 cpu0_thermal: cpu0-thermal {
1334 thermal-sensors = <&tmu_cpu0>;
1335 #include "exynos5420-trip-points.dtsi"
1336 };
1337 cpu1_thermal: cpu1-thermal {
1338 thermal-sensors = <&tmu_cpu1>;
1339 #include "exynos5420-trip-points.dtsi"
1340 };
1341 cpu2_thermal: cpu2-thermal {
1342 thermal-sensors = <&tmu_cpu2>;
1343 #include "exynos5420-trip-points.dtsi"
1344 };
1345 cpu3_thermal: cpu3-thermal {
1346 thermal-sensors = <&tmu_cpu3>;
1347 #include "exynos5420-trip-points.dtsi"
1348 };
1349 gpu_thermal: gpu-thermal {
1350 thermal-sensors = <&tmu_gpu>;
1351 #include "exynos5420-trip-points.dtsi"
1352 };
1353 };
1354 };
1356 &adc {
1357 clocks = <&clock CLK_TSADC>;
1358 clock-names = "adc";
1359 samsung,syscon-phandle = <&pmu_system_controller>;
1360 };
1362 &dp {
1363 clocks = <&clock CLK_DP1>;
1364 clock-names = "dp";
1365 phys = <&dp_phy>;
1366 phy-names = "dp";
1367 power-domains = <&disp_pd>;
1368 };
1370 &fimd {
1371 compatible = "samsung,exynos5420-fimd";
1372 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1373 clock-names = "sclk_fimd", "fimd";
1374 power-domains = <&disp_pd>;
1375 iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1376 iommu-names = "m0", "m1";
1377 };
1379 &g2d {
1380 iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>;
1381 clocks = <&clock CLK_G2D>;
1382 clock-names = "fimg2d";
1383 status = "okay";
1384 };
1386 &i2c_0 {
1387 clocks = <&clock CLK_I2C0>;
1388 clock-names = "i2c";
1389 pinctrl-names = "default";
1390 pinctrl-0 = <&i2c0_bus>;
1391 };
1393 &i2c_1 {
1394 clocks = <&clock CLK_I2C1>;
1395 clock-names = "i2c";
1396 pinctrl-names = "default";
1397 pinctrl-0 = <&i2c1_bus>;
1398 };
1400 &i2c_2 {
1401 clocks = <&clock CLK_I2C2>;
1402 clock-names = "i2c";
1403 pinctrl-names = "default";
1404 pinctrl-0 = <&i2c2_bus>;
1405 };
1407 &i2c_3 {
1408 clocks = <&clock CLK_I2C3>;
1409 clock-names = "i2c";
1410 pinctrl-names = "default";
1411 pinctrl-0 = <&i2c3_bus>;
1412 };
1414 &hsi2c_4 {
1415 clocks = <&clock CLK_USI0>;
1416 clock-names = "hsi2c";
1417 pinctrl-names = "default";
1418 pinctrl-0 = <&i2c4_hs_bus>;
1419 };
1421 &hsi2c_5 {
1422 clocks = <&clock CLK_USI1>;
1423 clock-names = "hsi2c";
1424 pinctrl-names = "default";
1425 pinctrl-0 = <&i2c5_hs_bus>;
1426 };
1428 &hsi2c_6 {
1429 clocks = <&clock CLK_USI2>;
1430 clock-names = "hsi2c";
1431 pinctrl-names = "default";
1432 pinctrl-0 = <&i2c6_hs_bus>;
1433 };
1435 &hsi2c_7 {
1436 clocks = <&clock CLK_USI3>;
1437 clock-names = "hsi2c";
1438 pinctrl-names = "default";
1439 pinctrl-0 = <&i2c7_hs_bus>;
1440 };
1442 &mct {
1443 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1444 clock-names = "fin_pll", "mct";
1445 };
1447 &prng {
1448 clocks = <&clock CLK_SSS>;
1449 clock-names = "secss";
1450 };
1452 &pwm {
1453 clocks = <&clock CLK_PWM>;
1454 clock-names = "timers";
1455 };
1457 &rtc {
1458 clocks = <&clock CLK_RTC>;
1459 clock-names = "rtc";
1460 interrupt-parent = <&pmu_system_controller>;
1461 status = "disabled";
1462 };
1464 &serial_0 {
1465 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1466 clock-names = "uart", "clk_uart_baud0";
1467 dmas = <&pdma0 13>, <&pdma0 14>;
1468 dma-names = "rx", "tx";
1469 };
1471 &serial_1 {
1472 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1473 clock-names = "uart", "clk_uart_baud0";
1474 dmas = <&pdma1 15>, <&pdma1 16>;
1475 dma-names = "rx", "tx";
1476 };
1478 &serial_2 {
1479 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1480 clock-names = "uart", "clk_uart_baud0";
1481 dmas = <&pdma0 15>, <&pdma0 16>;
1482 dma-names = "rx", "tx";
1483 };
1485 &serial_3 {
1486 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1487 clock-names = "uart", "clk_uart_baud0";
1488 dmas = <&pdma1 17>, <&pdma1 18>;
1489 dma-names = "rx", "tx";
1490 };
1492 &sss {
1493 clocks = <&clock CLK_SSS>;
1494 clock-names = "secss";
1495 };
1497 &trng {
1498 clocks = <&clock CLK_SSS>;
1499 clock-names = "secss";
1500 };
1502 &usbdrd3_0 {
1503 clocks = <&clock CLK_USBD300>;
1504 clock-names = "usbdrd30";
1505 };
1507 &usbdrd_phy0 {
1508 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1509 clock-names = "phy", "ref";
1510 samsung,pmu-syscon = <&pmu_system_controller>;
1511 };
1513 &usbdrd3_1 {
1514 clocks = <&clock CLK_USBD301>;
1515 clock-names = "usbdrd30";
1516 };
1518 &usbdrd_dwc3_1 {
1519 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1520 };
1522 &usbdrd_phy1 {
1523 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1524 clock-names = "phy", "ref";
1525 samsung,pmu-syscon = <&pmu_system_controller>;
1526 };
1528 &usbhost1 {
1529 clocks = <&clock CLK_USBH20>;
1530 clock-names = "usbhost";
1531 };
1533 &usbhost2 {
1534 clocks = <&clock CLK_USBH20>;
1535 clock-names = "usbhost";
1536 };
1538 &usb2_phy {
1539 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1540 clock-names = "phy", "ref";
1541 samsung,sysreg-phandle = <&sysreg_system_controller>;
1542 samsung,pmureg-phandle = <&pmu_system_controller>;
1543 };
1545 &watchdog {
1546 clocks = <&clock CLK_WDT>;
1547 clock-names = "watchdog";
1548 samsung,syscon-phandle = <&pmu_system_controller>;
1549 };
1551 #include "exynos5420-pinctrl.dtsi"
1552 #include "exynos-syscon-restart.dtsi"