arch/arm/boot/dts/imx6qdl-gw551x.dtsi

   1 /*
   2  * Copyright 2014 Gateworks Corporation
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/gpio/gpio.h>
  49 #include <dt-bindings/media/tda1997x.h>
  50 #include <dt-bindings/sound/fsl-imx-audmux.h>
  51
  52 / {
  53         /* these are used by bootloader for disabling nodes */
  54         aliases {
  55                 led0 = &led0;
  56                 nand = &gpmi;
  57                 ssi0 = &ssi1;
  58                 usb0 = &usbh1;
  59                 usb1 = &usbotg;
  60         };
  61
  62         chosen {
  63                 bootargs = "console=ttymxc1,115200";
  64         };
  65
  66         leds {
  67                 compatible = "gpio-leds";
  68                 pinctrl-names = "default";
  69                 pinctrl-0 = <&pinctrl_gpio_leds>;
  70
  71                 led0: user1 {
  72                         label = "user1";
  73                         gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
  74                         default-state = "on";
  75                         linux,default-trigger = "heartbeat";
  76                 };
  77         };
  78
  79         memory@10000000 {
  80                 device_type = "memory";
  81                 reg = <0x10000000 0x20000000>;
  82         };
  83
  84         reg_5p0v: regulator-5p0v {
  85                 compatible = "regulator-fixed";
  86                 regulator-name = "5P0V";
  87                 regulator-min-microvolt = <5000000>;
  88                 regulator-max-microvolt = <5000000>;
  89         };
  90
  91         reg_usb_h1_vbus: regulator-usb-h1-vbus {
  92                 compatible = "regulator-fixed";
  93                 regulator-name = "usb_h1_vbus";
  94                 regulator-min-microvolt = <5000000>;
  95                 regulator-max-microvolt = <5000000>;
  96         };
  97
  98         reg_usb_otg_vbus: regulator-usb-otg-vbus {
  99                 compatible = "regulator-fixed";
 100                 regulator-name = "usb_otg_vbus";
 101                 regulator-min-microvolt = <5000000>;
 102                 regulator-max-microvolt = <5000000>;
 103         };
 104
 105         sound-digital {
 106                 compatible = "simple-audio-card";
 107                 simple-audio-card,name = "tda1997x-audio";
 108
 109                 simple-audio-card,dai-link@0 {
 110                         format = "i2s";
 111
 112                         cpu {
 113                                 sound-dai = <&ssi2>;
 114                         };
 115
 116                         codec {
 117                                 bitclock-master;
 118                                 frame-master;
 119                                 sound-dai = <&hdmi_receiver>;
 120                         };
 121                 };
 122         };
 123 };
 124
 125 &audmux {
 126         pinctrl-names = "default";
 127         pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */
 128         status = "okay";
 129
 130         ssi1 {
 131                 fsl,audmux-port = <0>;
 132                 fsl,port-config = <
 133                         (IMX_AUDMUX_V2_PTCR_TFSDIR |
 134                         IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
 135                         IMX_AUDMUX_V2_PTCR_TCLKDIR |
 136                         IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
 137                         IMX_AUDMUX_V2_PTCR_SYN)
 138                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
 139                 >;
 140         };
 141
 142         aud5 {
 143                 fsl,audmux-port = <4>;
 144                 fsl,port-config = <
 145                         IMX_AUDMUX_V2_PTCR_SYN
 146                         IMX_AUDMUX_V2_PDCR_RXDSEL(0)>;
 147         };
 148 };
 149
 150 &can1 {
 151         pinctrl-names = "default";
 152         pinctrl-0 = <&pinctrl_flexcan1>;
 153         status = "okay";
 154 };
 155
 156 &gpmi {
 157         pinctrl-names = "default";
 158         pinctrl-0 = <&pinctrl_gpmi_nand>;
 159         status = "okay";
 160 };
 161
 162 &hdmi {
 163         ddc-i2c-bus = <&i2c3>;
 164         status = "okay";
 165 };
 166
 167 &i2c1 {
 168         clock-frequency = <100000>;
 169         pinctrl-names = "default";
 170         pinctrl-0 = <&pinctrl_i2c1>;
 171         status = "okay";
 172
 173         eeprom1: eeprom@50 {
 174                 compatible = "atmel,24c02";
 175                 reg = <0x50>;
 176                 pagesize = <16>;
 177         };
 178
 179         eeprom2: eeprom@51 {
 180                 compatible = "atmel,24c02";
 181                 reg = <0x51>;
 182                 pagesize = <16>;
 183         };
 184
 185         eeprom3: eeprom@52 {
 186                 compatible = "atmel,24c02";
 187                 reg = <0x52>;
 188                 pagesize = <16>;
 189         };
 190
 191         eeprom4: eeprom@53 {
 192                 compatible = "atmel,24c02";
 193                 reg = <0x53>;
 194                 pagesize = <16>;
 195         };
 196
 197         gpio: pca9555@23 {
 198                 compatible = "nxp,pca9555";
 199                 reg = <0x23>;
 200                 gpio-controller;
 201                 #gpio-cells = <2>;
 202         };
 203
 204         rtc: ds1672@68 {
 205                 compatible = "dallas,ds1672";
 206                 reg = <0x68>;
 207         };
 208 };
 209
 210 &i2c2 {
 211         clock-frequency = <100000>;
 212         pinctrl-names = "default";
 213         pinctrl-0 = <&pinctrl_i2c2>;
 214         status = "okay";
 215
 216         ltc3676: pmic@3c {
 217                 compatible = "lltc,ltc3676";
 218                 reg = <0x3c>;
 219                 pinctrl-names = "default";
 220                 pinctrl-0 = <&pinctrl_pmic>;
 221                 interrupt-parent = <&gpio1>;
 222                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 223
 224                 regulators {
 225                         /* VDD_SOC (1+R1/R2 = 1.635) */
 226                         reg_vdd_soc: sw1 {
 227                                 regulator-name = "vddsoc";
 228                                 regulator-min-microvolt = <674400>;
 229                                 regulator-max-microvolt = <1308000>;
 230                                 lltc,fb-voltage-divider = <127000 200000>;
 231                                 regulator-ramp-delay = <7000>;
 232                                 regulator-boot-on;
 233                                 regulator-always-on;
 234                         };
 235
 236                         /* VDD_DDR (1+R1/R2 = 2.105) */
 237                         reg_vdd_ddr: sw2 {
 238                                 regulator-name = "vddddr";
 239                                 regulator-min-microvolt = <868310>;
 240                                 regulator-max-microvolt = <1684000>;
 241                                 lltc,fb-voltage-divider = <221000 200000>;
 242                                 regulator-ramp-delay = <7000>;
 243                                 regulator-boot-on;
 244                                 regulator-always-on;
 245                         };
 246
 247                         /* VDD_ARM (1+R1/R2 = 1.635) */
 248                         reg_vdd_arm: sw3 {
 249                                 regulator-name = "vddarm";
 250                                 regulator-min-microvolt = <674400>;
 251                                 regulator-max-microvolt = <1308000>;
 252                                 lltc,fb-voltage-divider = <127000 200000>;
 253                                 regulator-ramp-delay = <7000>;
 254                                 regulator-boot-on;
 255                                 regulator-always-on;
 256                         };
 257
 258                         /* VDD_3P3 (1+R1/R2 = 1.281) */
 259                         reg_3p3: sw4 {
 260                                 regulator-name = "vdd3p3";
 261                                 regulator-min-microvolt = <1880000>;
 262                                 regulator-max-microvolt = <3647000>;
 263                                 lltc,fb-voltage-divider = <200000 56200>;
 264                                 regulator-ramp-delay = <7000>;
 265                                 regulator-boot-on;
 266                                 regulator-always-on;
 267                         };
 268
 269                         /* VDD_1P8a (1+R1/R2 = 2.505): HDMI In core */
 270                         reg_1p8a: ldo2 {
 271                                 regulator-name = "vdd1p8a";
 272                                 regulator-min-microvolt = <1816125>;
 273                                 regulator-max-microvolt = <1816125>;
 274                                 lltc,fb-voltage-divider = <301000 200000>;
 275                                 regulator-boot-on;
 276                                 regulator-always-on;
 277                         };
 278
 279                         /* VDD_1P8b: HDMI In analog */
 280                         reg_1p8b: ldo3 {
 281                                 regulator-name = "vdd1p8b";
 282                                 regulator-min-microvolt = <1800000>;
 283                                 regulator-max-microvolt = <1800000>;
 284                                 regulator-boot-on;
 285                         };
 286
 287                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 288                         reg_3p0: ldo4 {
 289                                 regulator-name = "vdd3p0";
 290                                 regulator-min-microvolt = <3023250>;
 291                                 regulator-max-microvolt = <3023250>;
 292                                 lltc,fb-voltage-divider = <634000 200000>;
 293                                 regulator-boot-on;
 294                                 regulator-always-on;
 295                         };
 296                 };
 297         };
 298 };
 299
 300 &i2c3 {
 301         clock-frequency = <100000>;
 302         pinctrl-names = "default";
 303         pinctrl-0 = <&pinctrl_i2c3>;
 304         status = "okay";
 305
 306         gpio_exp: pca9555@24 {
 307                 compatible = "nxp,pca9555";
 308                 reg = <0x24>;
 309                 gpio-controller;
 310                 #gpio-cells = <2>;
 311         };
 312
 313         hdmi_receiver: hdmi-receiver@48 {
 314                 compatible = "nxp,tda19971";
 315                 pinctrl-names = "default";
 316                 pinctrl-0 = <&pinctrl_tda1997x>;
 317                 reg = <0x48>;
 318                 interrupt-parent = <&gpio1>;
 319                 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
 320                 DOVDD-supply = <&reg_3p3>;
 321                 AVDD-supply = <&reg_1p8b>;
 322                 DVDD-supply = <&reg_1p8a>;
 323                 #sound-dai-cells = <0>;
 324                 nxp,audout-format = "i2s";
 325                 nxp,audout-layout = <0>;
 326                 nxp,audout-width = <16>;
 327                 nxp,audout-mclk-fs = <128>;
 328                 /*
 329                  * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
 330                  * and Y[11:4] across 16bits in the same cycle
 331                  * which we map to VP[15:08]<->CSI_DATA[19:12]
 332                  */
 333                 nxp,vidout-portcfg =
 334                         /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
 335                         < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
 336                         /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
 337                         < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
 338                         /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
 339                         < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
 340                         /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
 341                         < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
 342
 343                 port {
 344                         tda1997x_to_ipu1_csi0_mux: endpoint {
 345                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 346                                 bus-width = <16>;
 347                                 hsync-active = <1>;
 348                                 vsync-active = <1>;
 349                                 data-active = <1>;
 350                         };
 351                 };
 352         };
 353 };
 354
 355 &ipu1_csi0_from_ipu1_csi0_mux {
 356         bus-width = <16>;
 357 };
 358
 359 &ipu1_csi0_mux_from_parallel_sensor {
 360         remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
 361         bus-width = <16>;
 362 };
 363
 364 &ipu1_csi0 {
 365         pinctrl-names = "default";
 366         pinctrl-0 = <&pinctrl_ipu1_csi0>;
 367 };
 368
 369 &pcie {
 370         pinctrl-names = "default";
 371         pinctrl-0 = <&pinctrl_pcie>;
 372         reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 373         status = "okay";
 374 };
 375
 376 &pwm2 {
 377         pinctrl-names = "default";
 378         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 379         status = "disabled";
 380 };
 381
 382 &pwm3 {
 383         pinctrl-names = "default";
 384         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 385         status = "disabled";
 386 };
 387
 388 &ssi1 {
 389         status = "okay";
 390 };
 391
 392 &uart2 {
 393         pinctrl-names = "default";
 394         pinctrl-0 = <&pinctrl_uart2>;
 395         status = "okay";
 396 };
 397
 398 &uart3 {
 399         pinctrl-names = "default";
 400         pinctrl-0 = <&pinctrl_uart3>;
 401         status = "okay";
 402 };
 403
 404 &usbotg {
 405         vbus-supply = <&reg_usb_otg_vbus>;
 406         pinctrl-names = "default";
 407         pinctrl-0 = <&pinctrl_usbotg>;
 408         disable-over-current;
 409         status = "okay";
 410 };
 411
 412 &usbh1 {
 413         vbus-supply = <&reg_usb_h1_vbus>;
 414         status = "okay";
 415 };
 416
 417 &wdog1 {
 418         pinctrl-names = "default";
 419         pinctrl-0 = <&pinctrl_wdog>;
 420         fsl,ext-reset-output;
 421 };
 422
 423 &iomuxc {
 424         pinctrl_audmux: audmuxgrp {
 425                 fsl,pins = <
 426                         MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
 427                         MX6QDL_PAD_DISP0_DAT14__AUD5_RXC        0x130b0
 428                         MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS       0x130b0
 429                 >;
 430         };
 431
 432         pinctrl_flexcan1: flexcan1grp {
 433                 fsl,pins = <
 434                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
 435                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
 436                         MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x4001b0b0 /* CAN_STBY */
 437                 >;
 438         };
 439
 440         pinctrl_gpio_leds: gpioledsgrp {
 441                 fsl,pins = <
 442                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07   0x1b0b0
 443                 >;
 444         };
 445
 446         pinctrl_gpmi_nand: gpminandgrp {
 447                 fsl,pins = <
 448                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 449                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 450                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 451                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 452                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 453                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 454                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 455                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 456                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 457                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 458                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 459                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 460                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 461                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 462                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 463                 >;
 464         };
 465
 466         pinctrl_i2c1: i2c1grp {
 467                 fsl,pins = <
 468                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 469                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 470                 >;
 471         };
 472
 473         pinctrl_i2c2: i2c2grp {
 474                 fsl,pins = <
 475                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 476                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 477                 >;
 478         };
 479
 480         pinctrl_i2c3: i2c3grp {
 481                 fsl,pins = <
 482                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 483                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 484                 >;
 485         };
 486
 487         pinctrl_ipu1_csi0: ipu1_csi0grp {
 488                 fsl,pins = <
 489                         MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04          0x1b0b0
 490                         MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05          0x1b0b0
 491                         MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06          0x1b0b0
 492                         MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07          0x1b0b0
 493                         MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08          0x1b0b0
 494                         MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09          0x1b0b0
 495                         MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10         0x1b0b0
 496                         MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11         0x1b0b0
 497                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12         0x1b0b0
 498                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13         0x1b0b0
 499                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14         0x1b0b0
 500                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15         0x1b0b0
 501                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16         0x1b0b0
 502                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17         0x1b0b0
 503                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18         0x1b0b0
 504                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19         0x1b0b0
 505                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC           0x1b0b0
 506                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK        0x1b0b0
 507                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC          0x1b0b0
 508                 >;
 509         };
 510
 511         pinctrl_pcie: pciegrp {
 512                 fsl,pins = <
 513                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0 /* PCIE RST */
 514                 >;
 515         };
 516
 517         pinctrl_pmic: pmicgrp {
 518                 fsl,pins = <
 519                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
 520                 >;
 521         };
 522
 523         pinctrl_pwm2: pwm2grp {
 524                 fsl,pins = <
 525                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 526                 >;
 527         };
 528
 529         pinctrl_pwm3: pwm3grp {
 530                 fsl,pins = <
 531                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 532                 >;
 533         };
 534
 535         pinctrl_tda1997x: tda1997xgrp {
 536                 fsl,pins = <
 537                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0
 538                 >;
 539         };
 540
 541         pinctrl_uart2: uart2grp {
 542                 fsl,pins = <
 543                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 544                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 545                 >;
 546         };
 547
 548         pinctrl_uart3: uart3grp {
 549                 fsl,pins = <
 550                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 551                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 552                 >;
 553         };
 554
 555         pinctrl_usbotg: usbotggrp {
 556                 fsl,pins = <
 557                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 558                 >;
 559         };
 560
 561         pinctrl_wdog: wdoggrp {
 562                 fsl,pins = <
 563                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 564                 >;
 565         };
 566 };