arch/arm/boot/dts/imx6ul-phytec-pcl063.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016 PHYTEC Messtechnik GmbH
   4  * Author: Christian Hemp <c.hemp@phytec.de>
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/pwm/pwm.h>
  10 #include "imx6ul.dtsi"
  11
  12 / {
  13         model = "Phytec phyCORE i.MX6 UltraLite";
  14         compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
  15
  16         chosen {
  17                 stdout-path = &uart1;
  18         };
  19
  20         /*
  21          * Set the minimum memory size here and
  22          * let the bootloader set the real size.
  23          */
  24         memory {
  25                 device_type = "memory";
  26                 reg = <0x80000000 0x8000000>;
  27         };
  28
  29         gpio_leds_som: leds {
  30                 pinctrl-names = "default";
  31                 pinctrl-0 = <&pinctrl_gpioleds_som>;
  32                 compatible = "gpio-leds";
  33
  34                 led_green {
  35                         label = "phycore:green";
  36                         gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
  37                         linux,default-trigger = "heartbeat";
  38                 };
  39         };
  40 };
  41
  42 &fec1 {
  43         pinctrl-names = "default";
  44         pinctrl-0 = <&pinctrl_enet1>;
  45         phy-mode = "rmii";
  46         phy-handle = <&ethphy0>;
  47         status = "okay";
  48
  49         mdio: mdio {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 ethphy0: ethernet-phy@1 {
  54                         reg = <1>;
  55                         interrupt-parent = <&gpio1>;
  56                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
  57                         micrel,led-mode = <1>;
  58                         clocks = <&clks IMX6UL_CLK_ENET_REF>;
  59                         clock-names = "rmii-ref";
  60                 };
  61         };
  62 };
  63
  64 &gpmi {
  65         pinctrl-names = "default";
  66         pinctrl-0 = <&pinctrl_gpmi_nand>;
  67         nand-on-flash-bbt;
  68         status = "okay";
  69 };
  70
  71 &i2c1 {
  72         pinctrl-names = "default";
  73         pinctrl-0 =<&pinctrl_i2c1>;
  74         clock-frequency = <100000>;
  75         status = "okay";
  76
  77         eeprom@52 {
  78                 compatible = "catalyst,24c32", "atmel,24c32";
  79                 reg = <0x52>;
  80         };
  81 };
  82
  83 &snvs_poweroff {
  84         status = "okay";
  85 };
  86
  87 &uart1 {
  88         pinctrl-names = "default";
  89         pinctrl-0 = <&pinctrl_uart1>;
  90         status = "okay";
  91 };
  92
  93 &iomuxc {
  94         pinctrl_enet1: enet1grp {
  95                 fsl,pins = <
  96                         MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x1b0b0
  97                         MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
  98                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
  99                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
 100                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 101                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 102                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 103                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 104                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 105                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
 106                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x17059
 107                 >;
 108         };
 109
 110         pinctrl_gpioleds_som: gpioledssomgrp {
 111                 fsl,pins = <MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04  0x0b0b0>;
 112         };
 113
 114         pinctrl_gpmi_nand: gpminandgrp {
 115                 fsl,pins = <
 116                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
 117                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
 118                         MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
 119                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
 120                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
 121                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
 122                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
 123                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
 124                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
 125                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
 126                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
 127                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
 128                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
 129                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
 130                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
 131                 >;
 132         };
 133
 134         pinctrl_i2c1: i2cgrp {
 135                 fsl,pins = <
 136                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL       0x4001b8b0
 137                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA       0x4001b8b0
 138                 >;
 139         };
 140
 141         pinctrl_uart1: uart1grp {
 142                 fsl,pins = <
 143                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
 144                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
 145                 >;
 146         };
 147
 148 };