arch/arm/boot/dts/imx6ul-phytec-phyboard-segin-full.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016 PHYTEC Messtechnik GmbH
   4  * Author: Christian Hemp <c.hemp@phytec.de>
   5  */
   6
   7 /dts-v1/;
   8 #include "imx6ul-phytec-pcl063.dtsi"
   9 #include "imx6ul-phytec-phyboard-segin.dtsi"
  10 #include "imx6ul-phytec-peb-eval-01.dtsi"
  11
  12 / {
  13         model = "Phytec phyBOARD-Segin i.MX6 UltraLite Full Featured";
  14         compatible = "phytec,imx6ul-pbacd10", "phytec,imx6ul-pcl063", "fsl,imx6ul";
  15 };
  16
  17 &adc1 {
  18         status = "okay";
  19 };
  20
  21 &can1 {
  22         status = "okay";
  23 };
  24
  25 &tlv320 {
  26         status = "okay";
  27 };
  28
  29 &ecspi3 {
  30         pinctrl-names = "default";
  31         pinctrl-0 = <&pinctrl_ecspi3>;
  32         cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
  33         status = "okay";
  34 };
  35
  36 &fec2 {
  37         status = "okay";
  38 };
  39
  40 &i2c_rtc {
  41         status = "okay";
  42 };
  43
  44 &reg_can1_en {
  45         status = "okay";
  46 };
  47
  48 &reg_sound_1v8 {
  49         status = "okay";
  50 };
  51
  52 &reg_sound_3v3 {
  53         status = "okay";
  54 };
  55
  56 &sai2 {
  57         status = "okay";
  58 };
  59
  60 &sound {
  61         status = "okay";
  62 };
  63
  64 &uart5 {
  65         status = "okay";
  66 };
  67
  68 &usbotg1 {
  69         status = "okay";
  70 };
  71
  72 &usbotg2 {
  73         status = "okay";
  74 };
  75
  76 &usdhc1 {
  77         status = "okay";
  78 };
  79
  80 &iomuxc {
  81         pinctrl_ecspi3: ecspi3grp {
  82                 fsl,pins = <
  83                         MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO      0x10b0
  84                         MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI      0x10b0
  85                         MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK    0x10b0
  86                         MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20     0x10b0
  87                 >;
  88         };
  89 };